coreboot-gerrit August 2018

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Change in coreboot[master]: acpi/gnvs: delay setting chromeos_apci_t.vdat until depthcharge
by Joel Kitching (Code Review) 31 Aug '18

31 Aug '18

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/28407 Change subject: acpi/gnvs: delay setting chromeos_apci_t.vdat until depthcharge ...................................................................... acpi/gnvs: delay setting chromeos_apci_t.vdat until depthcharge Standardize on using vboot_handoff data structure for transferring data between coreboot and depthcharge. chromeos_acpi_t.vdat is undefined until set in depthcharge. BUG=b:112288216 TEST=compile and run on eve CQ-DEPEND=CL:1198814 Change-Id: Iccc021334d3c6f0145dffd5ca05beb9e430378a9 Signed-off-by: Joel Kitching <kitching(a)gmail.com> --- M src/vendorcode/google/chromeos/gnvs.c 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/28407/1 diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index f21eb09..86ba4f3 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -37,12 +37,6 @@ /* Copy saved ME hash into NVS */ memcpy(chromeos_acpi->mehh, me_hash_saved, sizeof(chromeos_acpi->mehh)); - struct vboot_handoff *vboot_handoff; - - if (vboot_get_handoff_info((void **)&vboot_handoff, NULL) == 0) - memcpy(&chromeos_acpi->vdat[0], &vboot_handoff->shared_data[0], - ARRAY_SIZE(chromeos_acpi->vdat)); - chromeos_ram_oops_init(chromeos_acpi); } -- To view, visit https://review.coreboot.org/28407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iccc021334d3c6f0145dffd5ca05beb9e430378a9 Gerrit-Change-Number: 28407 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com>

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Change in coreboot[master]: chromeos/gnvs: remove function and naming cleanup
by Joel Kitching (Code Review) 31 Aug '18

31 Aug '18

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/28406 Change subject: chromeos/gnvs: remove function and naming cleanup ...................................................................... chromeos/gnvs: remove function and naming cleanup - Remove unused acpi_get_chromeos_acpi_info (see CL:28190) - Make function naming in gnvs.h consistent (start with "chromeos_") BUG=b:112288216 TEST=compile and run on eve Change-Id: I5b0066bc311b0ea995fa30bca1cd9235dc9b7d1b Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/arch/x86/smbios.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/skylake/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/lynxpoint/lpc.c M src/vendorcode/google/chromeos/gnvs.c M src/vendorcode/google/chromeos/gnvs.h 12 files changed, 15 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/28406/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 103b4ae..fc3a0a7 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -367,7 +367,8 @@ #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) /* SMBIOS offsets start at 1 rather than 0 */ - acpi_get_chromeos_acpi()->vbt10 = (u32)t->eos + (version_offset - 1); + chromeos_get_chromeos_acpi()->vbt10 = + (u32)t->eos + (version_offset - 1); #endif #endif /* CONFIG_CHROMEOS */ diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 4094c38..3881042 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -273,7 +273,7 @@ if (IS_ENABLED(CONFIG_CHROMEOS)) { /* Initialize Verified Boot data */ - chromeos_init_vboot(&gnvs->chromeos); + chromeos_init_chromeos_acpi(&gnvs->chromeos); gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; } diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 5e42091..bf93ef4 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -96,7 +96,7 @@ if (IS_ENABLED(CONFIG_CHROMEOS)) { /* Initialize Verified Boot data */ - chromeos_init_vboot(&gnvs->chromeos); + chromeos_init_chromeos_acpi(&gnvs->chromeos); gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; } diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index a43e6b6..cdf3abf 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -92,7 +92,7 @@ #if IS_ENABLED(CONFIG_CHROMEOS) /* Initialize Verified Boot data */ - chromeos_init_vboot(&(gnvs->chromeos)); + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index ebca9fa..0a683fb 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -100,7 +100,7 @@ #if IS_ENABLED(CONFIG_CHROMEOS) /* Initialize Verified Boot data */ - chromeos_init_vboot(&(gnvs->chromeos)); + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index d826d43..2d9d0b7 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -177,7 +177,7 @@ #if IS_ENABLED(CONFIG_CHROMEOS) /* Initialize Verified Boot data */ - chromeos_init_vboot(&(gnvs->chromeos)); + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 97d5ce7..155756c 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -214,7 +214,7 @@ if (IS_ENABLED(CONFIG_CHROMEOS)) { /* Initialize Verified Boot data */ - chromeos_init_vboot(&(gnvs->chromeos)); + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) { gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 44096cd..d2ec7e7 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -192,7 +192,7 @@ #if IS_ENABLED(CONFIG_CHROMEOS) /* Initialize Verified Boot data */ - chromeos_init_vboot(&(gnvs->chromeos)); + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index d9e72b4..271b5b0 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -739,7 +739,7 @@ memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); #if IS_ENABLED(CONFIG_CHROMEOS) - chromeos_init_vboot(&(gnvs->chromeos)); + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); #endif /* And tell SMI about it */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 8f695cd..5b09fed 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -770,7 +770,7 @@ gnvs->pcnt = dev_count_cpu(); #if IS_ENABLED(CONFIG_CHROMEOS) - chromeos_init_vboot(&(gnvs->chromeos)); + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); #endif /* Update the mem console pointer. */ diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 70aa899..f21eb09 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -30,7 +30,7 @@ static chromeos_acpi_t *chromeos_acpi; static u32 me_hash_saved[8]; -void chromeos_init_vboot(chromeos_acpi_t *init) +void chromeos_init_chromeos_acpi(chromeos_acpi_t *init) { chromeos_acpi = init; @@ -59,14 +59,7 @@ memcpy(me_hash_saved, hash, len*sizeof(u32)); } -void acpi_get_chromeos_acpi_info(uint64_t *chromeos_acpi_addr, - uint32_t *chromeos_acpi_size) -{ - *chromeos_acpi_addr = (intptr_t)chromeos_acpi; - *chromeos_acpi_size = sizeof(*chromeos_acpi); -} - -chromeos_acpi_t *acpi_get_chromeos_acpi(void) +chromeos_acpi_t *chromeos_get_chromeos_acpi(void) { return chromeos_acpi; } diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 62fa08c..77c2f0a 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -73,10 +73,8 @@ u8 pad[314]; // dc6-eff } __packed chromeos_acpi_t; -void chromeos_init_vboot(chromeos_acpi_t *init); +void chromeos_init_chromeos_acpi(chromeos_acpi_t *init); void chromeos_set_me_hash(u32*, int); -void acpi_get_chromeos_acpi_info(uint64_t *chromeos_acpi_addr, - uint32_t *chromeos_acpi_size); -chromeos_acpi_t *acpi_get_chromeos_acpi(void); +chromeos_acpi_t *chromeos_get_chromeos_acpi(void); #endif -- To view, visit https://review.coreboot.org/28406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5b0066bc311b0ea995fa30bca1cd9235dc9b7d1b Gerrit-Change-Number: 28406 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com>

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Change in coreboot[master]: rammus: add SPD mapping for rammus and shyvana support.
by Kane Chen (Code Review) 31 Aug '18

31 Aug '18

Kane Chen has abandoned this change. ( https://review.coreboot.org/28404 ) Change subject: rammus: add SPD mapping for rammus and shyvana support. ...................................................................... Abandoned update wrong file -- To view, visit https://review.coreboot.org/28404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Iaa70bfa31bbde5a563993d11e57afdc1d97426d5 Gerrit-Change-Number: 28404 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/opencellular/elgon: Add mainboard support
by build bot (Jenkins) (Code Review) 31 Aug '18

31 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28024 ) Change subject: mainboard/opencellular/elgon: Add mainboard support ...................................................................... Patch Set 14: (25 comments) https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… File src/mainboard/opencellular/elgon/gbcv2.dts: https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 215: reg = <0x8440 0xa0000 0x0 0x1000 0x8440 0xb0000 0x0 0x1000>; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 223: interrupts = <0x0 0x44 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4>; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 238: ranges = <0x3000000 0x8010 0x0 0x8010 0x0 0x80 0x0 0x3000000 0x8100 0x0 0x8100 0x0 0x80 0x0 0x3000000 0x8680 0x0 0x8680 0x0 0x160 0x28000000 0x3000000 0x87e0 0x2c000000 0x87e0 0x2c000000 0x0 0x94000000 0x3000000 0x8400 0x0 0x8400 0x0 0x10 0x0 0x3000000 0x8430 0x0 0x8430 0x0 0x2 0x0 0x3000000 0x87e0 0xc6000000 0x87e0 0xc6000000 0x1f 0x3a000000>; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 243: compatible = "pci-bridge", "cavium,thunder-8890-mrml-bridge"; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 246: ranges = <0x3000000 0x87e0 0x0 0x3000000 0x87e0 0x0 0x10 0x0>; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 251: compatible = "cavium,thunder-8890-mdio-nexus"; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 255: assigned-addresses = <0x3000000 0x87e0 0x5000000 0x0 0x800000>; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 256: ranges = <0x87e0 0x5000000 0x3000000 0x87e0 0x5000000 0x0 0x800000>; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 259: compatible = "cavium,thunder-8890-mdio"; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 262: reg = <0x87e0 0x5003800 0x0 0x30>; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 266: compatible = "cavium,thunder-8890-mdio"; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 269: reg = <0x87e0 0x5003880 0x0 0x30>; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 332: compatible = "infineon,slb9645tt"; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 345: local-mac-address = [00 00 00 00 00 00]; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 358: local-mac-address = [00 00 00 00 00 00]; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 379: compatible = "winbond,w25q128", "jedec,spi-nor"; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 415: reg = <0x8800 0x1f000000 0x0 0x39000000 0x87e0 0xc0000000 0x0 0x1000000>; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 416: ranges = <0x1000000 0x0 0x0 0x8830 0x0 0x0 0x10000 0x3000000 0x0 0x10000000 0x8810 0x10000000 0xf 0xf0000000 0x43000000 0x10 0x0 0x8820 0x0 0x10 0x0 0x3000000 0x87e0 0xc0000000 0x87e0 0xc0000000 0x0 0x1000000>; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 419: interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x10 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x11 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x12 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x13 0x4>; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 434: reg = <0x8840 0x57000000 0x0 0x39000000 0x87e0 0xc1000000 0x0 0x1000000>; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 435: ranges = <0x1000000 0x0 0x10000 0x8870 0x10000 0x0 0x10000 0x3000000 0x0 0x10000000 0x8850 0x10000000 0xf 0xf0000000 0x43000000 0x10 0x0 0x8860 0x0 0x10 0x0 0x3000000 0x87e0 0xc1000000 0x87e0 0xc1000000 0x0 0x1000000>; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 438: interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x14 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x15 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x16 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x17 0x4>; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 453: reg = <0x8880 0x8f000000 0x0 0x39000000 0x87e0 0xc2000000 0x0 0x1000000>; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 454: ranges = <0x1000000 0x0 0x20000 0x88b0 0x20000 0x0 0x10000 0x3000000 0x0 0x10000000 0x8890 0x10000000 0xf 0xf0000000 0x43000000 0x10 0x0 0x88a0 0x0 0x10 0x0 0x3000000 0x87e0 0xc2000000 0x87e0 0xc2000000 0x0 0x1000000>; line over 80 characters https://review.coreboot.org/#/c/28024/14/src/mainboard/opencellular/elgon/g… PS14, Line 457: interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x18 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x19 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x1a 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x1b 0x4>; line over 80 characters -- To view, visit https://review.coreboot.org/28024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9b809306cc48facbade5dc63846c4532b397e0b5 Gerrit-Change-Number: 28024 Gerrit-PatchSet: 14 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 31 Aug 2018 09:39:02 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/sifive/fu540: add CLINT support
by build bot (Jenkins) (Code Review) 31 Aug '18

31 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28355 ) Change subject: soc/sifive/fu540: add CLINT support ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/#/c/28355/6/src/soc/sifive/fu540/include/soc/cl… File src/soc/sifive/fu540/include/soc/clint.h: https://review.coreboot.org/#/c/28355/6/src/soc/sifive/fu540/include/soc/cl… PS6, Line 27: #endif adding a line without newline at end of file -- To view, visit https://review.coreboot.org/28355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibc3a8644dcb83d5697d9d6e551c7682377285116 Gerrit-Change-Number: 28355 Gerrit-PatchSet: 6 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 31 Aug 2018 08:37:32 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: rammus: add SPD mapping for rammus and shyvana support.
by Kane Chen (Code Review) 31 Aug '18

31 Aug '18

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/28404 Change subject: rammus: add SPD mapping for rammus and shyvana support. ...................................................................... rammus: add SPD mapping for rammus and shyvana support. Add MICRO 4G and 8G SPD file. BUG=none BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boot up. Change-Id: Iaa70bfa31bbde5a563993d11e57afdc1d97426d5 Signed-off-by: kane_chen <kane_chen(a)pegatron.corp-partner.google.com> --- A src/mainboard/google/poppy/spd/micron_dimm_MT52L256M32D1PF-093.spd.hex A src/mainboard/google/poppy/spd/micron_dimm_MT52L512M32D2PF-093.spd.hex M src/mainboard/google/poppy/variants/rammus/devicetree.cb 3 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/28404/1 diff --git a/src/mainboard/google/poppy/spd/micron_dimm_MT52L256M32D1PF-093.spd.hex b/src/mainboard/google/poppy/spd/micron_dimm_MT52L256M32D1PF-093.spd.hex new file mode 100644 index 0000000..9868714 --- /dev/null +++ b/src/mainboard/google/poppy/spd/micron_dimm_MT52L256M32D1PF-093.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 03 03 11 01 08 08 00 00 15 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 10 C2 08 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 5A 5C +4D 54 35 32 4C 32 35 36 4D 33 32 44 31 50 46 2D +30 39 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/micron_dimm_MT52L512M32D2PF-093.spd.hex b/src/mainboard/google/poppy/spd/micron_dimm_MT52L512M32D2PF-093.spd.hex new file mode 100644 index 0000000..715f4dc --- /dev/null +++ b/src/mainboard/google/poppy/spd/micron_dimm_MT52L512M32D2PF-093.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 0B 03 11 01 08 08 00 00 15 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 21 C2 08 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 12 81 +4D 54 35 32 4C 35 31 32 4D 33 32 44 32 50 46 2D +30 39 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 78de3ca..0e8ce4d 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -203,6 +203,10 @@ .sda_hold = 36, }, }, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, }" # Touchscreen -- To view, visit https://review.coreboot.org/28404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iaa70bfa31bbde5a563993d11e57afdc1d97426d5 Gerrit-Change-Number: 28404 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com>

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Change in coreboot[master]: [WIP] Nvidia Optimus support for ThinkPads
by Evgeny Zinoviev (Code Review) 31 Aug '18

31 Aug '18

Evgeny Zinoviev has posted comments on this change. ( https://review.coreboot.org/28380 ) Change subject: [WIP] Nvidia Optimus support for ThinkPads ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/#/c/28380/7//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28380/7//COMMIT_MSG@41 PS7, Line 41: > We could patch the Option ROM with the "correct" PCI ID. […] Oh I see. You mean we could patch it automatically. Yes, I can create a separate commit with this feature. -- To view, visit https://review.coreboot.org/28380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Gerrit-Change-Number: 28380 Gerrit-PatchSet: 9 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anonymous Coward (1002090) Gerrit-Comment-Date: Fri, 31 Aug 2018 08:13:17 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads
by Evgeny Zinoviev (Code Review) 31 Aug '18

31 Aug '18

Evgeny Zinoviev has posted comments on this change. ( https://review.coreboot.org/28393 ) Change subject: mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28393/2/src/mainboard/lenovo/t430s/romstage… File src/mainboard/lenovo/t430s/romstage.c: https://review.coreboot.org/#/c/28393/2/src/mainboard/lenovo/t430s/romstage… PS2, Line 72: enum hybrid_graphics_req mode = HYBRID_GRAPHICS_INTEGRATED; > why not using the hybrid graphics driver ? it looks like the code is the same. Just use: […] Well, here https://review.coreboot.org/c/coreboot/+/28380/2/src/mainboard/lenovo/t430s… you pointed me at "DRIVERS_LENOVO_HYBRID_GRAPHICS" in Kconfig and said that there's no hybrid graphics in this model, I thought that means "don't use it". -- To view, visit https://review.coreboot.org/28393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7 Gerrit-Change-Number: 28393 Gerrit-PatchSet: 2 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 31 Aug 2018 07:32:55 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: [WIP] Nvidia Optimus support for ThinkPads
by Evgeny Zinoviev (Code Review) 31 Aug '18

31 Aug '18

Evgeny Zinoviev has posted comments on this change. ( https://review.coreboot.org/28380 ) Change subject: [WIP] Nvidia Optimus support for ThinkPads ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/#/c/28380/7//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28380/7//COMMIT_MSG@41 PS7, Line 41: > We could patch the Option ROM with the "correct" PCI ID. […] That's exactly what I did. The vendor and device id are located right after the "PCIR" signature. -- To view, visit https://review.coreboot.org/28380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Gerrit-Change-Number: 28380 Gerrit-PatchSet: 9 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anonymous Coward (1002090) Gerrit-Comment-Date: Fri, 31 Aug 2018 07:24:32 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: [WIP] Nvidia Optimus support for ThinkPads
by Patrick Rudolph (Code Review) 31 Aug '18

31 Aug '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28380 ) Change subject: [WIP] Nvidia Optimus support for ThinkPads ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/#/c/28380/7//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28380/7//COMMIT_MSG@41 PS7, Line 41: > Yes, I edited the device id and it works now, so I guess we can remove it from the list of "known pr […] We could patch the Option ROM with the "correct" PCI ID. Where correct is the filename in CBFS / the PCI ID of the card. Intel has the same problem, there's one Option ROM for multiple GPUs with different PCI IDs... As Option ROMs aren't signed, that should be easy to do. -- To view, visit https://review.coreboot.org/28380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Gerrit-Change-Number: 28380 Gerrit-PatchSet: 9 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anonymous Coward (1002090) Gerrit-Comment-Date: Fri, 31 Aug 2018 07:18:45 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit August 2018