coreboot-gerrit June 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/intel/dg41wv: Expose some SIO devices via devicetree
by build bot (Jenkins) (Code Review) 15 Jun '18

15 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27120 ) Change subject: mb/intel/dg41wv: Expose some SIO devices via devicetree ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29087/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74989/ : SUCCESS -- To view, visit https://review.coreboot.org/27120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia658c117434c3fae45bbbe6c472ca58ba4f1a117 Gerrit-Change-Number: 27120 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 15 Jun 2018 18:05:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/lenovo/t400: Enable PCIe port on dock
by Arthur Heymans (Code Review) 15 Jun '18

15 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27121 Change subject: mb/lenovo/t400: Enable PCIe port on dock ...................................................................... mb/lenovo/t400: Enable PCIe port on dock According to the schematics the dock PCIe port is port #5. Change-Id: I2ad8a37988f2b6b5974ce0bdb565a7729e6dd15d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/devicetree.cb 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/27121/1 diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 0c72c86..268a79a 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -118,7 +118,9 @@ device pci 1c.3 on subsystemid 0x17aa 0x20f3 # Expresscard end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 + device pci 1c.4 on + subsystemid 0x17aa 0x20f3 # Dock + end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 device pci 1d.0 on # UHCI subsystemid 0x17aa 0x20f0 -- To view, visit https://review.coreboot.org/27121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2ad8a37988f2b6b5974ce0bdb565a7729e6dd15d Gerrit-Change-Number: 27121 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mb/intel/dg41wv: Expose some SIO devices via devicetree
by Arthur Heymans (Code Review) 15 Jun '18

15 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27120 Change subject: mb/intel/dg41wv: Expose some SIO devices via devicetree ...................................................................... mb/intel/dg41wv: Expose some SIO devices via devicetree Change-Id: Ia658c117434c3fae45bbbe6c472ca58ba4f1a117 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/dg41wv/acpi/superio.asl 1 file changed, 28 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/27120/1 diff --git a/src/mainboard/intel/dg41wv/acpi/superio.asl b/src/mainboard/intel/dg41wv/acpi/superio.asl index 2997587..3185a0b 100644 --- a/src/mainboard/intel/dg41wv/acpi/superio.asl +++ b/src/mainboard/intel/dg41wv/acpi/superio.asl @@ -1 +1,28 @@ -/* dummy */ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#undef W83627DHG_SHOW_UARTA +#undef W83627DHG_SHOW_UARTB +#undef W83627DHG_SHOW_KBC +#undef W83627DHG_SHOW_PS2M +#undef W83627DHG_SHOW_HWMON +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define W83627DHG_SHOW_UARTA 1 +#define W83627DHG_SHOW_UARTB 1 +#define W83627DHG_SHOW_KBC +#define W83627DHG_SHOW_PS2M +#define W83627DHG_SHOW_HWMON +#include <superio/winbond/w83627dhg/acpi/superio.asl> -- To view, visit https://review.coreboot.org/27120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia658c117434c3fae45bbbe6c472ca58ba4f1a117 Gerrit-Change-Number: 27120 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/i945: Fix domain resources
by build bot (Jenkins) (Code Review) 15 Jun '18

15 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27119 ) Change subject: nb/intel/i945: Fix domain resources ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29086/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74987/ : SUCCESS -- To view, visit https://review.coreboot.org/27119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iff5f1426015a908e988ff757055034c87085c0f5 Gerrit-Change-Number: 27119 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 15 Jun 2018 17:44:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/sandybridge: Fix domain resources
by build bot (Jenkins) (Code Review) 15 Jun '18

15 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27118 ) Change subject: nb/intel/sandybridge: Fix domain resources ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29085/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74988/ : SUCCESS -- To view, visit https://review.coreboot.org/27118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2c69ff8ec269d472f034fd79aafb337463193adf Gerrit-Change-Number: 27118 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 15 Jun 2018 17:42:35 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/i945: Fix domain resources
by Arthur Heymans (Code Review) 15 Jun '18

15 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27119 Change subject: nb/intel/i945: Fix domain resources ...................................................................... nb/intel/i945: Fix domain resources Fixed resources have to be registered early during read_resources() phase, such that device allocator will avoid them. Change-Id: Iff5f1426015a908e988ff757055034c87085c0f5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/i945/northbridge.c 1 file changed, 13 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/27119/1 diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index b8a2255..089d7e9 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -57,7 +57,7 @@ return 0; } -static void pci_domain_set_resources(struct device *dev) +static void mch_domain_read_resources(struct device *dev) { uint32_t pci_tolm, tseg_sizek; uint8_t tolud; @@ -66,6 +66,8 @@ uint64_t uma_memory_base = 0, uma_memory_size = 0; uint64_t tseg_memory_base = 0, tseg_memory_size = 0; + pci_domain_read_resources(dev); + /* Can we find out how much memory we can use at most * this way? */ @@ -113,6 +115,14 @@ ram_resource(dev, 4, 768, (tomk - 768)); uma_resource(dev, 5, uma_memory_base >> 10, uma_memory_size >> 10); mmio_resource(dev, 6, tseg_memory_base >> 10, tseg_memory_size >> 10); +} + +static void mch_domain_set_resources(struct device *dev) +{ + struct resource *res; + + for (res = dev->resource_list; res; res = res->next) + report_resource_stored(dev, res, ""); assign_resources(dev->link_list); } @@ -122,8 +132,8 @@ * See e7525/northbridge.c for an example. */ static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, + .read_resources = mch_domain_read_resources, + .set_resources = mch_domain_set_resources, .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, -- To view, visit https://review.coreboot.org/27119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iff5f1426015a908e988ff757055034c87085c0f5 Gerrit-Change-Number: 27119 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/sandybridge: Fix domain resources
by Arthur Heymans (Code Review) 15 Jun '18

15 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27118 Change subject: nb/intel/sandybridge: Fix domain resources ...................................................................... nb/intel/sandybridge: Fix domain resources Fixed resources have to be registered early during read_resources() phase, such that device allocator will avoid them. Tested on Lenovo X220, still boots. Change-Id: I2c69ff8ec269d472f034fd79aafb337463193adf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/northbridge.c 1 file changed, 13 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/27118/1 diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 8c2aaf3..645128f 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -119,13 +119,15 @@ } } -static void pci_domain_set_resources(struct device *dev) +static void mch_domain_read_resources(struct device *dev) { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; uint16_t ggc; unsigned long long tomk; + pci_domain_read_resources(dev); + /* Total Memory 2GB example: * * 00000000 0000MB-1992MB 1992MB RAM (writeback) @@ -237,6 +239,14 @@ } add_fixed_resources(dev, 6); +} + +static void mch_domain_set_resources(struct device *dev) +{ + struct resource *res; + + for (res = dev->resource_list; res; res = res->next) + report_resource_stored(dev, res, ""); assign_resources(dev->link_list); } @@ -262,8 +272,8 @@ * See e7525/northbridge.c for an example. */ static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, + .read_resources = mch_domain_read_resources, + .set_resources = mch_domain_set_resources, .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, -- To view, visit https://review.coreboot.org/27118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2c69ff8ec269d472f034fd79aafb337463193adf Gerrit-Change-Number: 27118 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/x4x: Issue a hard reset with empty MRC cache on warm reset
by build bot (Jenkins) (Code Review) 15 Jun '18

15 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27100 ) Change subject: nb/intel/x4x: Issue a hard reset with empty MRC cache on warm reset ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29084/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74986/ : SUCCESS -- To view, visit https://review.coreboot.org/27100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I405c0eca076fe081641ede9a670f734c98cbf8fc Gerrit-Change-Number: 27100 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 15 Jun 2018 16:26:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge/southbridge.c: Store PM related registers in cbmem
by build bot (Jenkins) (Code Review) 15 Jun '18

15 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27109 ) Change subject: soc/amd/stoneyridge/southbridge.c: Store PM related registers in cbmem ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29083/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74985/ : SUCCESS -- To view, visit https://review.coreboot.org/27109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib27a743b7e7f8c94918caf7ba5efd473f4054986 Gerrit-Change-Number: 27109 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 15 Jun 2018 15:37:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/Kahlee: All variants identify as Grunt in SMBIOS
by Patrick Georgi (Code Review) 15 Jun '18

15 Jun '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27117 ) Change subject: mainboard/google/Kahlee: All variants identify as Grunt in SMBIOS ...................................................................... mainboard/google/Kahlee: All variants identify as Grunt in SMBIOS All Grunt variants should identify as grunt in SMBIOS so that they're recognized correctly as a unibuild Grunt variant. BUG=b:110244268 TEST=Careena identifies as grunt Change-Id: Iaf254149fbec9551d9220018d6d6a0a1be741538 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/27117 Reviewed-by: Simon Glass <sjg(a)chromium.org> Reviewed-by: Simon Glass <sjg(a)chromium.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/kahlee/Kconfig 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Simon Glass: Looks good to me, but someone else must approve Simon Glass: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index f5ae3fb..fd43ed6 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -54,8 +54,7 @@ config MAINBOARD_PART_NUMBER string - default "Careena" if BOARD_GOOGLE_CAREENA - default "Grunt" if BOARD_GOOGLE_GRUNT + default "Grunt" config DEVICETREE string -- To view, visit https://review.coreboot.org/27117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Iaf254149fbec9551d9220018d6d6a0a1be741538 Gerrit-Change-Number: 27117 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit June 2018