coreboot-gerrit June 2018

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Change in coreboot[master]: [WIP]cbfstool: Add compression attribute
by Patrick Rudolph (Code Review) 15 Jun '18

15 Jun '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27115 Change subject: [WIP]cbfstool: Add compression attribute ...................................................................... [WIP]cbfstool: Add compression attribute Add the compression attribute to stage, payload and flat payloads. Test: The compression is shown in cbfstool coreboot.rom print instead of "none". Change-Id: I03927dcbd486602f54210a344d5cc7af2265c965 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M util/cbfstool/cbfstool.c 1 file changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/27115/1 diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 08f2e32..2b6cb31 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -614,6 +614,19 @@ ret = parse_elf_to_stage(buffer, &output, param.compression, offset, param.ignore_section); + struct cbfs_file_attr_compression *attrs = + (struct cbfs_file_attr_compression *) + cbfs_add_file_attr(header, + CBFS_FILE_ATTR_TAG_COMPRESSION, + sizeof(struct cbfs_file_attr_compression)); + if (attrs == NULL) { + buffer_delete(buffer); + return -1; + } + + attrs->compression = htonl(param.compression); + attrs->decompressed_size = htonl(buffer_size(buffer)); + if (ret != 0) return -1; buffer_delete(buffer); @@ -647,6 +660,18 @@ return -1; } + struct cbfs_file_attr_compression *attrs = + (struct cbfs_file_attr_compression *) + cbfs_add_file_attr(header, + CBFS_FILE_ATTR_TAG_COMPRESSION, + sizeof(struct cbfs_file_attr_compression)); + if (attrs == NULL) { + buffer_delete(buffer); + return -1; + } + attrs->compression = htonl(param.compression); + attrs->decompressed_size = htonl(buffer_size(buffer)); + buffer_delete(buffer); // direct assign, no dupe. memcpy(buffer, &output, sizeof(*buffer)); @@ -664,6 +689,19 @@ param.compression) != 0) { return -1; } + + struct cbfs_file_attr_compression *attrs = + (struct cbfs_file_attr_compression *) + cbfs_add_file_attr(header, + CBFS_FILE_ATTR_TAG_COMPRESSION, + sizeof(struct cbfs_file_attr_compression)); + if (attrs == NULL) { + buffer_delete(buffer); + return -1; + } + attrs->compression = htonl(param.compression); + attrs->decompressed_size = htonl(buffer_size(buffer)); + buffer_delete(buffer); // direct assign, no dupe. memcpy(buffer, &output, sizeof(*buffer)); -- To view, visit https://review.coreboot.org/27115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I03927dcbd486602f54210a344d5cc7af2265c965 Gerrit-Change-Number: 27115 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: Documentation: Add SandyBridge NRI feature matrix
by Patrick Georgi (Code Review) 15 Jun '18

15 Jun '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27093 ) Change subject: Documentation: Add SandyBridge NRI feature matrix ...................................................................... Documentation: Add SandyBridge NRI feature matrix Change-Id: I69b014430802de132c8d9b6c8409bc762b995468 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/27093 Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/northbridge/intel/sandybridge/index.md A Documentation/northbridge/intel/sandybridge/nri_features.md 2 files changed, 90 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/Documentation/northbridge/intel/sandybridge/index.md b/Documentation/northbridge/intel/sandybridge/index.md index 815abce..dcb090a 100644 --- a/Documentation/northbridge/intel/sandybridge/index.md +++ b/Documentation/northbridge/intel/sandybridge/index.md @@ -5,3 +5,4 @@ ## Topics - [Native Ram Initialization](nri.md) +- [RAM initialization feature matrix](nri_features.md) diff --git a/Documentation/northbridge/intel/sandybridge/nri_features.md b/Documentation/northbridge/intel/sandybridge/nri_features.md new file mode 100644 index 0000000..6305e78 --- /dev/null +++ b/Documentation/northbridge/intel/sandybridge/nri_features.md @@ -0,0 +1,89 @@ +# RAM initialization feature matrix + +## Options + +1. Native raminit + * Open Source + * Native Raminit is working for most frequencies on most boards. + * There might be errors to fix. + * Position in romstage doesn't matter. +2. mrc.bin raminit + * Closed Source (aka BLOB) + * No known errors. + * Needs to be placed at fixed offset in romstage. + +## Native raminit implemented features + +```eval_rst ++---------------------------+----------------------+-------------+---------+---------------------+ +| Option | Supported | Implemented | Working | Description | ++===========================+======================+=============+=========+=====================+ +| **Supported channels** | ++---------------------------+----------------------+-------------+---------+---------------------+ +| single and dual channel | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| Up to 4 slots | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| Up to 4 ranks per channel | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| **Supported frequencies** | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-1066 (533MHz) | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-1600 (800MHz) | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-1866 (933MHz) | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-2133 (1066MHz) | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-1400 (700MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-1800 (900MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-2000 (1000MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-2200 (1100MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-2400 (1200MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-1800 (900MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| **Supported CAS latencies** | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL6 | yes | yes | ? | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL7 | yes | yes | ? | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL8 | yes | yes | ? | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL9 | yes | yes | ? | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL10 | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL11 | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL12 | yes | yes | ? | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL13 | yes | yes | yes | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL14 | yes | yes | ? | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL15 | yes | yes | ? | Since coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| **MRC cache (stored timings of last training)** | ++---------------------------+----------------------+-------------+---------+---------------------+ +| S3 | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| normal boot | yes | yes | yes | reset on CRC16 diff | ++---------------------------+----------------------+-------------+---------+---------------------+ +| **XMP support** | ++---------------------------+----------------------+-------------+---------+---------------------+ +| XMP Profile 1 | yes | yes | yes | only 1.5 V profiles | ++---------------------------+----------------------+-------------+---------+---------------------+ +| XMP Profile 2 | yes | yes | no | not activated | ++---------------------------+----------------------+-------------+---------+---------------------+ +| **ECC support** | ++---------------------------+----------------------+-------------+---------+---------------------+ +| ECC | yes | no | | | ++---------------------------+----------------------+-------------+---------+---------------------+ +``` -- To view, visit https://review.coreboot.org/27093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I69b014430802de132c8d9b6c8409bc762b995468 Gerrit-Change-Number: 27093 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src: Use "foo *bar" instead of "foo* bar"
by build bot (Jenkins) (Code Review) 15 Jun '18

15 Jun '18

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Change in coreboot[master]: src: Use "foo *bar" instead of "foo* bar"
by build bot (Jenkins) (Code Review) 15 Jun '18

15 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26942 ) Change subject: src: Use "foo *bar" instead of "foo* bar" ...................................................................... Patch Set 10: (36 comments) https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h File src/device/oprom/yabel/compat/of.h: https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 38: #define p32cast (int) (unsigned long) (void *) Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 53: phandle_t of_peer(phandle_t); function definition argument 'phandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 54: phandle_t of_child(phandle_t); function definition argument 'phandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 55: phandle_t of_parent(phandle_t); function definition argument 'phandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 56: int of_getprop(phandle_t, const char *, void *, int); function definition argument 'phandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 56: int of_getprop(phandle_t, const char *, void *, int); function definition argument 'const char *' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 56: int of_getprop(phandle_t, const char *, void *, int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 56: int of_getprop(phandle_t, const char *, void *, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 57: void *of_call_method_3(const char *, ihandle_t, int); function definition argument 'const char *' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 57: void *of_call_method_3(const char *, ihandle_t, int); function definition argument 'ihandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 57: void *of_call_method_3(const char *, ihandle_t, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 60: ihandle_t of_open(const char *); function definition argument 'const char *' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 62: int of_read(ihandle_t, void *, int); function definition argument 'ihandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 62: int of_read(ihandle_t, void *, int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 62: int of_read(ihandle_t, void *, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 63: int of_write(ihandle_t, void *, int); function definition argument 'ihandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 63: int of_write(ihandle_t, void *, int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 63: int of_write(ihandle_t, void *, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 64: int of_seek(ihandle_t, int, int); function definition argument 'ihandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 64: int of_seek(ihandle_t, int, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 64: int of_seek(ihandle_t, int, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 66: void *of_claim(void *, unsigned int, unsigned int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 66: void *of_claim(void *, unsigned int, unsigned int); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 66: void *of_claim(void *, unsigned int, unsigned int); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 67: void of_release(void *, unsigned int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 67: void of_release(void *, unsigned int); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 70: void *of_set_callback(void *); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 72: int vpd_read(unsigned int, unsigned int, char *); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 72: int vpd_read(unsigned int, unsigned int, char *); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 72: int vpd_read(unsigned int, unsigned int, char *); function definition argument 'char *' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 73: int vpd_write(unsigned int, unsigned int, char *); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 73: int vpd_write(unsigned int, unsigned int, char *); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 73: int vpd_write(unsigned int, unsigned int, char *); function definition argument 'char *' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 74: int write_mm_log(char *, unsigned int, unsigned short); function definition argument 'char *' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 74: int write_mm_log(char *, unsigned int, unsigned short); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/10/src/device/oprom/yabel/compat/of.h… PS10, Line 74: int write_mm_log(char *, unsigned int, unsigned short); function definition argument 'unsigned short' should also have an identifier name -- To view, visit https://review.coreboot.org/26942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8e4118c5c5d70719ad7dc5f9ff9f86d93fa498ac Gerrit-Change-Number: 26942 Gerrit-PatchSet: 10 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 15 Jun 2018 08:01:57 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/pcengines: Remove unneeded includes and dead code
by build bot (Jenkins) (Code Review) 15 Jun '18

15 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26633 ) Change subject: mb/pcengines: Remove unneeded includes and dead code ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/74971/ : SUCCESS -- To view, visit https://review.coreboot.org/26633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id13c0ee284293c0c06d46c75c850bc7e81cfc1f6 Gerrit-Change-Number: 26633 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 15 Jun 2018 07:44:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/pcengines: Remove unneeded includes and dead code
by build bot (Jenkins) (Code Review) 15 Jun '18

15 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26633 ) Change subject: mb/pcengines: Remove unneeded includes and dead code ...................................................................... Patch Set 7: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/74970/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/29069/ : SUCCESS -- To view, visit https://review.coreboot.org/26633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id13c0ee284293c0c06d46c75c850bc7e81cfc1f6 Gerrit-Change-Number: 26633 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 15 Jun 2018 07:40:51 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: devicetree: Add method to delete property by name
by build bot (Jenkins) (Code Review) 15 Jun '18

15 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26693 ) Change subject: devicetree: Add method to delete property by name ...................................................................... Patch Set 11: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29068/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74969/ : SUCCESS -- To view, visit https://review.coreboot.org/26693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7c58a2411206bca62d0e96fa627530e937383ac9 Gerrit-Change-Number: 26693 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 15 Jun 2018 07:28:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mediatek/mt8183: Remove temporary hack of flash code.
by build bot (Jenkins) (Code Review) 15 Jun '18

15 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27114 ) Change subject: mediatek/mt8183: Remove temporary hack of flash code. ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29067/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74968/ : SUCCESS -- To view, visit https://review.coreboot.org/27114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If29869461fc8c2efe26bb8c901737ee85935d27f Gerrit-Change-Number: 27114 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 15 Jun 2018 07:09:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mediatek/mt8183: Remove temporary hack of flash code.
by Tristan Hsieh (Code Review) 15 Jun '18

15 Jun '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/27114 Change subject: mediatek/mt8183: Remove temporary hack of flash code. ...................................................................... mediatek/mt8183: Remove temporary hack of flash code. BUG=b:80501386 BRANCH=none TEST=work fine on Kukui Change-Id: If29869461fc8c2efe26bb8c901737ee85935d27f Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc D src/soc/mediatek/mt8183/flash_controller.c M src/soc/mediatek/mt8183/spi.c 3 files changed, 0 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/27114/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 9f80500..a0e4a60 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -1,24 +1,20 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8183),y) -bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += ../common/timer.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c endif -verstage-$(CONFIG_SPI_FLASH) += flash_controller.c verstage-$(CONFIG_SPI_FLASH) += spi.c verstage-y += ../common/timer.c verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c -romstage-$(CONFIG_SPI_FLASH) += flash_controller.c romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-y += ../common/timer.c romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c ramstage-y += ../common/cbmem.c emi.c -ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += ../common/timer.c ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c diff --git a/src/soc/mediatek/mt8183/flash_controller.c b/src/soc/mediatek/mt8183/flash_controller.c deleted file mode 100644 index a6a816f..0000000 --- a/src/soc/mediatek/mt8183/flash_controller.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 MediaTek Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* this is a spi driver which adapts emmc to fake spi flash */ - -#include <soc/flash_controller.h> -#include <spi_flash.h> - -static void init_io(void) -{ -} - -static int emmc_adapter_read(const struct spi_flash *flash, u32 addr, - size_t len, void *buf) -{ - return 0; -} - -static int emmc_adapter_write(const struct spi_flash *flash, u32 addr, - size_t len, const void *buf) -{ - return 0; -} - -static int emmc_adapter_erase(const struct spi_flash *flash, u32 offset, - size_t len) -{ - return 0; -} - -const struct spi_flash_ops spi_emmc_flash_ops = { - .read = emmc_adapter_read, - .write = emmc_adapter_write, - .erase = emmc_adapter_erase, -}; - -int mtk_spi_flash_probe(const struct spi_slave *spi, struct spi_flash *flash) -{ - init_io(); - - flash->name = "spi emmc flash controller"; - flash->sector_size = 0x800; - flash->size = CONFIG_ROM_SIZE; - - flash->ops = &spi_emmc_flash_ops; - return 0; -} diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c index 78821d1..d85138c 100644 --- a/src/soc/mediatek/mt8183/spi.c +++ b/src/soc/mediatek/mt8183/spi.c @@ -18,7 +18,6 @@ static const struct spi_ctrlr spi_flash_ctrlr = { .max_xfer_size = 65535, - .flash_probe = mtk_spi_flash_probe, }; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { -- To view, visit https://review.coreboot.org/27114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If29869461fc8c2efe26bb8c901737ee85935d27f Gerrit-Change-Number: 27114 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: mediatek/mt8183: Remove DRAM_DMA section.
by build bot (Jenkins) (Code Review) 15 Jun '18

15 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27113 ) Change subject: mediatek/mt8183: Remove DRAM_DMA section. ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29066/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74967/ : SUCCESS -- To view, visit https://review.coreboot.org/27113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6ba0757adbf4f1f8d2688e5ab1a36007e4e0d0fd Gerrit-Change-Number: 27113 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 15 Jun 2018 06:44:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit June 2018