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Change subject: soc/intel/{skl,kbl}: ensure C1E is disabled after S3 resume
......................................................................
Patch Set 2:
Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/75002/ : SUCCESS
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Cole Nelson has uploaded this change for review. ( https://review.coreboot.org/27125
Change subject: soc/intel/{skl,kbl}: ensure C1E is disabled after S3 resume
......................................................................
soc/intel/{skl,kbl}: ensure C1E is disabled after S3 resume
C1E is disabled by the kernel driver intel_idle at boot. This does not
address the S3 resume case, so we lose state and C1E is enabled after S3
resume.
Disable C1E for GLK as it is for APL. This gives a coherent state before
and after S3 resume.
TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3
resume with bit [1] set to zero (0x20005d).
Change-Id: I1343f343bfac9b787f13c15b812c0a201dcccb38
Signed-off-by: Cole Nelson <colex.nelson(a)intel.com>
---
M src/soc/intel/skylake/cpu.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/27125/1
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index d386d1f..3a499ce 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -310,9 +310,9 @@
msr.hi = 0;
wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
- /* Enable PROCHOT */
msr = rdmsr(MSR_POWER_CTL);
msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/
+ msr.lo &= ~POWER_CTL_C1E_MASK; /* Disable C1E */
msr.lo |= (1 << 23); /* Lock it */
wrmsr(MSR_POWER_CTL, msr);
}
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Rajmohan Mani has posted comments on this change. ( https://review.coreboot.org/27094 )
Change subject: mainboard/google/nocturne: Set camera power sequence
......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/#/c/27094/3/src/mainboard/google/poppy/variants…
File src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl:
https://review.coreboot.org/#/c/27094/3/src/mainboard/google/poppy/variants…
PS3, Line 155: Name (_CRS, ResourceTemplate ()
Since the NVM0 requires the IMX355 sensor module to be powered, we should also be adding the dependencies for the front camera power resources.
Name (_DEP, Package() { ^^I2C5.CAM0 })
Name (_PR0, Package (0x01) { ^^I2C5.CAM0.RCPR })
Name (_PR3, Package (0x01) { ^^I2C5.CAM0.RCPR })
https://review.coreboot.org/#/c/27094/3/src/mainboard/google/poppy/variants…
PS3, Line 167: 1
32
Page size is 32 bytes, per the NVM data sheet.
https://review.coreboot.org/#/c/27094/3/src/mainboard/google/poppy/variants…
File src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl:
https://review.coreboot.org/#/c/27094/3/src/mainboard/google/poppy/variants…
PS3, Line 136: 1
32
Page size is 32 bytes, per the NVM data sheet.
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Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/27094 )
Change subject: mainboard/google/nocturne: Set camera power sequence
......................................................................
Set Ready For Review
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