coreboot-gerrit June 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: [TEST]cpu/intel/p4-netburst/CAR: Test if a huge region is properly ca...
by build bot (Jenkins) (Code Review) 16 Jun '18

16 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27134 ) Change subject: [TEST]cpu/intel/p4-netburst/CAR: Test if a huge region is properly cached ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29116/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75020/ : SUCCESS -- To view, visit https://review.coreboot.org/27134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibef20c86d4377ed36ef8ad1bcff5e1eb5c9b766a Gerrit-Change-Number: 27134 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Jun 2018 22:28:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/lars, lili: Update Memory IDs
by build bot (Jenkins) (Code Review) 16 Jun '18

16 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27135 ) Change subject: google/lars,lili: Update Memory IDs ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29115/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75019/ : SUCCESS -- To view, visit https://review.coreboot.org/27135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icf6588582da3b4a7861bced539d51a914b011dc4 Gerrit-Change-Number: 27135 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Jun 2018 21:58:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/lars, lili: Update Memory IDs
by Matt DeVillier (Code Review) 16 Jun '18

16 Jun '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27135 Change subject: google/lars,lili: Update Memory IDs ...................................................................... google/lars,lili: Update Memory IDs Upstreaming Chromium commit 0bc6c43: Lili: Update Memory IDs TEST=Build and boot up on lili board Original-Change-Id: I6da1e97820b1bf2e751102384eed07236143fe2b Original-Signed-off-by: Ren Kuo <Ren.Kuo(a)quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/956782 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Change-Id: Icf6588582da3b4a7861bced539d51a914b011dc4 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/lars/spd/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/27135/1 diff --git a/src/mainboard/google/lars/spd/Makefile.inc b/src/mainboard/google/lars/spd/Makefile.inc index b6e4fd7..fff5856 100644 --- a/src/mainboard/google/lars/spd/Makefile.inc +++ b/src/mainboard/google/lars/spd/Makefile.inc @@ -31,7 +31,7 @@ SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD-1G-1866 # 0b1010 Dual Channel 4GB SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107-2G-1866 # 0b1011 Single Channel 4GB SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF-2G-1866 # 0b1100 Single Channel 4GB -SPD_SOURCES += empty # 0b1101 +SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR-NUD-2G-1866 # 0b1101 Dual Channel 8GB SPD_SOURCES += empty # 0b1110 SPD_SOURCES += empty # 0b1111 -- To view, visit https://review.coreboot.org/27135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icf6588582da3b4a7861bced539d51a914b011dc4 Gerrit-Change-Number: 27135 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quantatw.com>

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Change in coreboot[master]: [TEST]cpu/intel/p4-netburst/CAR: Test if a huge region is properly ca...
by build bot (Jenkins) (Code Review) 16 Jun '18

16 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27134 ) Change subject: [TEST]cpu/intel/p4-netburst/CAR: Test if a huge region is properly cached ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29114/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75018/ : SUCCESS -- To view, visit https://review.coreboot.org/27134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibef20c86d4377ed36ef8ad1bcff5e1eb5c9b766a Gerrit-Change-Number: 27134 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Jun 2018 20:51:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [TEST]cpu/intel/p4-netburst/CAR: Test if a huge region is properly ca...
by build bot (Jenkins) (Code Review) 16 Jun '18

16 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27134 ) Change subject: [TEST]cpu/intel/p4-netburst/CAR: Test if a huge region is properly cached ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29113/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75017/ : SUCCESS -- To view, visit https://review.coreboot.org/27134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibef20c86d4377ed36ef8ad1bcff5e1eb5c9b766a Gerrit-Change-Number: 27134 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Jun 2018 19:56:32 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [TEST]cpu/intel/p4-netburst/CAR: Test if a huge region is properly ca...
by Arthur Heymans (Code Review) 16 Jun '18

16 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27134 Change subject: [TEST]cpu/intel/p4-netburst/CAR: Test if a huge region is properly cached ...................................................................... [TEST]cpu/intel/p4-netburst/CAR: Test if a huge region is properly cached Test if a large region is properly cached to see if L2 cache is properly working. Change-Id: Ibef20c86d4377ed36ef8ad1bcff5e1eb5c9b766a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/car/romstage.c M src/cpu/intel/socket_LGA775/Kconfig 3 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/27134/1 diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index cd55ad4..27afcf5 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -109,6 +109,8 @@ wrmsr movl $MTRR_PHYS_MASK(1), %ecx wrmsr + movl $MTRR_PHYS_MASK(2), %ecx + wrmsr movl $LAPIC_BASE_MSR, %ecx not %edx movl %edx, %ebx @@ -251,6 +253,18 @@ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr + /* Set Cache-as-RAM base address. */ + movl $(MTRR_PHYS_BASE(2)), %ecx + movl $(CONFIG_TEST_DCACHE_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + /* Set Cache-as-RAM mask. */ + movl $(MTRR_PHYS_MASK(2)), %ecx + rdmsr + movl $(~(CONFIG_TEST_DCACHE_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + post_code(0x2b) /* Enable MTRR. */ diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index c36e046..727e298 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -12,11 +12,13 @@ */ #include <arch/cpu.h> +#include <arch/io.h> #include <console/console.h> #include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <arch/symbols.h> #include <program_loading.h> +#include <halt.h> #define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000 @@ -42,6 +44,13 @@ for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; + for (i = 0; i < CONFIG_TEST_DCACHE_SIZE; i = i + 4) + write32((u8 *)CONFIG_TEST_DCACHE_BASE + i, 0x5bb54aa4); + + for (i = 0; i < CONFIG_TEST_DCACHE_SIZE; i = i + 4) + if (read32((u8 *)CONFIG_TEST_DCACHE_BASE + i) != 0x5bb54aa4) + halt(); + mainboard_romstage_entry(bist); /* Check the stack. */ diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 8b227bd..f7946b3 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -23,4 +23,12 @@ hex default 0xfeffc000 # 4GB - 16MB - DCACHE_RAM_SIZE +config TEST_DCACHE_SIZE + hex + default 0x40000 # 256kB + +config TEST_DCACHE_BASE + hex + default 0x1400000 # 20MB + endif # CPU_INTEL_SOCKET_LGA775 -- To view, visit https://review.coreboot.org/27134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibef20c86d4377ed36ef8ad1bcff5e1eb5c9b766a Gerrit-Change-Number: 27134 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: [TESTONLY]cpu/intel/p4-netburst: skip caching rom on model_fxx
by build bot (Jenkins) (Code Review) 16 Jun '18

16 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27133 ) Change subject: [TESTONLY]cpu/intel/p4-netburst: skip caching rom on model_fxx ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29111/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75015/ : SUCCESS -- To view, visit https://review.coreboot.org/27133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1df84ad55e2d8d6d4e8dca10125131b5f525f0d7 Gerrit-Change-Number: 27133 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Jun 2018 18:12:43 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [TESTONLY]cpu/intel/p4-netburst: skip caching rom on model_fxx
by Arthur Heymans (Code Review) 16 Jun '18

16 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27133 Change subject: [TESTONLY]cpu/intel/p4-netburst: skip caching rom on model_fxx ...................................................................... [TESTONLY]cpu/intel/p4-netburst: skip caching rom on model_fxx Vendor does this too... Change-Id: I1df84ad55e2d8d6d4e8dca10125131b5f525f0d7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/p4-netburst/cache_as_ram.S 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/27133/1 diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 58782b9..cd55ad4 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -315,6 +315,11 @@ orl $CR0_CacheDisable, %eax movl %eax, %cr0 + movl $1, %eax + cpuid + cmp $0x6, %ah + jne skip_cache_rom + /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx @@ -332,6 +337,8 @@ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr +skip_cache_rom: + post_code(0x2e) /* Enable cache. */ movl %cr0, %eax -- To view, visit https://review.coreboot.org/27133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1df84ad55e2d8d6d4e8dca10125131b5f525f0d7 Gerrit-Change-Number: 27133 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: drivers/spi/winbond.c: Add W25Q80
by Arthur Heymans (Code Review) 16 Jun '18

16 Jun '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27132 ) Change subject: drivers/spi/winbond.c: Add W25Q80 ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27132/1/src/drivers/spi/winbond.c File src/drivers/spi/winbond.c: https://review.coreboot.org/#/c/27132/1/src/drivers/spi/winbond.c@71 PS1, Line 71: }, this list is ordered so place it here. -- To view, visit https://review.coreboot.org/27132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I60c940aa30081047a0f96cecf5464c4eb69795eb Gerrit-Change-Number: 27132 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Jun 2018 17:10:45 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: drivers/spi/winbond.c: Add W25Q80
by build bot (Jenkins) (Code Review) 16 Jun '18

16 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27132 ) Change subject: drivers/spi/winbond.c: Add W25Q80 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29110/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75014/ : SUCCESS -- To view, visit https://review.coreboot.org/27132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I60c940aa30081047a0f96cecf5464c4eb69795eb Gerrit-Change-Number: 27132 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Jun 2018 17:01:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit June 2018