coreboot-gerrit June 2018

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Change in coreboot[master]: nb/lenovo/t400: Enable libgfxinit
by Arthur Heymans (Code Review) 11 Jun '18

11 Jun '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27014 to look at the new patch set (#2). Change subject: nb/lenovo/t400: Enable libgfxinit ...................................................................... nb/lenovo/t400: Enable libgfxinit Change-Id: I243c22c83a5575c2e1500cc869c41691c4fba415 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t400/Makefile.inc A src/mainboard/lenovo/t400/gma-mainboard.ads 3 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/27014/2 -- To view, visit https://review.coreboot.org/27014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I243c22c83a5575c2e1500cc869c41691c4fba415 Gerrit-Change-Number: 27014 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/lenovo/x200: Enable libgfxinit
by Arthur Heymans (Code Review) 11 Jun '18

11 Jun '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27013 to look at the new patch set (#2). Change subject: mb/lenovo/x200: Enable libgfxinit ...................................................................... mb/lenovo/x200: Enable libgfxinit Change-Id: I6919845965d90fe8a20a07748ae4804fed0d0cef Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x200/Makefile.inc A src/mainboard/lenovo/x200/gma-mainboard.ads 3 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/27013/2 -- To view, visit https://review.coreboot.org/27013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6919845965d90fe8a20a07748ae4804fed0d0cef Gerrit-Change-Number: 27013 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src: Move constant to the right side of comparison
by build bot (Jenkins) (Code Review) 11 Jun '18

11 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27015 ) Change subject: src: Move constant to the right side of comparison ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/74746/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/28846/ : SUCCESS -- To view, visit https://review.coreboot.org/27015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I76d35a3643600f81a6da7e0af99c935ebd1c2fc7 Gerrit-Change-Number: 27015 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Jun 2018 08:37:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/lenovo/t400: Enable libgfxinit
by build bot (Jenkins) (Code Review) 11 Jun '18

11 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27014 ) Change subject: nb/lenovo/t400: Enable libgfxinit ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/74745/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/28845/ : SUCCESS -- To view, visit https://review.coreboot.org/27014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I243c22c83a5575c2e1500cc869c41691c4fba415 Gerrit-Change-Number: 27014 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Jun 2018 08:37:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/lenovo/x200: Enable libgfxinit
by build bot (Jenkins) (Code Review) 11 Jun '18

11 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27013 ) Change subject: mb/lenovo/x200: Enable libgfxinit ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/74744/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/28844/ : SUCCESS -- To view, visit https://review.coreboot.org/27013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6919845965d90fe8a20a07748ae4804fed0d0cef Gerrit-Change-Number: 27013 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Jun 2018 08:37:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/gm45: Depreciate native graphic init
by Arthur Heymans (Code Review) 11 Jun '18

11 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27016 Change subject: nb/intel/gm45: Depreciate native graphic init ...................................................................... nb/intel/gm45: Depreciate native graphic init Libgfxinit provides a better alternative to the native C init. While libgfxinit mandates an ada compiler, we want to encourage use of it since it is in much better shape and is actually maintained. This way libgfxinit also gets build-tested by Jenkins. Change-Id: I540cf08cef6ff7825694ebfa36e2e6437916e657 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/x200/Kconfig M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/gma.c 4 files changed, 4 insertions(+), 580 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/27016/1 diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 2b37857..e6b55a8 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -17,7 +17,6 @@ select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME - select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_INT15 select SUPERIO_NSC_PC87382 select SUPERIO_NSC_PC87384 diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 51a08e8..543d69c 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -17,7 +17,6 @@ select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME - select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_INT15 select SUPERIO_NSC_PC87382 select DRIVERS_LENOVO_WACOM diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index a45e841..da67882 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -26,8 +26,6 @@ select INTEL_EDID select INTEL_GMA_ACPI select INTEL_GMA_SSC_ALTERNATE_REF - select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT - select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select POSTCAR_STAGE select POSTCAR_CONSOLE diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 606170c..6381919 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -64,579 +64,6 @@ gnvs_ptr->aslb = aslb; } -static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb, - struct edid *edid) -{ - int i; - struct edid_mode *mode; - u32 hactive, vactive, right_border, bottom_border; - int hpolarity, vpolarity; - u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; - u32 smallest_err = 0xffffffff; - u32 target_frequency; - u32 pixel_p1 = 1; - u32 pixel_n = 1; - u32 pixel_m1 = 1; - u32 pixel_m2 = 1; - u32 pixel_p2; - - vga_gr_write(0x18, 0); - - /* Setup GTT. */ - for (i = 0; i < 0x2000; i++) - { - outl((i << 2) | 1, piobase); - outl(physbase + (i << 12) + 1, piobase + 4); - } - - write32(mmio + ADPA, 0x40008c18); - write32(mmio + 0x7041c, 0x0); - write32(mmio + _DPLL_B_MD, 0x3); - - vga_misc_write(0x67); - - const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, - 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, - 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, - 0xff - }; - vga_cr_write(0x11, 0); - - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - mode = &edid->mode; - - hactive = edid->x_resolution; - vactive = edid->y_resolution; - right_border = mode->hborder; - bottom_border = mode->vborder; - hpolarity = (mode->phsync == '-'); - vpolarity = (mode->pvsync == '-'); - vsync = mode->vspw; - hsync = mode->hspw; - vblank = mode->vbl; - hblank = mode->hbl; - hfront_porch = mode->hso; - vfront_porch = mode->vso; - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - vga_sr_write(1, 1); - vga_sr_write(0x2, 0xf); - vga_sr_write(0x3, 0x0); - vga_sr_write(0x4, 0xe); - vga_gr_write(0, 0x0); - vga_gr_write(1, 0x0); - vga_gr_write(2, 0x0); - vga_gr_write(3, 0x0); - vga_gr_write(4, 0x0); - vga_gr_write(5, 0x0); - vga_gr_write(6, 0x5); - vga_gr_write(7, 0xf); - vga_gr_write(0x10, 0x1); - vga_gr_write(0x11, 0); - - edid->bytes_per_line = (edid->bytes_per_line + 63) & ~63; - - write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); - write32(mmio + DSPADDR(0), 0); - write32(mmio + DSPSTRIDE(0), edid->bytes_per_line); - write32(mmio + DSPSURF(0), 0); - for (i = 0; i < 0x100; i++) - write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); - } else { - vga_textmode_init(); - } - - target_frequency = mode->pixel_clock; - /* - * p2 divisor must 7 for dual channel LVDS - * and 14 for single channel LVDS - */ - pixel_p2 = mode->lvds_dual_channel ? 7 : 14; - - /* - * Find suitable divisors, m1, m2, p1, n. - * refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 - * should be closest to target frequency as possible - */ - u32 candn, candm1, candm2, candp1; - for (candn = 1; candn <= 3; candn++) { - for (candm1 = 23; candm1 >= 17; candm1--) { - for (candm2 = 11; candm2 >= 5; candm2--) { - for (candp1 = mode->lvds_dual_channel ? 6 : 8; - candp1 >= 2; candp1--) { - u32 m = 5 * (candm1 + 2) + (candm2 + 2); - u32 p = candp1 * pixel_p2; - u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); - u32 dot = DIV_ROUND_CLOSEST(vco, p); - u32 this_err = MAX(dot, target_frequency) - - MIN(dot, target_frequency); - if (this_err < smallest_err) { - smallest_err = this_err; - pixel_n = candn; - pixel_m1 = candm1; - pixel_m2 = candm2; - pixel_p1 = candp1; - } - } - } - } - } - - if (smallest_err == 0xffffffff) { - printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); - return; - } - - printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", - hactive, vactive); - printk(BIOS_DEBUG, "Borders %d x %d\n", - right_border, bottom_border); - printk(BIOS_DEBUG, "Blank %d x %d\n", - hblank, vblank); - printk(BIOS_DEBUG, "Sync %d x %d\n", - hsync, vsync); - printk(BIOS_DEBUG, "Front porch %d x %d\n", - hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock - ? "Spread spectrum clock\n" : "DREF clock\n")); - printk(BIOS_DEBUG, - mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); - printk(BIOS_DEBUG, "Polarities %d, %d\n", - hpolarity, vpolarity); - printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1); - printk(BIOS_DEBUG, "Pixel clock %d kHz\n", - BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / - (pixel_n + 2) / (pixel_p1 * pixel_p2)); - - write32(mmio + LVDS, - (hpolarity << 20) | (vpolarity << 21) - | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL - | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_ENABLE_DITHER - | LVDS_CLOCK_A_POWERUP_ALL - | LVDS_PIPE(0)); - mdelay(1); - write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS - | (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - write32(mmio + FP0(0), - (pixel_n << 16) - | (pixel_m1 << 8) | (pixel_m2)); - write32(mmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | DPLL_VGA_MODE_DIS - | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | (0x10000 << (pixel_p1 - 1)) - | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) - | (6 << PLL_LOAD_PULSE_PHASE_SHIFT)); - mdelay(1); - write32(mmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | DPLL_VGA_MODE_DIS - | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | (0x10000 << (pixel_p1 - 1)) - | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) - | (6 << PLL_LOAD_PULSE_PHASE_SHIFT)); - /* Re-lock the registers. */ - write32(mmio + PP_CONTROL, - (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - - write32(mmio + LVDS, - (hpolarity << 20) | (vpolarity << 21) - | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL - | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_CLOCK_A_POWERUP_ALL - | LVDS_ENABLE_DITHER - | LVDS_PIPE(0)); - - write32(mmio + HTOTAL(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), - ((hactive + right_border + hfront_porch + hsync - 1) << 16) - | (hactive + right_border + hfront_porch - 1)); - - write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); - write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), - ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) - | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - write32(mmio + PIPESRC(0), ((hactive - 1) << 16) - | (vactive - 1)); - write32(mmio + PF_CTL(0), 0); - write32(mmio + PF_WIN_SZ(0), 0); - write32(mmio + PFIT_CONTROL, 0); - } else { - write32(mmio + PIPESRC(0), (639 << 16) | 399); - write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); - write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - write32(mmio + PFIT_CONTROL, 0x80000000); - } - - mdelay(1); - write32(mmio + PIPECONF(0), PIPECONF_BPP_6); - write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - write32(mmio + VGACNTRL, VGA_DISP_DISABLE); - write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE - | DISPPLANE_BGRX888); - mdelay(1); - } else { - write32(mmio + VGACNTRL, 0xc4008e); - } - - write32(mmio + LVDS, LVDS_PORT_ENABLE - | (hpolarity << 20) | (vpolarity << 21) - | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL - | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_CLOCK_A_POWERUP_ALL - | LVDS_ENABLE_DITHER - | LVDS_PIPE(0)); - - write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - - /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - memset((void *) lfb, 0, - edid->x_resolution * edid->y_resolution * 4); - set_vbe_mode_info_valid(edid, lfb); - } -} - -static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb, - struct edid *edid) -{ - - int i; - struct edid_mode *mode; - u32 hactive, vactive, right_border, bottom_border; - int hpolarity, vpolarity; - u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; - u32 target_frequency; - u32 smallest_err = 0xffffffff; - u32 pixel_p1 = 1; - u32 pixel_p2; - u32 pixel_n = 1; - u32 pixel_m1 = 1; - u32 pixel_m2 = 1; - - vga_gr_write(0x18, 0); - - /* Set up GTT. */ - for (i = 0; i < 0x2000; i++) { - outl((i << 2) | 1, piobase); - outl(physbase + (i << 12) + 1, piobase + 4); - } - - - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); - write32(mmio + DPLL_MD(1), 0x3); - - vga_misc_write(0x67); - - const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, - 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, - 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, - 0xff - }; - vga_cr_write(0x11, 0); - - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - - udelay(1); - - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - mode = &edid->mode; - - hactive = edid->x_resolution; - vactive = edid->y_resolution; - right_border = mode->hborder; - bottom_border = mode->vborder; - hpolarity = (mode->phsync == '-'); - vpolarity = (mode->pvsync == '-'); - vsync = mode->vspw; - hsync = mode->hspw; - vblank = mode->vbl; - hblank = mode->hbl; - hfront_porch = mode->hso; - vfront_porch = mode->vso; - target_frequency = mode->pixel_clock; - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - vga_sr_write(1, 1); - vga_sr_write(0x2, 0xf); - vga_sr_write(0x3, 0x0); - vga_sr_write(0x4, 0xe); - vga_gr_write(0, 0x0); - vga_gr_write(1, 0x0); - vga_gr_write(2, 0x0); - vga_gr_write(3, 0x0); - vga_gr_write(4, 0x0); - vga_gr_write(5, 0x0); - vga_gr_write(6, 0x5); - vga_gr_write(7, 0xf); - vga_gr_write(0x10, 0x1); - vga_gr_write(0x11, 0); - - edid->bytes_per_line = (edid->bytes_per_line + 63) & ~63; - - write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE - | DISPPLANE_BGRX888); - write32(mmio + DSPADDR(0), 0); - write32(mmio + DSPSTRIDE(0), edid->bytes_per_line); - write32(mmio + DSPSURF(0), 0); - for (i = 0; i < 0x100; i++) - write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); - } else { - vga_textmode_init(); - } - - pixel_p2 = target_frequency <= 225000 ? 10 : 5; - - u32 candn, candm1, candm2, candp1; - for (candn = 1; candn <= 4; candn++) { - for (candm1 = 23; candm1 >= 17; candm1--) { - for (candm2 = 11; candm2 >= 5; candm2--) { - for (candp1 = 8; candp1 >= 1; candp1--) { - u32 m = 5 * (candm1 + 2) + (candm2 + 2); - u32 p = candp1 * pixel_p2; - u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); - u32 dot = DIV_ROUND_CLOSEST(vco, p); - u32 this_err = MAX(dot, target_frequency) - - MIN(dot, target_frequency); - if (this_err < smallest_err) { - smallest_err= this_err; - pixel_n = candn; - pixel_m1 = candm1; - pixel_m2 = candm2; - pixel_p1 = candp1; - } - } - } - } - } - - if (smallest_err == 0xffffffff) { - printk(BIOS_ERR, "Error: Couldn't find GFX clock divisors\n"); - return; - } - - printk(BIOS_INFO, "Bringing up panel at resolution %d x %d\n", - hactive, vactive); - printk(BIOS_SPEW, "Borders %d x %d\n", - right_border, bottom_border); - printk(BIOS_SPEW, "Blank %d x %d\n", - hblank, vblank); - printk(BIOS_SPEW, "Sync %d x %d\n", - hsync, vsync); - printk(BIOS_SPEW, "Front porch %d x %d\n", - hfront_porch, vfront_porch); - printk(BIOS_SPEW, (info->gfx.use_spread_spectrum_clock - ? "Spread spectrum clock\n" : "DREF clock\n")); - printk(BIOS_SPEW, "Polarities %d, %d\n", - hpolarity, vpolarity); - printk(BIOS_SPEW, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2); - printk(BIOS_SPEW, "Pixel clock %d kHz\n", - BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / - (pixel_n + 2) / (pixel_p1 * pixel_p2)); - - mdelay(1); - write32(mmio + FP0(0), (pixel_n << 16) - | (pixel_m1 << 8) | pixel_m2); - write32(mmio + DPLL(0), DPLL_VCO_ENABLE - | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL - | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 : - DPLL_DAC_SERIAL_P2_CLOCK_DIV_5) - | (0x10000 << (pixel_p1 - 1)) - | (6 << 9)); - - mdelay(1); - write32(mmio + DPLL(0), DPLL_VCO_ENABLE - | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL - | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 : - DPLL_DAC_SERIAL_P2_CLOCK_DIV_5) - | (0x10000 << (pixel_p1 - 1)) - | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : - ADPA_VSYNC_ACTIVE_HIGH) - | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : - ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), - ((hactive + right_border + hfront_porch + hsync - 1) << 16) - | (hactive + right_border + hfront_porch - 1)); - - write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); - write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), - ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) - | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - write32(mmio + PIPESRC(0), ((hactive - 1) << 16) - | (vactive - 1)); - write32(mmio + PF_CTL(0), 0); - write32(mmio + PF_WIN_SZ(0), 0); - write32(mmio + PFIT_CONTROL, 0); - } else { - write32(mmio + PIPESRC(0), (639 << 16) | 399); - write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); - write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - write32(mmio + PFIT_CONTROL, 0x80000000); - } - - mdelay(1); - write32(mmio + PIPECONF(0), PIPECONF_BPP_6); - write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - write32(mmio + VGACNTRL, VGA_DISP_DISABLE); - write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE - | DISPPLANE_BGRX888); - mdelay(1); - } else { - write32(mmio + VGACNTRL, 0xc4008e); - } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : - ADPA_VSYNC_ACTIVE_HIGH) - | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : - ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - - /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - memset((void *) lfb, 0, - edid->x_resolution * edid->y_resolution * 4); - set_vbe_mode_info_valid(edid, lfb); - } - - -} - -static void gma_ngi(struct device *const dev, struct edid *edid_lvds) -{ - u8 edid_data_vga[128]; - struct edid edid_vga; - int vga_edid_status; - u8 *mmio; - struct northbridge_intel_gm45_config *conf = dev->chip_info; - - mmio = res2mmio(gtt_res, 0, 0); - printk(BIOS_DEBUG, "VGA EDID\n"); - intel_gmbus_read_edid(mmio + GMBUS0, GMBUS_PORT_VGADDC, 0x50, - edid_data_vga, sizeof(edid_data_vga)); - intel_gmbus_stop(mmio + GMBUS0); - vga_edid_status = decode_edid(edid_data_vga, - sizeof(edid_data_vga), &edid_vga); - - u32 physbase; - struct resource *lfb_res; - struct resource *pio_res; - - lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); - pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); - - physbase = pci_read_config32(dev, 0x5c) & ~0xf; - - if (!(physbase && pio_res && pio_res->base && lfb_res && lfb_res->base)) - return; - - printk(BIOS_SPEW, "Initializing display without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_edid_status != EDID_ABSENT) { - printk(BIOS_DEBUG, "Initialising display on VGA output\n"); - gma_init_vga(conf, mmio, physbase, pio_res->base, lfb_res->base, - &edid_vga); - } else { - printk(BIOS_DEBUG, "Initialising display on LVDS output\n"); - gma_init_lvds(conf, mmio, physbase, pio_res->base, - lfb_res->base, edid_lvds); - } - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CANTIGA"); -} - static u32 get_cdclk(struct device *const dev) { const u16 cdclk_sel = @@ -745,6 +172,7 @@ u8 *mmio; u8 edid_data_lvds[128]; struct edid edid_lvds; + const struct northbridge_intel_gm45_config *const conf = dev->chip_info; /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); @@ -771,11 +199,11 @@ /* Post VBIOS init */ gma_pm_init_post_vbios(dev, edid_lvds.ascii_string); - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { - gma_ngi(dev, &edid_lvds); - } else if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { int lightup_ok; gma_gfxinit(&lightup_ok); + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CANTIGA"); } intel_gma_restore_opregion(); -- To view, visit https://review.coreboot.org/27016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I540cf08cef6ff7825694ebfa36e2e6437916e657 Gerrit-Change-Number: 27016 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: src: Move constant to the right side of comparison
by Elyes HAOUAS (Code Review) 11 Jun '18

11 Jun '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27015 Change subject: src: Move constant to the right side of comparison ...................................................................... src: Move constant to the right side of comparison Change-Id: I76d35a3643600f81a6da7e0af99c935ebd1c2fc7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/pci_rom.c M src/northbridge/amd/agesa/family16kb/state_machine.c M src/northbridge/amd/amdmct/mct/mctardk4.c M src/southbridge/amd/cimx/sb800/late.c 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/27015/1 diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 35d3d69..7bc18a1 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -151,7 +151,7 @@ * whether the ROM image is for a VGA device because some * devices have a mismatch between the hardware and the ROM. */ - if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) { + if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) { #if !IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) extern struct device *vga_pri; /* Primary VGA device (device.c). */ if (dev != vga_pri) return NULL; /* Only one VGA supported. */ diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c index 00a7e85..39f7a29 100644 --- a/src/northbridge/amd/agesa/family16kb/state_machine.c +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -34,7 +34,7 @@ if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) { status = OemInitResume(&Post->MemConfig.MemContext); - if (AGESA_SUCCESS == status) + if (status == AGESA_SUCCESS) Post->MemConfig.MemRestoreCtl = 1; } } diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c index f7a4bee..d112c46 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk4.c +++ b/src/northbridge/amd/amdmct/mct/mctardk4.c @@ -146,6 +146,6 @@ } } p+=10; - } while (0xFF == *p); + } while (*p == 0xff); } } diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 30cddb2..45011b8 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -387,7 +387,7 @@ case PCI_DEVFN(0x14, 2): /* 0:14:2 HDA */ if (dev->enabled) { - if (AZALIA_DISABLE == sb_config->AzaliaController) { + if (sb_config->AzaliaController == AZALIA_DISABLE) { sb_config->AzaliaController = AZALIA_AUTO; } } else { -- To view, visit https://review.coreboot.org/27015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I76d35a3643600f81a6da7e0af99c935ebd1c2fc7 Gerrit-Change-Number: 27015 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: nb/lenovo/t400: Enable libgfxinit
by Arthur Heymans (Code Review) 11 Jun '18

11 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27014 Change subject: nb/lenovo/t400: Enable libgfxinit ...................................................................... nb/lenovo/t400: Enable libgfxinit Change-Id: I243c22c83a5575c2e1500cc869c41691c4fba415 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t400/Makefile.inc A src/mainboard/lenovo/t400/gma-mainboard.ads 3 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/27014/1 diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 8eb5fc5..2b37857 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -22,6 +22,7 @@ select SUPERIO_NSC_PC87382 select SUPERIO_NSC_PC87384 select DRIVERS_LENOVO_HYBRID_GRAPHICS + select MAINBOARD_HAS_LIBGFXINIT config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc index c2c82b6..a0d3ec5 100644 --- a/src/mainboard/lenovo/t400/Makefile.inc +++ b/src/mainboard/lenovo/t400/Makefile.inc @@ -18,3 +18,5 @@ ramstage-y += dock.c ramstage-y += cstates.c ramstage-y += blc.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads \ No newline at end of file diff --git a/src/mainboard/lenovo/t400/gma-mainboard.ads b/src/mainboard/lenovo/t400/gma-mainboard.ads new file mode 100644 index 0000000..680dd1b --- /dev/null +++ b/src/mainboard/lenovo/t400/gma-mainboard.ads @@ -0,0 +1,31 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + HDMI1, + HDMI2, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; -- To view, visit https://review.coreboot.org/27014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I243c22c83a5575c2e1500cc869c41691c4fba415 Gerrit-Change-Number: 27014 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: mb/lenovo/x200: Enable libgfxinit
by Arthur Heymans (Code Review) 11 Jun '18

11 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27013 Change subject: mb/lenovo/x200: Enable libgfxinit ...................................................................... mb/lenovo/x200: Enable libgfxinit Change-Id: I6919845965d90fe8a20a07748ae4804fed0d0cef Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x200/Makefile.inc A src/mainboard/lenovo/x200/gma-mainboard.ads 3 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/27013/1 diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index d2fcec4..51a08e8 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -21,6 +21,7 @@ select INTEL_INT15 select SUPERIO_NSC_PC87382 select DRIVERS_LENOVO_WACOM + select MAINBOARD_HAS_LIBGFXINIT config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x200/Makefile.inc b/src/mainboard/lenovo/x200/Makefile.inc index 0029d32..010d670 100644 --- a/src/mainboard/lenovo/x200/Makefile.inc +++ b/src/mainboard/lenovo/x200/Makefile.inc @@ -16,3 +16,5 @@ ramstage-y += dock.c ramstage-y += cstates.c ramstage-y += blc.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads \ No newline at end of file diff --git a/src/mainboard/lenovo/x200/gma-mainboard.ads b/src/mainboard/lenovo/x200/gma-mainboard.ads new file mode 100644 index 0000000..92702b2 --- /dev/null +++ b/src/mainboard/lenovo/x200/gma-mainboard.ads @@ -0,0 +1,30 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, + HDMI2, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; -- To view, visit https://review.coreboot.org/27013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6919845965d90fe8a20a07748ae4804fed0d0cef Gerrit-Change-Number: 27013 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: src: Get rid of unneeded whitespace
by build bot (Jenkins) (Code Review) 11 Jun '18

11 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26991 ) Change subject: src: Get rid of unneeded whitespace ...................................................................... Patch Set 10: (21 comments) https://review.coreboot.org/#/c/26991/10/src/include/bootstate.h File src/include/bootstate.h: https://review.coreboot.org/#/c/26991/10/src/include/bootstate.h@127 PS10, Line 127: #define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \ Single statement macros should not use a do {} while (0) loop https://review.coreboot.org/#/c/26991/10/src/mainboard/amd/bimini_fam10/rom… File src/mainboard/amd/bimini_fam10/romstage.c: https://review.coreboot.org/#/c/26991/10/src/mainboard/amd/bimini_fam10/rom… PS10, Line 83: inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */ line over 80 characters https://review.coreboot.org/#/c/26991/10/src/mainboard/amd/tilapia_fam10/ma… File src/mainboard/amd/tilapia_fam10/mainboard.c: https://review.coreboot.org/#/c/26991/10/src/mainboard/amd/tilapia_fam10/ma… PS10, Line 153: /* When the gpio40 is configured as GPIO, this will represent the output value*/ line over 80 characters https://review.coreboot.org/#/c/26991/10/src/mainboard/amd/tilapia_fam10/ma… PS10, Line 165: /* When the gpio40 is configured as GPIO, this will represent the output value*/ line over 80 characters https://review.coreboot.org/#/c/26991/10/src/mainboard/asus/kfsn4-dre/resou… File src/mainboard/asus/kfsn4-dre/resourcemap.c: https://review.coreboot.org/#/c/26991/10/src/mainboard/asus/kfsn4-dre/resou… PS10, Line 229: // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, line over 80 characters https://review.coreboot.org/#/c/26991/10/src/mainboard/tyan/s2912_fam10/res… File src/mainboard/tyan/s2912_fam10/resourcemap.c: https://review.coreboot.org/#/c/26991/10/src/mainboard/tyan/s2912_fam10/res… PS10, Line 269: // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */ line over 80 characters https://review.coreboot.org/#/c/26991/10/src/northbridge/amd/agesa/family14… File src/northbridge/amd/agesa/family14/chip.h: https://review.coreboot.org/#/c/26991/10/src/northbridge/amd/agesa/family14… PS10, Line 30: * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused) line over 80 characters https://review.coreboot.org/#/c/26991/10/src/northbridge/amd/amdht/h3gtopo.h File src/northbridge/amd/amdht/h3gtopo.h: https://review.coreboot.org/#/c/26991/10/src/northbridge/amd/amdht/h3gtopo.… PS10, Line 259: 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6 line over 80 characters https://review.coreboot.org/#/c/26991/10/src/northbridge/amd/amdmct/mct/mct… File src/northbridge/amd/amdmct/mct/mctdqs_d.c: https://review.coreboot.org/#/c/26991/10/src/northbridge/amd/amdmct/mct/mct… PS10, Line 464: BanksPresent = 1; /* flag for at least one bank is present */ line over 80 characters https://review.coreboot.org/#/c/26991/10/src/northbridge/amd/amdmct/mct_ddr… File src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c: https://review.coreboot.org/#/c/26991/10/src/northbridge/amd/amdmct/mct_ddr… PS10, Line 118: OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ line over 80 characters https://review.coreboot.org/#/c/26991/10/src/northbridge/amd/amdmct/mct_ddr… PS10, Line 123: /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */ line over 80 characters https://review.coreboot.org/#/c/26991/10/src/northbridge/amd/amdmct/mct_ddr… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/26991/10/src/northbridge/amd/amdmct/mct_ddr… PS10, Line 699: // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]); line over 80 characters https://review.coreboot.org/#/c/26991/10/src/southbridge/amd/cimx/sb800/lat… File src/southbridge/amd/cimx/sb800/late.c: https://review.coreboot.org/#/c/26991/10/src/southbridge/amd/cimx/sb800/lat… PS10, Line 355: sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; line over 80 characters https://review.coreboot.org/#/c/26991/10/src/southbridge/amd/cimx/sb800/lat… PS10, Line 361: sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; line over 80 characters https://review.coreboot.org/#/c/26991/10/src/southbridge/amd/cimx/sb800/lat… PS10, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/26991/10/src/southbridge/amd/cimx/sb800/lat… PS10, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26991/10/src/southbridge/amd/cimx/sb900/lat… File src/southbridge/amd/cimx/sb900/late.c: https://review.coreboot.org/#/c/26991/10/src/southbridge/amd/cimx/sb900/lat… PS10, Line 383: sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; line over 80 characters https://review.coreboot.org/#/c/26991/10/src/southbridge/amd/cimx/sb900/lat… PS10, Line 390: if (sb_config->AzaliaController == AZALIA_DISABLE) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26991/10/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/26991/10/src/southbridge/amd/rs780/gfx.c@452 PS10, Line 452: vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default line over 80 characters https://review.coreboot.org/#/c/26991/10/src/southbridge/amd/rs780/rs780.c File src/southbridge/amd/rs780/rs780.c: https://review.coreboot.org/#/c/26991/10/src/southbridge/amd/rs780/rs780.c@… PS10, Line 96: /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ line over 80 characters https://review.coreboot.org/#/c/26991/10/src/southbridge/amd/sr5650/cmn.h File src/southbridge/amd/sr5650/cmn.h: https://review.coreboot.org/#/c/26991/10/src/southbridge/amd/sr5650/cmn.h@23 PS10, Line 23: #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ line over 80 characters -- To view, visit https://review.coreboot.org/26991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Gerrit-Change-Number: 26991 Gerrit-PatchSet: 10 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Jun 2018 07:47:06 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit June 2018