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Change in coreboot[master]: src: Remove unneeded whitespace
by build bot (Jenkins) (Code Review) 11 Jun '18

11 Jun '18

1 0

Change in coreboot[master]: src: Remove unneeded whitespace
by Elyes HAOUAS (Code Review) 11 Jun '18

11 Jun '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/26991 to look at the new patch set (#8). Change subject: src: Remove unneeded whitespace ...................................................................... src: Remove unneeded whitespace Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Documentation/RFC/config.tex M src/drivers/intel/fsp2_0/hand_off_block.c M src/include/bootstate.h M src/mainboard/advansus/a785e-i/devicetree.cb M src/mainboard/amd/bettong/acpi/gpe.asl M src/mainboard/amd/bettong/dsdt.asl M src/mainboard/amd/bimini_fam10/devicetree.cb M src/mainboard/amd/bimini_fam10/dsdt.asl M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl M src/mainboard/amd/db-ft3b-lc/dsdt.asl M src/mainboard/amd/gardenia/acpi/gpe.asl M src/mainboard/amd/inagua/acpi/gpe.asl M src/mainboard/amd/inagua/acpi/sleep.asl M src/mainboard/amd/inagua/acpi/usb_oc.asl M src/mainboard/amd/lamar/acpi/gpe.asl M src/mainboard/amd/lamar/acpi/sleep.asl M src/mainboard/amd/mahogany_fam10/devicetree.cb M src/mainboard/amd/mahogany_fam10/dsdt.asl M src/mainboard/amd/olivehill/acpi/gpe.asl M src/mainboard/amd/olivehill/dsdt.asl M src/mainboard/amd/olivehillplus/acpi/gpe.asl M src/mainboard/amd/olivehillplus/dsdt.asl M src/mainboard/amd/parmer/acpi/gpe.asl M src/mainboard/amd/parmer/acpi/sleep.asl M src/mainboard/amd/persimmon/acpi/gpe.asl M src/mainboard/amd/persimmon/acpi/sleep.asl M src/mainboard/amd/south_station/acpi/gpe.asl M src/mainboard/amd/south_station/acpi/sleep.asl M src/mainboard/amd/south_station/acpi/usb_oc.asl M src/mainboard/amd/south_station/devicetree.cb M src/mainboard/amd/south_station/mainboard.c M src/mainboard/amd/thatcher/acpi/gpe.asl M src/mainboard/amd/thatcher/acpi/sleep.asl M src/mainboard/amd/tilapia_fam10/devicetree.cb M src/mainboard/amd/tilapia_fam10/dsdt.asl M src/mainboard/amd/tilapia_fam10/mainboard.c M src/mainboard/amd/torpedo/devicetree.cb M src/mainboard/amd/torpedo/dsdt.asl M src/mainboard/amd/torpedo/gpio.c M src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl M src/mainboard/asus/kfsn4-dre/dsdt.asl M src/mainboard/asus/kfsn4-dre/resourcemap.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/pcengines/alix1c/devicetree.cb M src/mainboard/pcengines/alix1c/irq_tables.c M src/mainboard/pcengines/alix2d/devicetree.cb M src/mainboard/pcengines/apu1/acpi/gpe.asl M src/mainboard/pcengines/apu1/acpi/sleep.asl M src/mainboard/pcengines/apu2/acpi/gpe.asl M src/mainboard/pcengines/apu2/dsdt.asl M src/mainboard/pcengines/apu2/mptable.c M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/roda/rk886ex/acpi/thermal.asl M src/mainboard/roda/rk886ex/devicetree.cb M src/mainboard/tyan/s2912_fam10/resourcemap.c M src/northbridge/amd/agesa/family14/chip.h M src/northbridge/amd/amdfam10/resourcemap.c M src/northbridge/amd/amdht/h3gtopo.h M src/northbridge/amd/amdmct/amddefs.h M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct/mct_d_gcc.c M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct/mctecc_d.c M src/northbridge/amd/amdmct/mct/mctmtr_d.c M src/northbridge/amd/amdmct/mct/mctsrc.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.h M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/amd/lx/northbridgeinit.c M src/northbridge/amd/lx/raminit.c M src/northbridge/intel/e7505/e7505.h M src/soc/amd/common/block/pi/def_callouts.c M src/southbridge/amd/agesa/hudson/resume.c M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/cimx/sb900/late.c M src/southbridge/amd/cs5536/cs5536.c M src/southbridge/amd/cs5536/cs5536.h M src/southbridge/amd/pi/hudson/amd_pci_int_defs.h M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/hudson.h M src/southbridge/amd/rs780/early_setup.c M src/southbridge/amd/rs780/gfx.c M src/southbridge/amd/rs780/rs780.c M src/southbridge/amd/rs780/rs780.h M src/southbridge/amd/sb700/sm.c M src/southbridge/amd/sb700/usb.c M src/southbridge/amd/sb800/usb.c M src/southbridge/amd/sr5650/cmn.h M src/southbridge/amd/sr5650/pcie.c M src/southbridge/amd/sr5650/sr5650.c M src/southbridge/broadcom/bcm5785/lpc.c M src/southbridge/intel/bd82x6x/acpi/pch.asl M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pciehp.c M src/southbridge/intel/common/smbus.c M src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl M src/southbridge/intel/fsp_bd82x6x/me.h M src/southbridge/intel/fsp_bd82x6x/smi.c M src/southbridge/intel/fsp_bd82x6x/smihandler.c M src/southbridge/intel/fsp_i89xx/acpi/pch.asl M src/southbridge/intel/fsp_i89xx/me.h M src/southbridge/intel/fsp_i89xx/smihandler.c M src/southbridge/intel/fsp_rangeley/acpi/soc.asl M src/southbridge/intel/i82801dx/smihandler.c M src/southbridge/intel/i82801gx/acpi/ich7.asl M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/i82870/82870.h M src/southbridge/intel/ibexpeak/me.h M src/southbridge/intel/lynxpoint/acpi/pch.asl M src/southbridge/intel/lynxpoint/me.h M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/smihandler.c M src/southbridge/via/common/early_smbus_print_error.c M util/autoport/readme.md M util/crossgcc/buildgcc M util/intelmetool/me.h M util/romcc/romcc.c M util/vgabios/device.c M util/vgabios/testbios.c 128 files changed, 534 insertions(+), 531 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/26991/8 -- To view, visit https://review.coreboot.org/26991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Gerrit-Change-Number: 26991 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: src: Use of device_t is deprecated
by build bot (Jenkins) (Code Review) 11 Jun '18

11 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27010 ) Change subject: src: Use of device_t is deprecated ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/74738/ : SUCCESS -- To view, visit https://review.coreboot.org/27010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417 Gerrit-Change-Number: 27010 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Jun 2018 06:56:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: google/fizz: fix LAN driver chip_info attachment
by build bot (Jenkins) (Code Review) 11 Jun '18

11 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27012 ) Change subject: google/fizz: fix LAN driver chip_info attachment ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/74736/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/28839/ : SUCCESS -- To view, visit https://review.coreboot.org/27012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I08810c0c89d99af5799f42c7c4e51814f09aafec Gerrit-Change-Number: 27012 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Jun 2018 06:39:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: src: Use of device_t is deprecated
by Elyes HAOUAS (Code Review) 11 Jun '18

11 Jun '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27010 to look at the new patch set (#3). Change subject: src: Use of device_t is deprecated ...................................................................... src: Use of device_t is deprecated Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/hypertransport.c M src/drivers/net/ne2k.c M src/drivers/usb/pci_ehci.c M src/include/device/cardbus.h M src/include/device/pciexp.h M src/include/device/pcix.h M src/mainboard/hp/dl165_g6_fam10/bootblock.c M src/northbridge/amd/amdfam10/acpi.c M src/northbridge/amd/amdfam10/amdfam10.h M src/northbridge/amd/amdfam10/ht_config.c M src/northbridge/amd/amdfam10/ht_config.h M src/northbridge/amd/amdfam10/misc_control.c M src/northbridge/amd/amdfam10/northbridge.h M src/northbridge/amd/amdfam10/util.c M src/northbridge/amd/lx/northbridge.c M src/northbridge/amd/pi/00630F01/iommu.c M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/smihandler.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/spi.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/braswell/spi.c M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/fsp_baytrail/pmutil.c M src/soc/intel/fsp_baytrail/spi.c M src/southbridge/amd/sr5650/early_setup.c M src/superio/intel/i8900/i8900.h M src/superio/winbond/wpcd376i/early_serial.c M src/superio/winbond/wpcd376i/superio.c M src/superio/winbond/wpcd376i/wpcd376i.h 35 files changed, 109 insertions(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/27010/3 -- To view, visit https://review.coreboot.org/27010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417 Gerrit-Change-Number: 27010 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: src: Remove unneeded whitespace
by build bot (Jenkins) (Code Review) 11 Jun '18

11 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26991 ) Change subject: src: Remove unneeded whitespace ...................................................................... Patch Set 7: (17 comments) https://review.coreboot.org/#/c/26991/7/src/include/bootstate.h File src/include/bootstate.h: https://review.coreboot.org/#/c/26991/7/src/include/bootstate.h@127 PS7, Line 127: #define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \ Single statement macros should not use a do {} while (0) loop https://review.coreboot.org/#/c/26991/7/src/northbridge/amd/agesa/family14/… File src/northbridge/amd/agesa/family14/chip.h: https://review.coreboot.org/#/c/26991/7/src/northbridge/amd/agesa/family14/… PS7, Line 30: * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused) line over 80 characters https://review.coreboot.org/#/c/26991/7/src/northbridge/amd/amdht/h3gtopo.h File src/northbridge/amd/amdht/h3gtopo.h: https://review.coreboot.org/#/c/26991/7/src/northbridge/amd/amdht/h3gtopo.h… PS7, Line 259: 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6 line over 80 characters https://review.coreboot.org/#/c/26991/7/src/northbridge/amd/amdmct/mct/mctd… File src/northbridge/amd/amdmct/mct/mctdqs_d.c: https://review.coreboot.org/#/c/26991/7/src/northbridge/amd/amdmct/mct/mctd… PS7, Line 464: BanksPresent = 1; /* flag for at least one bank is present */ line over 80 characters https://review.coreboot.org/#/c/26991/7/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c: https://review.coreboot.org/#/c/26991/7/src/northbridge/amd/amdmct/mct_ddr3… PS7, Line 118: OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ line over 80 characters https://review.coreboot.org/#/c/26991/7/src/northbridge/amd/amdmct/mct_ddr3… PS7, Line 123: /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */ line over 80 characters https://review.coreboot.org/#/c/26991/7/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/26991/7/src/northbridge/amd/amdmct/mct_ddr3… PS7, Line 699: // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]); line over 80 characters https://review.coreboot.org/#/c/26991/7/src/northbridge/amd/lx/northbridgei… File src/northbridge/amd/lx/northbridgeinit.c: https://review.coreboot.org/#/c/26991/7/src/northbridge/amd/lx/northbridgei… PS7, Line 597: * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough line over 80 characters https://review.coreboot.org/#/c/26991/7/src/southbridge/amd/cimx/sb800/late… File src/southbridge/amd/cimx/sb800/late.c: https://review.coreboot.org/#/c/26991/7/src/southbridge/amd/cimx/sb800/late… PS7, Line 355: sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; line over 80 characters https://review.coreboot.org/#/c/26991/7/src/southbridge/amd/cimx/sb800/late… PS7, Line 361: sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; line over 80 characters https://review.coreboot.org/#/c/26991/7/src/southbridge/amd/cimx/sb800/late… PS7, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/26991/7/src/southbridge/amd/cimx/sb800/late… PS7, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26991/7/src/southbridge/amd/cimx/sb900/late… File src/southbridge/amd/cimx/sb900/late.c: https://review.coreboot.org/#/c/26991/7/src/southbridge/amd/cimx/sb900/late… PS7, Line 383: sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; line over 80 characters https://review.coreboot.org/#/c/26991/7/src/southbridge/amd/cimx/sb900/late… PS7, Line 390: if (sb_config->AzaliaController == AZALIA_DISABLE) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26991/7/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/26991/7/src/southbridge/amd/rs780/gfx.c@452 PS7, Line 452: vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default line over 80 characters https://review.coreboot.org/#/c/26991/7/src/southbridge/amd/rs780/rs780.c File src/southbridge/amd/rs780/rs780.c: https://review.coreboot.org/#/c/26991/7/src/southbridge/amd/rs780/rs780.c@96 PS7, Line 96: /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ line over 80 characters https://review.coreboot.org/#/c/26991/7/src/southbridge/amd/sr5650/cmn.h File src/southbridge/amd/sr5650/cmn.h: https://review.coreboot.org/#/c/26991/7/src/southbridge/amd/sr5650/cmn.h@23 PS7, Line 23: #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ line over 80 characters -- To view, visit https://review.coreboot.org/26991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Gerrit-Change-Number: 26991 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Jun 2018 06:33:56 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: {src, util}: Use NULL instead of 0 for pointer
by build bot (Jenkins) (Code Review) 11 Jun '18

11 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26857 ) Change subject: {src,util}: Use NULL instead of 0 for pointer ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/74735/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/28838/ : SUCCESS -- To view, visit https://review.coreboot.org/26857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I75fa4577055f25dde0a8b1044c005bba72cabd92 Gerrit-Change-Number: 26857 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Jun 2018 06:33:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src: Remove unneeded whitespace
by Elyes HAOUAS (Code Review) 11 Jun '18

11 Jun '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/26991 to look at the new patch set (#7). Change subject: src: Remove unneeded whitespace ...................................................................... src: Remove unneeded whitespace Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Documentation/RFC/config.tex M src/drivers/intel/fsp2_0/hand_off_block.c M src/include/bootstate.h M src/mainboard/advansus/a785e-i/devicetree.cb M src/mainboard/amd/south_station/devicetree.cb M src/mainboard/amd/torpedo/devicetree.cb M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/roda/rk886ex/acpi/thermal.asl M src/mainboard/roda/rk886ex/devicetree.cb M src/northbridge/amd/agesa/family14/chip.h M src/northbridge/amd/amdfam10/resourcemap.c M src/northbridge/amd/amdht/h3gtopo.h M src/northbridge/amd/amdmct/amddefs.h M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct/mct_d_gcc.c M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct/mctecc_d.c M src/northbridge/amd/amdmct/mct/mctmtr_d.c M src/northbridge/amd/amdmct/mct/mctsrc.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.h M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/amd/lx/northbridgeinit.c M src/northbridge/amd/lx/raminit.c M src/northbridge/intel/e7505/e7505.h M src/soc/amd/common/block/pi/def_callouts.c M src/southbridge/amd/agesa/hudson/resume.c M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/cimx/sb900/late.c M src/southbridge/amd/cs5536/cs5536.c M src/southbridge/amd/cs5536/cs5536.h M src/southbridge/amd/pi/hudson/amd_pci_int_defs.h M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/hudson.h M src/southbridge/amd/rs780/early_setup.c M src/southbridge/amd/rs780/gfx.c M src/southbridge/amd/rs780/rs780.c M src/southbridge/amd/rs780/rs780.h M src/southbridge/amd/sb700/sm.c M src/southbridge/amd/sb700/usb.c M src/southbridge/amd/sb800/usb.c M src/southbridge/amd/sr5650/cmn.h M src/southbridge/amd/sr5650/pcie.c M src/southbridge/amd/sr5650/sr5650.c M src/southbridge/broadcom/bcm5785/lpc.c M src/southbridge/intel/bd82x6x/acpi/pch.asl M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pciehp.c M src/southbridge/intel/common/smbus.c M src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl M src/southbridge/intel/fsp_bd82x6x/me.h M src/southbridge/intel/fsp_bd82x6x/smi.c M src/southbridge/intel/fsp_bd82x6x/smihandler.c M src/southbridge/intel/fsp_i89xx/acpi/pch.asl M src/southbridge/intel/fsp_i89xx/me.h M src/southbridge/intel/fsp_i89xx/smihandler.c M src/southbridge/intel/fsp_rangeley/acpi/soc.asl M src/southbridge/intel/i82801dx/smihandler.c M src/southbridge/intel/i82801gx/acpi/ich7.asl M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/i82870/82870.h M src/southbridge/intel/ibexpeak/me.h M src/southbridge/intel/lynxpoint/acpi/pch.asl M src/southbridge/intel/lynxpoint/me.h M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/smihandler.c M src/southbridge/via/common/early_smbus_print_error.c M util/autoport/readme.md M util/crossgcc/buildgcc M util/intelmetool/me.h M util/romcc/romcc.c M util/vgabios/device.c M util/vgabios/testbios.c 81 files changed, 401 insertions(+), 398 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/26991/7 -- To view, visit https://review.coreboot.org/26991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Gerrit-Change-Number: 26991 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/fizz: fix LAN driver chip_info attachment
by Matt DeVillier (Code Review) 11 Jun '18

11 Jun '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27012 Change subject: google/fizz: fix LAN driver chip_info attachment ...................................................................... google/fizz: fix LAN driver chip_info attachment As a result of commit: [711fb81] soc/intel/skylake: Swap PCI devfn resides in same PCI device fizz's chip_info for the LAN driver is being overwritten/nulled, as the LAN device is on function 2 (PCIe port 3), but the driver info was set for the post-swapped PCIe port (1). Move the driver chip_info to function 2/port 3, so that it follows the PCI device function when swapped after FSP-s, and is correctly passed to the LAN driver. Test: boot google/fizz (teemo variant), check cbmem console and verify ethernet MAC address and LED config correctly set. Change-Id: I08810c0c89d99af5799f42c7c4e51814f09aafec Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/fizz/devicetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/27012/1 diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 67828d1..0ac403e 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -429,17 +429,17 @@ end end # I2C #5 device pci 19.2 off end # I2C #4 - device pci 1c.0 on # PCI Express Port 1 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + # PCI Express Port 3 for LAN, will be swapped to port 1 by FSP + device pci 1c.2 on chip drivers/net register "customized_leds" = "0x0fa5" register "wake" = "GPE0_PCI_EXP" register "device_index" = "1" device pci 00.0 on end end - end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - # PCI Express Port 3 for LAN, but will be swapped to port 1 - device pci 1c.2 on end + end # PCI Express Port 3 device pci 1c.3 on chip drivers/intel/wifi register "wake" = "GPE0_PCI_EXP" -- To view, visit https://review.coreboot.org/27012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I08810c0c89d99af5799f42c7c4e51814f09aafec Gerrit-Change-Number: 27012 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: src: Get rid of device_t
by build bot (Jenkins) (Code Review) 11 Jun '18

11 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27010 ) Change subject: src: Get rid of device_t ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/74734/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/28837/ : SUCCESS -- To view, visit https://review.coreboot.org/27010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417 Gerrit-Change-Number: 27010 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Jun 2018 06:23:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit June 2018