coreboot-gerrit June 2018

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Change in coreboot[master]: src: Use NULL instead of 0 for pointer
by Elyes HAOUAS (Code Review) 13 Jun '18

13 Jun '18

Elyes HAOUAS has uploaded a new patch set (#2). ( https://review.coreboot.org/27096 ) Change subject: src: Use NULL instead of 0 for pointer ...................................................................... src: Use NULL instead of 0 for pointer Change-Id: Ie9d22a4d6bab1caf61f4f89e236ae3cd2f7fb42c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/exception.c M src/arch/x86/mpspec.c M src/arch/x86/smbios.c M src/device/dram/ddr2.c M src/drivers/amd/agesa/oem_s3.c M src/drivers/i2c/tpm/tis.c M src/drivers/intel/fsp1_1/hob.c M src/drivers/intel/fsp1_1/stage_cache.c M src/drivers/intel/fsp2_0/mma_core.c M src/drivers/intel/fsp2_0/stage_cache.c M src/drivers/intel/i210/i210.c M src/drivers/pc80/vga/vga.c M src/drivers/spi/tpm/tpm.c M src/drivers/xgi/common/vb_setmode.c M src/ec/google/chromeec/ec.c M src/lib/device_tree.c M src/mainboard/google/beltino/lan.c M src/mainboard/google/butterfly/mainboard.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/poppy/variants/atlas/nhlt.c M src/mainboard/google/poppy/variants/baseboard/gpio.c M src/mainboard/google/poppy/variants/baseboard/nhlt.c M src/mainboard/google/poppy/variants/nami/nhlt.c M src/mainboard/google/poppy/variants/nautilus/nhlt.c M src/mainboard/google/poppy/variants/nocturne/nhlt.c M src/mainboard/google/rambi/variants/ninja/lan.c M src/mainboard/google/rambi/variants/sumo/lan.c M src/mainboard/google/reef/mainboard.c M src/northbridge/amd/amdmct/mct/mct_d_gcc.c M src/northbridge/amd/amdmct/mct/mctardk3.c M src/northbridge/amd/amdmct/mct/mctardk4.c M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct/mctpro_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c M src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/rcven.c M src/northbridge/intel/nehalem/raminit.c M src/northbridge/intel/pineview/ram_calc.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_sandy.c M src/northbridge/intel/x4x/ram_calc.c M src/northbridge/intel/x4x/raminit.c M src/soc/amd/stoneyridge/gpio.c M src/soc/intel/broadwell/igd.c M src/soc/intel/broadwell/systemagent.c M src/soc/intel/common/block/acpi/acpi.c 55 files changed, 83 insertions(+), 83 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/27096/2 -- To view, visit https://review.coreboot.org/27096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie9d22a4d6bab1caf61f4f89e236ae3cd2f7fb42c Gerrit-Change-Number: 27096 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: src: Use NULL instead of 0 for pointer
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27096 ) Change subject: src: Use NULL instead of 0 for pointer ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27096/1/src/device/oprom/x86emu/debug.c File src/device/oprom/x86emu/debug.c: https://review.coreboot.org/#/c/27096/1/src/device/oprom/x86emu/debug.c@334 PS1, Line 334: *n = NULL; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/27096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie9d22a4d6bab1caf61f4f89e236ae3cd2f7fb42c Gerrit-Change-Number: 27096 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 20:55:13 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src: Use NULL instead of 0 for pointer
by Elyes HAOUAS (Code Review) 13 Jun '18

13 Jun '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27096 Change subject: src: Use NULL instead of 0 for pointer ...................................................................... src: Use NULL instead of 0 for pointer Change-Id: Ie9d22a4d6bab1caf61f4f89e236ae3cd2f7fb42c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/exception.c M src/arch/x86/mpspec.c M src/arch/x86/smbios.c M src/device/dram/ddr2.c M src/device/oprom/x86emu/debug.c M src/drivers/amd/agesa/oem_s3.c M src/drivers/i2c/tpm/tis.c M src/drivers/intel/fsp1_1/hob.c M src/drivers/intel/fsp1_1/stage_cache.c M src/drivers/intel/fsp2_0/mma_core.c M src/drivers/intel/fsp2_0/stage_cache.c M src/drivers/intel/i210/i210.c M src/drivers/pc80/vga/vga.c M src/drivers/spi/tpm/tpm.c M src/drivers/xgi/common/vb_setmode.c M src/ec/google/chromeec/ec.c M src/lib/device_tree.c M src/mainboard/google/beltino/lan.c M src/mainboard/google/butterfly/mainboard.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/poppy/variants/atlas/nhlt.c M src/mainboard/google/poppy/variants/baseboard/gpio.c M src/mainboard/google/poppy/variants/baseboard/nhlt.c M src/mainboard/google/poppy/variants/nami/nhlt.c M src/mainboard/google/poppy/variants/nautilus/nhlt.c M src/mainboard/google/poppy/variants/nocturne/nhlt.c M src/mainboard/google/rambi/variants/ninja/lan.c M src/mainboard/google/rambi/variants/sumo/lan.c M src/mainboard/google/reef/mainboard.c M src/northbridge/amd/amdmct/mct/mct_d_gcc.c M src/northbridge/amd/amdmct/mct/mctardk3.c M src/northbridge/amd/amdmct/mct/mctardk4.c M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct/mctpro_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c M src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/rcven.c M src/northbridge/intel/nehalem/raminit.c M src/northbridge/intel/pineview/ram_calc.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_sandy.c M src/northbridge/intel/x4x/ram_calc.c M src/northbridge/intel/x4x/raminit.c M src/soc/amd/stoneyridge/gpio.c M src/soc/intel/broadwell/igd.c M src/soc/intel/broadwell/systemagent.c M src/soc/intel/common/block/acpi/acpi.c 56 files changed, 84 insertions(+), 84 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/27096/1 diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index f668ffc..eb5d50d 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -273,7 +273,7 @@ char *start; start = *ptr; - *value = 0; + *value = NULL; while ((digit = hex(**ptr)) >= 0) { *value = ((*value) << 4) | digit; @@ -294,7 +294,7 @@ *buf++ = hexchars[ch >> 4]; *buf++ = hexchars[ch & 0x0f]; } - *buf = 0; + *buf = NULL; } diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index 8280171..03b54ed 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -487,7 +487,7 @@ if (!isa_bus) isa_bus = &dummy; - *max_pci_bus = 0; + *max_pci_bus = NULL; highest = 0; memset(buses, 0, sizeof(buses)); diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index da1b711..eeff760 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -205,7 +205,7 @@ for (char *p = buffer + len - 1; p >= buffer; --p) { if (*p == ' ') - *p = 0; + *p = NULL; else break; } diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 0d395c4..1055af1 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -741,7 +741,7 @@ } else if (*tclk <= TCK_200MHZ) { *tclk = TCK_200MHZ; } else { - *tclk = 0; + *tclk = NULL; printk(BIOS_ERR, "Too slow common tCLK found\n"); } } diff --git a/src/device/oprom/x86emu/debug.c b/src/device/oprom/x86emu/debug.c index 9e216e9..ad9d9db 100644 --- a/src/device/oprom/x86emu/debug.c +++ b/src/device/oprom/x86emu/debug.c @@ -331,7 +331,7 @@ #if 0 int cmd; - *n = 0; + *n = NULL; while(*s == ' ' || *s == '\t') s++; ps[*n] = *s; switch (*s) { diff --git a/src/drivers/amd/agesa/oem_s3.c b/src/drivers/amd/agesa/oem_s3.c index 1ca6e5b..9d13302 100644 --- a/src/drivers/amd/agesa/oem_s3.c +++ b/src/drivers/amd/agesa/oem_s3.c @@ -51,8 +51,8 @@ *len = S3_DATA_NONVOLATILE_SIZE; break; default: - *pos = 0; - *len = 0; + *pos = NULL; + *len = NULL; break; } } diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c index 1893d16..300b244 100644 --- a/src/drivers/i2c/tpm/tis.c +++ b/src/drivers/i2c/tpm/tis.c @@ -153,7 +153,7 @@ int len = tpm_transmit(sendbuf, sbuf_size, recvbuf, *rbuf_len); if (len < 10) { - *rbuf_len = 0; + *rbuf_len = NULL; return -1; } diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c index 85d0f35..e5d97a6 100644 --- a/src/drivers/intel/fsp1_1/hob.c +++ b/src/drivers/intel/fsp1_1/hob.c @@ -276,7 +276,7 @@ void print_hob_type_structure(u16 hob_type, void *hob_list_ptr) { u32 *current_hob; - u32 *next_hob = 0; + u32 *next_hob = NULL; u8 last_hob = 0; u32 current_type; const char *current_type_str; diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/drivers/intel/fsp1_1/stage_cache.c index 2d594e6..b918120 100644 --- a/src/drivers/intel/fsp1_1/stage_cache.c +++ b/src/drivers/intel/fsp1_1/stage_cache.c @@ -23,6 +23,6 @@ if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); *base = NULL; - *size = 0; + *size = NULL; } } diff --git a/src/drivers/intel/fsp2_0/mma_core.c b/src/drivers/intel/fsp2_0/mma_core.c index dfb1a1f..ad3b2cb 100644 --- a/src/drivers/intel/fsp2_0/mma_core.c +++ b/src/drivers/intel/fsp2_0/mma_core.c @@ -23,7 +23,7 @@ int fsp_locate_mma_results(const void **mma_hob, size_t *mma_hob_size) { - *mma_hob_size = 0; + *mma_hob_size = NULL; *mma_hob = fsp_find_extension_hob_by_guid(mma_results_uuid, mma_hob_size); diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c index 434eae9..67e1635 100644 --- a/src/drivers/intel/fsp2_0/stage_cache.c +++ b/src/drivers/intel/fsp2_0/stage_cache.c @@ -25,6 +25,6 @@ if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); *base = NULL; - *size = 0; + *size = NULL; } } diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c index 2eae6a9..b6a4fda 100644 --- a/src/drivers/intel/i210/i210.c +++ b/src/drivers/intel/i210/i210.c @@ -92,7 +92,7 @@ return I210_READ_ERROR; /* The checksum is computed in that way that after summarize all the */ /* data from word address 0 to 0x3f the result is 0xBABA. */ - *checksum = 0; + *checksum = NULL; for (i = 0; i < 0x3f; i++) *checksum += eep_data[i]; *checksum = I210_TARGET_CHECKSUM - *checksum; diff --git a/src/drivers/pc80/vga/vga.c b/src/drivers/pc80/vga/vga.c index 6e225e9..efcd8a7 100644 --- a/src/drivers/pc80/vga/vga.c +++ b/src/drivers/pc80/vga/vga.c @@ -204,7 +204,7 @@ if (j < height) *p = vga_font_8x16[i][j]; else - *p = 0x00; + *p = NULL; p++; } } diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 3206ba1..d996d12 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -238,7 +238,7 @@ car_set_var(prev_prefix, *prefix); car_set_var(prev_reg, reg); printk(BIOS_DEBUG, "\n%s %2.2x:", prefix, reg); - *current_char_ptr = 0; + *current_char_ptr = NULL; } if ((reg != TPM_DATA_FIFO_REG) && (bytes == 4)) { @@ -258,7 +258,7 @@ if (*current_char_ptr && !(*current_char_ptr % BYTES_PER_LINE)) { printk(BIOS_DEBUG, "\n "); - *current_char_ptr = 0; + *current_char_ptr = NULL; } (*current_char_ptr)++; printk(BIOS_DEBUG, " %2.2x", buffer[i]); diff --git a/src/drivers/xgi/common/vb_setmode.c b/src/drivers/xgi/common/vb_setmode.c index 1678b75..e47e105 100644 --- a/src/drivers/xgi/common/vb_setmode.c +++ b/src/drivers/xgi/common/vb_setmode.c @@ -4595,9 +4595,9 @@ static void XGI_GetTVPtrIndex2(unsigned short *tempbx, unsigned char *tempcl, unsigned char *tempch, struct vb_device_info *pVBInfo) { - *tempbx = 0; - *tempcl = 0; - *tempch = 0; + *tempbx = NULL; + *tempcl = NULL; + *tempch = NULL; if (pVBInfo->TVInfo & TVSetPAL) *tempbx = 1; diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 094f7ce..0cc5d79 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -175,7 +175,7 @@ if (action != EC_HOST_EVENT_GET) req.value = *value; else - *value = 0; + *value = NULL; cmd.cmd_code = EC_CMD_HOST_EVENT; cmd.cmd_version = 0; cmd.cmd_data_in = &req; @@ -207,7 +207,7 @@ if (action != EC_HOST_EVENT_GET) req.mask = (uint32_t)*value; else - *value = 0; + *value = NULL; cmd.cmd_code = hcmd; cmd.cmd_version = 0; diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 0a88c1f..e424bb6 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -801,7 +801,7 @@ struct device_tree_property *prop; *data = NULL; - *size = 0; + *size = NULL; list_for_each(prop, node->properties, list_node) { if (!strcmp(prop->prop.name, name)) { diff --git a/src/mainboard/google/beltino/lan.c b/src/mainboard/google/beltino/lan.c index 140c814..a8acf72 100644 --- a/src/mainboard/google/beltino/lan.c +++ b/src/mainboard/google/beltino/lan.c @@ -74,7 +74,7 @@ printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); offset += sizeof(key); /* move to next character */ - *high_dword = 0; + *high_dword = NULL; /* Fetch the MAC address and put the octets in the correct order to * be programmed. @@ -93,7 +93,7 @@ offset += 3; } - *low_dword = 0; + *low_dword = NULL; for (i = 0; i < 2; i++) { *low_dword |= (get_hex_digit(search_address + offset) << (4 + (i * 8))); diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index e7235ed..af1b837 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -87,7 +87,7 @@ printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); offset += sizeof(key); /* move to next character */ - *high_dword = 0; + *high_dword = NULL; /* Fetch the MAC address and put the octets in the correct order to * be programmed. @@ -106,7 +106,7 @@ offset += 3; } - *low_dword = 0; + *low_dword = NULL; for (i = 0; i < 2; i++) { *low_dword |= (get_hex_digit((char *)(search_address + offset)) << (4 + (i * 8))); diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c index 59ed111..495b0c1 100644 --- a/src/mainboard/google/jecht/lan.c +++ b/src/mainboard/google/jecht/lan.c @@ -74,7 +74,7 @@ printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); offset += sizeof(key); /* move to next character */ - *high_dword = 0; + *high_dword = NULL; /* Fetch the MAC address and put the octets in the correct order to * be programmed. @@ -93,7 +93,7 @@ offset += 3; } - *low_dword = 0; + *low_dword = NULL; for (i = 0; i < 2; i++) { *low_dword |= (get_hex_digit(search_address + offset) << (4 + (i * 8))); diff --git a/src/mainboard/google/poppy/variants/atlas/nhlt.c b/src/mainboard/google/poppy/variants/atlas/nhlt.c index 4d0fd1e..700cfc2 100644 --- a/src/mainboard/google/poppy/variants/atlas/nhlt.c +++ b/src/mainboard/google/poppy/variants/atlas/nhlt.c @@ -38,5 +38,5 @@ { *oem_id = "GOOGLE"; *oem_table_id = "ATLASMAX"; - *oem_revision = 0; + *oem_revision = NULL; } diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index 25202e6..7fbeebf 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -389,7 +389,7 @@ const struct pad_config * __weak variant_sku_gpio_table(size_t *num) { - *num = 0; + *num = NULL; return NULL; } diff --git a/src/mainboard/google/poppy/variants/baseboard/nhlt.c b/src/mainboard/google/poppy/variants/baseboard/nhlt.c index 927cb24..b5fa6a3 100644 --- a/src/mainboard/google/poppy/variants/baseboard/nhlt.c +++ b/src/mainboard/google/poppy/variants/baseboard/nhlt.c @@ -44,5 +44,5 @@ { *oem_id = "GOOGLE"; *oem_table_id = "POPPYMAX"; - *oem_revision = 0; + *oem_revision = NULL; } diff --git a/src/mainboard/google/poppy/variants/nami/nhlt.c b/src/mainboard/google/poppy/variants/nami/nhlt.c index c3096d4..7816d13 100644 --- a/src/mainboard/google/poppy/variants/nami/nhlt.c +++ b/src/mainboard/google/poppy/variants/nami/nhlt.c @@ -39,5 +39,5 @@ { *oem_id = "GOOGLE"; *oem_table_id = "NAMIMAX"; - *oem_revision = 0; + *oem_revision = NULL; } diff --git a/src/mainboard/google/poppy/variants/nautilus/nhlt.c b/src/mainboard/google/poppy/variants/nautilus/nhlt.c index 1fe3668..1b11d4c 100644 --- a/src/mainboard/google/poppy/variants/nautilus/nhlt.c +++ b/src/mainboard/google/poppy/variants/nautilus/nhlt.c @@ -39,5 +39,5 @@ { *oem_id = "GOOGLE"; *oem_table_id = "NAUTILUSMAX"; - *oem_revision = 0; + *oem_revision = NULL; } diff --git a/src/mainboard/google/poppy/variants/nocturne/nhlt.c b/src/mainboard/google/poppy/variants/nocturne/nhlt.c index 04a4482..9ac9399 100644 --- a/src/mainboard/google/poppy/variants/nocturne/nhlt.c +++ b/src/mainboard/google/poppy/variants/nocturne/nhlt.c @@ -34,5 +34,5 @@ { *oem_id = "GOOGLE"; *oem_table_id = "NOCTURNE"; - *oem_revision = 0; + *oem_revision = NULL; } diff --git a/src/mainboard/google/rambi/variants/ninja/lan.c b/src/mainboard/google/rambi/variants/ninja/lan.c index 3d08ad7..e1ce844 100644 --- a/src/mainboard/google/rambi/variants/ninja/lan.c +++ b/src/mainboard/google/rambi/variants/ninja/lan.c @@ -73,7 +73,7 @@ printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); offset += sizeof(key); /* move to next character */ - *high_dword = 0; + *high_dword = NULL; /* Fetch the MAC address and put the octets in the correct order to * be programmed. @@ -92,7 +92,7 @@ offset += 3; } - *low_dword = 0; + *low_dword = NULL; for (i = 0; i < 2; i++) { *low_dword |= (get_hex_digit(search_address + offset) << (4 + (i * 8))); diff --git a/src/mainboard/google/rambi/variants/sumo/lan.c b/src/mainboard/google/rambi/variants/sumo/lan.c index 07fe3d9..f6059f6 100644 --- a/src/mainboard/google/rambi/variants/sumo/lan.c +++ b/src/mainboard/google/rambi/variants/sumo/lan.c @@ -73,7 +73,7 @@ printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); offset += sizeof(key); /* move to next character */ - *high_dword = 0; + *high_dword = NULL; /* Fetch the MAC address and put the octets in the correct order to * be programmed. @@ -92,7 +92,7 @@ offset += 3; } - *low_dword = 0; + *low_dword = NULL; for (i = 0; i < 2; i++) { *low_dword |= (get_hex_digit(search_address + offset) << (4 + (i * 8))); diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 6db9ac6..40c6020 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -34,7 +34,7 @@ const struct pad_config __weak *variant_sku_gpio_table(size_t *num) { - *num = 0; + *num = NULL; return NULL; } diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c index 59618f6..b440634 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c @@ -346,6 +346,6 @@ u8 oemNodePresent_D(u8 Node, u8 *ret) { - *ret = 0; + *ret = NULL; return 0; } diff --git a/src/northbridge/amd/amdmct/mct/mctardk3.c b/src/northbridge/amd/amdmct/mct/mctardk3.c index ce79a52..e8a6ea4 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk3.c +++ b/src/northbridge/amd/amdmct/mct/mctardk3.c @@ -159,8 +159,8 @@ { const u8 *p; - *AddrTmgCTL = 0; - *ODC_CTL = 0; + *AddrTmgCTL = NULL; + *ODC_CTL = NULL; if (mctGet_NVbits(NV_MAX_DIMMS) == 8) { /* 8 DIMM Table */ diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c index f7a4bee..8388249 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk4.c +++ b/src/northbridge/amd/amdmct/mct/mctardk4.c @@ -84,8 +84,8 @@ { u8 const *p; - *AddrTmgCTL = 0; - *ODC_CTL = 0; + *AddrTmgCTL = NULL; + *ODC_CTL = NULL; *CMDmode = 1; // FIXME: add Ax support diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 7140007..708aed5 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -1063,7 +1063,7 @@ u32 dword; u32 dev = pDCTstat->dev_dct; - *valid = 0; + *valid = NULL; if (!pDCTstat->GangedMode) { @@ -1122,7 +1122,7 @@ lo >>= 8; if ((val >= lo) && (val < _4GB_RJ8)) { val = 0; - *valid = 0; + *valid = NULL; goto exitGetAddr; } else { *valid = 1; @@ -1145,7 +1145,7 @@ if (dword != 0) { if ((val >= dword) && (val < _4GB_RJ8)) { val = 0; - *valid = 0; + *valid = NULL; } else { *valid = 1; } diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c index 0acb6f4..b600e4b 100644 --- a/src/northbridge/amd/amdmct/mct/mctpro_d.c +++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c @@ -347,7 +347,7 @@ } } if (mct_AdjustDQSPosDelay_D(pDCTstat, DQSDelay)) { - *result = 0; + *result = NULL; } } } @@ -386,12 +386,12 @@ /* Erratum #202: disable DCache scrubber for Ax parts */ if (pDCTstat->LogicalCPUID & (AMD_DR_Ax)) { - *scrub_request = 0; + *scrub_request = NULL; pDCTstat->ErrStatus |= 1 << SB_DCBKScrubDis; } } void beforeInterleaveChannels_D(struct DCTStatStruc *pDCTstatA, u8 *enabled) { if (pDCTstatA->LogicalCPUID & (AMD_DR_Ax)) - *enabled = 0; + *enabled = NULL; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c index 82911c0..ade3b01 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c @@ -291,6 +291,6 @@ u8 oemNodePresent_D(u8 Node, u8 *ret) { - *ret = 0; + *ret = NULL; return 0; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c b/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c index d6480ab..f99bd19 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c @@ -54,8 +54,8 @@ u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, u8 *CMDmode) { - *AddrTmgCTL = 0; - *ODC_CTL = 0; + *AddrTmgCTL = NULL; + *ODC_CTL = NULL; *CMDmode = 1; if (mctGet_NVbits(NV_MAX_DIMMS) == 4) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index f751733..86ca59e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -2336,7 +2336,7 @@ u32 dword; u32 dev = pDCTstat->dev_dct; - *valid = 0; + *valid = NULL; if (!pDCTstat->GangedMode) { @@ -2395,7 +2395,7 @@ lo >>= 8; if ((val >= lo) && (val < _4GB_RJ8)) { val = 0; - *valid = 0; + *valid = NULL; goto exitGetAddr; } else { *valid = 1; @@ -2418,7 +2418,7 @@ if (dword != 0) { if ((val >= dword) && (val < _4GB_RJ8)) { val = 0; - *valid = 0; + *valid = NULL; } else { *valid = 1; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index 039a747..4ea0b95 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -287,7 +287,7 @@ ch_end = Channel + 1; } - *valid = 0; + *valid = NULL; for (ch = ch_start; ch < ch_end; ch++) { for (d = 0; d < 4; d++) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 4100b26..857d1fa 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -296,7 +296,7 @@ if (mem_info->mct_stat.GStatus & (1 << GSB_ConfigRestored)) *restored = 1; else - *restored = 0; + *restored = NULL; } } diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 27153f8..5607540 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -61,7 +61,7 @@ struct device *dev; u32 pciexbar_reg; - *base = 0; + *base = NULL; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 4c42513..571e7ff 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -38,8 +38,8 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) { - *base = 0; - *len = 0; + *base = NULL; + *len = NULL; struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 08f954d..83491e8 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -395,7 +395,7 @@ else if (*clock >= 333) *clock = 333; else - *clock = 0; + *clock = NULL; } static void lower_clock(unsigned int *const clock) { diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index f61a478..01da25f 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -38,8 +38,8 @@ u32 pciexbar_reg; u32 mask; - *base = 0; - *len = 0; + *base = NULL; + *len = NULL; pciexbar_reg = pci_read_config32(dev, index); diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index b8a2255..d1e7381 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -31,7 +31,7 @@ struct device *dev; u32 pciexbar_reg; - *base = 0; + *base = NULL; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c index 07580d1..ec1b445 100644 --- a/src/northbridge/intel/i945/rcven.c +++ b/src/northbridge/intel/i945/rcven.c @@ -246,7 +246,7 @@ continue; } - *fine = 0; + *fine = NULL; *mediumcoarse += 2; if (*mediumcoarse <= 0x40) { set_receive_enable(channel_offset, *mediumcoarse & 3, diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 6a27b57..b2179da 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -1853,12 +1853,12 @@ if (!head->length) { write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2); - *packet_size = 0; + *packet_size = NULL; return 0; } if (head->length + 4 > 4 * csr.csr.buffer_depth || head->length > *packet_size) { - *packet_size = 0; + *packet_size = NULL; return -1; } @@ -1871,7 +1871,7 @@ packet[i++] = read32(DEFAULT_HECIBAR + 0x8); *packet_size = head->length; if (!csr.csr.ready) - *packet_size = 0; + *packet_size = NULL; write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 4); return 0; } diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index d116709..6136183 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -27,8 +27,8 @@ u8 decode_pciebar(u32 *const base, u32 *const len) { - *base = 0; - *len = 0; + *base = NULL; + *len = NULL; const pci_devfn_t dev = PCI_DEV(0,0,0); u32 pciexbar = 0; u32 pciexbar_reg; diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index f31f032..c7fd713 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -1864,7 +1864,7 @@ MCHBAR16(0x58c) = (MCHBAR16(0x58c) & (u16)(~(0x3 << (bytelane*2)))) | (*medium << (bytelane*2)); } else { - *medium = 0; + *medium = NULL; (*coarse)++; MCHBAR32(0x248) = (MCHBAR32(0x248) & ~0xf0000) | (*coarse << 16); MCHBAR16(0x58c) = (MCHBAR16(0x58c) & (u16)(~0x3 << (bytelane*2))) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 8c2aaf3..3a46955 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -64,7 +64,7 @@ struct device *dev; u32 pciexbar_reg; - *base = 0; + *base = NULL; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c index 9fa6c7b..f64c706 100644 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -150,7 +150,7 @@ } else if (*tclk <= TCK_400MHZ) { *tclk = TCK_400MHZ; } else { - *tclk = 0; + *tclk = NULL; } } diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 49afdc3..cfaa7f2 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -54,8 +54,8 @@ u8 decode_pciebar(u32 *const base, u32 *const len) { - *base = 0; - *len = 0; + *base = NULL; + *len = NULL; const pci_devfn_t dev = PCI_DEV(0, 0, 0); u32 pciexbar = 0; u32 pciexbar_reg; diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 9e649b0..bb847a3 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -253,7 +253,7 @@ else if (*tCLK <= TCK_400MHZ) *tCLK = TCK_400MHZ; else - *tCLK = 0; + *tCLK = NULL; } static void select_cas_dramfreq_ddr3(struct sysinfo *s, diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index 6513476..933cee6 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -111,7 +111,7 @@ switch (trigger) { case GPIO_TRIGGER_LEVEL_LOW: *edge = SCI_TRIGGER_LEVEL; - *level = 0; + *level = NULL; break; case GPIO_TRIGGER_LEVEL_HIGH: *edge = SCI_TRIGGER_LEVEL; @@ -119,7 +119,7 @@ break; case GPIO_TRIGGER_EDGE_LOW: *edge = SCI_TRIGGER_EDGE; - *level = 0; + *level = NULL; break; case GPIO_TRIGGER_EDGE_HIGH: *edge = SCI_TRIGGER_EDGE; diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 23c650a..583e207 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -398,7 +398,7 @@ *inform_pc = 1; } else { cdclk = GT_CDCLK_450; - *inform_pc = 0; + *inform_pc = NULL; } /* Check for fixed fused clock */ diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index afb6038..9a411ae 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -42,8 +42,8 @@ { u32 pciexbar_reg; - *base = 0; - *len = 0; + *base = NULL; + *len = NULL; pciexbar_reg = pci_read_config32(dev, index); diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 02ab886..c90d867 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -376,7 +376,7 @@ static acpi_tstate_t *soc_get_tss_table(int *entries) { - *entries = 0; + *entries = NULL; return NULL; } -- To view, visit https://review.coreboot.org/27096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie9d22a4d6bab1caf61f4f89e236ae3cd2f7fb42c Gerrit-Change-Number: 27096 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: util/abuild: Fix building when not in coreboot root dir
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27095 ) Change subject: util/abuild: Fix building when not in coreboot root dir ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28982/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74880/ : SUCCESS -- To view, visit https://review.coreboot.org/27095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibe54096f275a05bda745ae2cc76c0109281c0c4b Gerrit-Change-Number: 27095 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 20:46:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: util/abuild: Fix building when not in coreboot root dir
by Arthur Heymans (Code Review) 13 Jun '18

13 Jun '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27095 to look at the new patch set (#2). Change subject: util/abuild: Fix building when not in coreboot root dir ...................................................................... util/abuild: Fix building when not in coreboot root dir Change-Id: Ibe54096f275a05bda745ae2cc76c0109281c0c4b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/abuild/abuild 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/27095/2 -- To view, visit https://review.coreboot.org/27095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibe54096f275a05bda745ae2cc76c0109281c0c4b Gerrit-Change-Number: 27095 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: util/abuild: Fix building when not in coreboot root dir
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27095 ) Change subject: util/abuild: Fix building when not in coreboot root dir ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28981/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74879/ : SUCCESS -- To view, visit https://review.coreboot.org/27095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibe54096f275a05bda745ae2cc76c0109281c0c4b Gerrit-Change-Number: 27095 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 20:38:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: util/abuild: Fix building when not in coreboot root dir
by Arthur Heymans (Code Review) 13 Jun '18

13 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27095 Change subject: util/abuild: Fix building when not in coreboot root dir ...................................................................... util/abuild: Fix building when not in coreboot root dir Change-Id: Ibe54096f275a05bda745ae2cc76c0109281c0c4b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/abuild/abuild 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/27095/1 diff --git a/util/abuild/abuild b/util/abuild/abuild index d8f4882..28e0eb6 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -454,7 +454,7 @@ required_arches=$(egrep "^CONFIG_ARCH_(BOOTBLOCK|R.MSTAGE|VERSTAGE)" "$TARGET/${BUILD_NAME}/config.build" | \ sed "s,^CONFIG_ARCH_[^_]*_$[^=]*$=.*$,\1," |sort -u |tr 'A-Z\n\r' 'a-z ') # shellcheck disable=SC2016,SC2059 - missing_arches=$(printf 'include .xcompile\nall: ; @echo $(foreach arch,'"$required_arches"',$(if $(filter $(arch),$(SUBARCH_SUPPORTED)),,$(arch)))' | make --no-print-directory -f -) + missing_arches=$(printf 'include .xcompile\nall: ; @echo $(foreach arch,'"$required_arches"',$(if $(filter $(arch),$(SUBARCH_SUPPORTED)),,$(arch)))' | $MAKE --no-print-directory -f -) if [ -n "$missing_arches" ]; then printf "skipping %s because we're missing compilers for (%s)\n" "$BUILD_NAME" "$missing_arches" return @@ -696,7 +696,7 @@ clean_work=true ;; -o|--outdir) shift - TARGET=$1; shift + TARGET=$1; MAKE="$MAKE -C $1"; shift ;; -x|--chromeos) shift chromeos=true -- To view, visit https://review.coreboot.org/27095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibe54096f275a05bda745ae2cc76c0109281c0c4b Gerrit-Change-Number: 27095 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in libgfxinit[master]: gma registers: Add Read_GTT() procedure
by Nico Huber (Code Review) 13 Jun '18

13 Jun '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/27057 ) Change subject: gma registers: Add Read_GTT() procedure ...................................................................... Patch Set 1: Verified+1 -- To view, visit https://review.coreboot.org/27057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0f8091b8958d0c228430fad4b8343fc362a2dbb7 Gerrit-Change-Number: 27057 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 13 Jun 2018 20:21:35 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in libgfxinit[master]: gma registers: Separate 32- and 64-bit GTT access
by Nico Huber (Code Review) 13 Jun '18

13 Jun '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/27056 ) Change subject: gma registers: Separate 32- and 64-bit GTT access ...................................................................... Patch Set 1: Verified+1 Could put arbitration into a separate package. Or maybe check if the dead code (static config case) can be removed automatically. -- To view, visit https://review.coreboot.org/27056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib6f21b71c434a9cbdd5cdfa3697da2b2e86750f4 Gerrit-Change-Number: 27056 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 13 Jun 2018 20:19:51 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in libgfxinit[master]: gma registers: Draw usage of Config.Fence_Count into the code
by Nico Huber (Code Review) 13 Jun '18

13 Jun '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/27055 ) Change subject: gma registers: Draw usage of Config.Fence_Count into the code ...................................................................... Patch Set 1: Verified+1 (1 comment) https://review.coreboot.org/#/c/27055/1/common/hw-gfx-gma-registers.adb File common/hw-gfx-gma-registers.adb: https://review.coreboot.org/#/c/27055/1/common/hw-gfx-gma-registers.adb@64 PS1, Line 64: subtype Fence_Range is Registers_Range range 0 .. 31; move to Config maybe -- To view, visit https://review.coreboot.org/27055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2ab37f4cd9e6b4d37353ae4fd11d7e5a686d166f Gerrit-Change-Number: 27055 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 13 Jun 2018 20:12:13 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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