coreboot-gerrit June 2018

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Change in coreboot[master]: [WIP]soc/intel/common: Add common code to report platform information
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

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Change in coreboot[master]: [WIP]soc/intel/common: Add bootblock common stage file
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18457 ) Change subject: [WIP]soc/intel/common: Add bootblock common stage file ...................................................................... Patch Set 16: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28991/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74889/ : SUCCESS -- To view, visit https://review.coreboot.org/18457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If84c08d33f6f8fd3cd9722ee893653f1d1ae90c1 Gerrit-Change-Number: 18457 Gerrit-PatchSet: 16 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 13 Jun 2018 22:20:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP] soc/intel/cannonlake: Use bootblock common stage
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

1 0

Change in coreboot[master]: [WIP] soc/intel/apollolake: Use bootblock common stage
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25802 ) Change subject: [WIP] soc/intel/apollolake: Use bootblock common stage ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28992/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74890/ : SUCCESS -- To view, visit https://review.coreboot.org/25802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I319453c902632f26eec63ab9c1e9bb6956b466fb Gerrit-Change-Number: 25802 Gerrit-PatchSet: 9 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 22:15:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP]soc/intel/common: Add common code to report platform information
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25810 ) Change subject: [WIP]soc/intel/common: Add common code to report platform information ...................................................................... Patch Set 5: (28 comments) https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/bootb… File src/soc/intel/common/basecode/bootblock/report_platform.c: https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/bootb… PS5, Line 32: __weak const struct cpu_info* soc_get_cpu_id_table(void) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/bootb… PS5, Line 38: __weak const struct mch_info* soc_get_mch_id_table(void) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/bootb… PS5, Line 44: __weak const struct pch_info* soc_get_pch_id_table(void) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/bootb… PS5, Line 50: __weak const struct igd_info* soc_get_igd_id_table(void) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… File src/soc/intel/common/basecode/include/intelbasecode/report_platform.h: https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 19: struct cpu_info{ missing space after struct definition https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 20: u32 cpuid; code indent should use tabs where possible https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 20: u32 cpuid; please, no spaces at the start of a line https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 21: const char *name; code indent should use tabs where possible https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 21: const char *name; please, no spaces at the start of a line https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 24: struct mch_info{ missing space after struct definition https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 25: u16 mchid; code indent should use tabs where possible https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 25: u16 mchid; please, no spaces at the start of a line https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 26: const char *name; code indent should use tabs where possible https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 26: const char *name; please, no spaces at the start of a line https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 29: struct pch_info{ missing space after struct definition https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 30: u16 lpcid; code indent should use tabs where possible https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 30: u16 lpcid; please, no spaces at the start of a line https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 31: const char *name; code indent should use tabs where possible https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 31: const char *name; please, no spaces at the start of a line https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 34: struct igd_info{ missing space after struct definition https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 35: u16 igdid; code indent should use tabs where possible https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 35: u16 igdid; please, no spaces at the start of a line https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 36: const char *name; code indent should use tabs where possible https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 36: const char *name; please, no spaces at the start of a line https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 40: const struct cpu_info* soc_get_cpu_id_table(void); "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 43: const struct mch_info* soc_get_mch_id_table(void); "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 46: const struct pch_info* soc_get_pch_id_table(void); "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/25810/5/src/soc/intel/common/basecode/inclu… PS5, Line 49: const struct igd_info* soc_get_igd_id_table(void); "foo* bar" should be "foo *bar" -- To view, visit https://review.coreboot.org/25810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id1497b72f784db00a334544f6c5ddc2774049107 Gerrit-Change-Number: 25810 Gerrit-PatchSet: 5 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 22:11:11 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: [WIP] soc/intel/cannonlake: Use bootblock common stage
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25811 ) Change subject: [WIP] soc/intel/cannonlake: Use bootblock common stage ...................................................................... Patch Set 6: (4 comments) https://review.coreboot.org/#/c/25811/6/src/soc/intel/cannonlake/bootblock/… File src/soc/intel/cannonlake/bootblock/report_platform.c: https://review.coreboot.org/#/c/25811/6/src/soc/intel/cannonlake/bootblock/… PS6, Line 55: const struct cpu_info* soc_get_cpu_id_table(void) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/25811/6/src/soc/intel/cannonlake/bootblock/… PS6, Line 60: const struct mch_info* soc_get_mch_id_table(void) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/25811/6/src/soc/intel/cannonlake/bootblock/… PS6, Line 65: const struct pch_info* soc_get_pch_id_table(void) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/25811/6/src/soc/intel/cannonlake/bootblock/… PS6, Line 70: const struct igd_info* soc_get_igd_id_table(void) "foo* bar" should be "foo *bar" -- To view, visit https://review.coreboot.org/25811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4397c6d599a9f4ef235755835db3f4d22f81674e Gerrit-Change-Number: 25811 Gerrit-PatchSet: 6 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 22:11:00 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: [WIP]soc/intel/common: Add bootblock common stage file
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18457 ) Change subject: [WIP]soc/intel/common: Add bootblock common stage file ...................................................................... Patch Set 16: (3 comments) https://review.coreboot.org/#/c/18457/16/src/soc/intel/common/basecode/boot… File src/soc/intel/common/basecode/bootblock/bootblock.c: https://review.coreboot.org/#/c/18457/16/src/soc/intel/common/basecode/boot… PS16, Line 178: bb_ops->bootblock_cpu_init = &bootblock_cmn_cpu_init; please, no space before tabs https://review.coreboot.org/#/c/18457/16/src/soc/intel/common/basecode/boot… PS16, Line 181: __weak void soc_update_ops(struct bootblock_ops* ops) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/18457/16/src/soc/intel/common/basecode/incl… File src/soc/intel/common/basecode/include/intelbasecode/bootblock.h: https://review.coreboot.org/#/c/18457/16/src/soc/intel/common/basecode/incl… PS16, Line 36: void soc_update_ops(struct bootblock_ops* soc_ops); "foo* bar" should be "foo *bar" -- To view, visit https://review.coreboot.org/18457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If84c08d33f6f8fd3cd9722ee893653f1d1ae90c1 Gerrit-Change-Number: 18457 Gerrit-PatchSet: 16 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 13 Jun 2018 22:09:45 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/apollolake: unify definition for spi base address
by Bora Guvendik (Code Review) 13 Jun '18

13 Jun '18

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/27097 Change subject: soc/intel/apollolake: unify definition for spi base address ...................................................................... soc/intel/apollolake: unify definition for spi base address Use SPI_BASE_ADDRESS instead of PRERAM_SPI_BASE_ADDRESS like big core in order make common code implementation straightforward. Change-Id: Ibcb013fc95de29234253e89c9ca100cc468d44f6 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/include/soc/iomap.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/27097/1 diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 81843a4..09ea91e 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -106,7 +106,7 @@ enable_pm_timer_emulation(); - fast_spi_early_init(PRERAM_SPI_BASE_ADDRESS); + fast_spi_early_init(SPI_BASE_ADDRESS); fast_spi_cache_bios_region(); diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 9a2500c..479882f 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -47,7 +47,7 @@ #define HECI1_BASE_ADDRESS 0xfed1a000 /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ -#define PRERAM_SPI_BASE_ADDRESS 0xfe010000 +#define SPI_BASE_ADDRESS 0xfe010000 #define EARLY_GSPI_BASE_ADDRESS 0xfe011000 /* Temporary BAR for early I2C bus access */ -- To view, visit https://review.coreboot.org/27097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibcb013fc95de29234253e89c9ca100cc468d44f6 Gerrit-Change-Number: 27097 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com>

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Change in coreboot[master]: src: Use NULL instead of 0 for pointer
by Elyes HAOUAS (Code Review) 13 Jun '18

13 Jun '18

Elyes HAOUAS has abandoned this change. ( https://review.coreboot.org/27096 ) Change subject: src: Use NULL instead of 0 for pointer ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/27096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ie9d22a4d6bab1caf61f4f89e236ae3cd2f7fb42c Gerrit-Change-Number: 27096 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src: Use NULL instead of 0 for pointer
by Elyes HAOUAS (Code Review) 13 Jun '18

13 Jun '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27096 to look at the new patch set (#6). Change subject: src: Use NULL instead of 0 for pointer ...................................................................... src: Use NULL instead of 0 for pointer Change-Id: Ie9d22a4d6bab1caf61f4f89e236ae3cd2f7fb42c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/exception.c M src/drivers/i2c/tpm/tis.c M src/drivers/intel/fsp1_1/hob.c M src/drivers/intel/fsp2_0/mma_core.c M src/drivers/spi/tpm/tpm.c M src/drivers/xgi/common/vb_setmode.c M src/ec/google/chromeec/ec.c M src/mainboard/google/beltino/lan.c M src/mainboard/google/butterfly/mainboard.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/poppy/variants/atlas/nhlt.c M src/mainboard/google/poppy/variants/baseboard/gpio.c M src/mainboard/google/poppy/variants/baseboard/nhlt.c M src/mainboard/google/poppy/variants/nami/nhlt.c M src/mainboard/google/poppy/variants/nautilus/nhlt.c M src/mainboard/google/poppy/variants/nocturne/nhlt.c M src/mainboard/google/rambi/variants/ninja/lan.c M src/mainboard/google/rambi/variants/sumo/lan.c M src/mainboard/google/reef/mainboard.c M src/northbridge/amd/amdmct/mct/mctardk3.c M src/northbridge/amd/amdmct/mct/mctardk4.c M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct/mctpro_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/intel/pineview/raminit.c M src/soc/amd/stoneyridge/gpio.c M src/soc/intel/broadwell/igd.c M src/soc/intel/common/block/acpi/acpi.c 31 files changed, 51 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/27096/6 -- To view, visit https://review.coreboot.org/27096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie9d22a4d6bab1caf61f4f89e236ae3cd2f7fb42c Gerrit-Change-Number: 27096 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit June 2018