coreboot-gerrit June 2018

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Change in coreboot[master]: Documentation: Add SandyBridge NRI feature matrix
by Patrick Rudolph (Code Review) 13 Jun '18

13 Jun '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27093 to look at the new patch set (#3). Change subject: Documentation: Add SandyBridge NRI feature matrix ...................................................................... Documentation: Add SandyBridge NRI feature matrix Change-Id: I69b014430802de132c8d9b6c8409bc762b995468 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/northbridge/intel/sandybridge/index.md A Documentation/northbridge/intel/sandybridge/nri_features.md 2 files changed, 90 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/27093/3 -- To view, visit https://review.coreboot.org/27093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I69b014430802de132c8d9b6c8409bc762b995468 Gerrit-Change-Number: 27093 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: Documentation: Add SandyBridge NRI feature matrix
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27093 ) Change subject: Documentation: Add SandyBridge NRI feature matrix ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28973/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74871/ : SUCCESS -- To view, visit https://review.coreboot.org/27093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I69b014430802de132c8d9b6c8409bc762b995468 Gerrit-Change-Number: 27093 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 13 Jun 2018 17:15:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP]src/cpu/intel/car: Update microcode before setting up CAR
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27091 ) Change subject: [WIP]src/cpu/intel/car: Update microcode before setting up CAR ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/74873/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/28975/ : SUCCESS -- To view, visit https://review.coreboot.org/27091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8bd192f3f345651db0010239f99293ae63b00652 Gerrit-Change-Number: 27091 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 17:11:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Documentation: Add rules for writing Documentation
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26602 ) Change subject: Documentation: Add rules for writing Documentation ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28974/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74872/ : SUCCESS -- To view, visit https://review.coreboot.org/26602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic3808a0a10ddc8064d185e0920dcd9f60c435419 Gerrit-Change-Number: 26602 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 17:11:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Documentation: Add SandyBridge NRI feature matrix
by Arthur Heymans (Code Review) 13 Jun '18

13 Jun '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27093 ) Change subject: Documentation: Add SandyBridge NRI feature matrix ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/27093/2/Documentation/northbridge/intel/san… File Documentation/northbridge/intel/sandybridge/nri_features.md: https://review.coreboot.org/#/c/27093/2/Documentation/northbridge/intel/san… PS2, Line 8: bla bla blub leftover? https://review.coreboot.org/#/c/27093/2/Documentation/northbridge/intel/san… PS2, Line 12: * No known errors. Might be good to add that it needs to be at a fixed offset in flash (mrc.bin cannot be relocated) -- To view, visit https://review.coreboot.org/27093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I69b014430802de132c8d9b6c8409bc762b995468 Gerrit-Change-Number: 27093 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 13 Jun 2018 17:10:50 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: [WIP]src/cpu/intel/car: Update microcode before setting up CAR
by Arthur Heymans (Code Review) 13 Jun '18

13 Jun '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27091 to look at the new patch set (#3). Change subject: [WIP]src/cpu/intel/car: Update microcode before setting up CAR ...................................................................... [WIP]src/cpu/intel/car: Update microcode before setting up CAR This reuses cbfstool adding a FIT table with pointers to microcode headers meant for later Intel CPUs. Change-Id: I8bd192f3f345651db0010239f99293ae63b00652 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/p4-netburst/cache_as_ram_bootblock.S A src/cpu/intel/microcode/microcode.S M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_LGA775/Makefile.inc 4 files changed, 161 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/27091/3 -- To view, visit https://review.coreboot.org/27091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I8bd192f3f345651db0010239f99293ae63b00652 Gerrit-Change-Number: 27091 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Documentation: Add SandyBridge NRI feature matrix
by Patrick Rudolph (Code Review) 13 Jun '18

13 Jun '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27093 to look at the new patch set (#2). Change subject: Documentation: Add SandyBridge NRI feature matrix ...................................................................... Documentation: Add SandyBridge NRI feature matrix Change-Id: I69b014430802de132c8d9b6c8409bc762b995468 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/northbridge/intel/sandybridge/index.md A Documentation/northbridge/intel/sandybridge/nri_features.md 2 files changed, 89 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/27093/2 -- To view, visit https://review.coreboot.org/27093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I69b014430802de132c8d9b6c8409bc762b995468 Gerrit-Change-Number: 27093 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Documentation: Add SandyBridge NRI feature matrix
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27093 ) Change subject: Documentation: Add SandyBridge NRI feature matrix ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/74870/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/28972/ : SUCCESS -- To view, visit https://review.coreboot.org/27093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I69b014430802de132c8d9b6c8409bc762b995468 Gerrit-Change-Number: 27093 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 16:58:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Documentation: Add SandyBridge NRI feature matrix
by Patrick Rudolph (Code Review) 13 Jun '18

13 Jun '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27093 Change subject: Documentation: Add SandyBridge NRI feature matrix ...................................................................... Documentation: Add SandyBridge NRI feature matrix Change-Id: I69b014430802de132c8d9b6c8409bc762b995468 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/northbridge/intel/sandybridge/index.md A Documentation/northbridge/intel/sandybridge/nri_features.md 2 files changed, 88 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/27093/1 diff --git a/Documentation/northbridge/intel/sandybridge/index.md b/Documentation/northbridge/intel/sandybridge/index.md index 815abce..dcb090a 100644 --- a/Documentation/northbridge/intel/sandybridge/index.md +++ b/Documentation/northbridge/intel/sandybridge/index.md @@ -5,3 +5,4 @@ ## Topics - [Native Ram Initialization](nri.md) +- [RAM initialization feature matrix](nri_features.md) diff --git a/Documentation/northbridge/intel/sandybridge/nri_features.md b/Documentation/northbridge/intel/sandybridge/nri_features.md new file mode 100644 index 0000000..4f48af1 --- /dev/null +++ b/Documentation/northbridge/intel/sandybridge/nri_features.md @@ -0,0 +1,87 @@ +# RAM initialization feature matrix + +## Options + +1. Native raminit + * Open Source + * Native Raminit is working for most frequencies on most boards. + * There might be errors to fix. +2. mrc.bin raminit + * Closed Source (aka BLOB) + * No known errors. + +## Native raminit implemented features + +```eval_rst ++---------------------------+----------------------+-------------+---------+---------------------+ +| Option | Supported | Implemented | Working | Description | ++===========================+======================+=============+=========+=====================+ +| **Supported channels** | ++---------------------------+----------------------+-------------+---------+---------------------+ +| single and dual channel | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| Up to 4 slots | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| Up to 4 ranks per channel | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| **Supported frequencies** | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-1066 (533MHz) | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-1600 (800MHz) | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-1866 (933MHz) | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-2133 (1066MHz) | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-1400 (700MHz) | yes (IvyBridge only) | yes | yes | Since Coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-1800 (900MHz) | yes (IvyBridge only) | yes | yes | Since Coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-2000 (1000MHz) | yes (IvyBridge only) | yes | yes | Since Coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-2200 (1100MHz) | yes (IvyBridge only) | yes | yes | Since Coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-2400 (1200MHz) | yes (IvyBridge only) | yes | yes | Since Coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| DDR3-1800 (900MHz) | yes (IvyBridge only) | yes | yes | Since Coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| **Supported CAS latencies** | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL6 | yes | yes | ? | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL7 | yes | yes | ? | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL8 | yes | yes | ? | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL9 | yes | yes | ? | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL10 | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL11 | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL12 | yes | yes | ? | Since Coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL13 | yes | yes | yes | Since Coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL14 | yes | yes | ? | Since Coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| CL15 | yes | yes | ? | Since Coreboot 4.6 | ++---------------------------+----------------------+-------------+---------+---------------------+ +| **MRC cache (stored timings of last training)** | ++---------------------------+----------------------+-------------+---------+---------------------+ +| S3 | yes | yes | yes | | ++---------------------------+----------------------+-------------+---------+---------------------+ +| normal boot | yes | yes | yes | reset on CRC16 diff | ++---------------------------+----------------------+-------------+---------+---------------------+ +| **XMP support** | ++---------------------------+----------------------+-------------+---------+---------------------+ +| XMP Profile 1 | yes | yes | yes | only 1.5 V profiles | ++---------------------------+----------------------+-------------+---------+---------------------+ +| XMP Profile 2 | yes | yes | no | not activated | ++---------------------------+----------------------+-------------+---------+---------------------+ +| **ECC support** | ++---------------------------+----------------------+-------------+---------+---------------------+ +| ECC | yes | no | | | ++---------------------------+----------------------+-------------+---------+---------------------+ +``` -- To view, visit https://review.coreboot.org/27093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I69b014430802de132c8d9b6c8409bc762b995468 Gerrit-Change-Number: 27093 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: mainboard/google/kahlee: Enable keyboard backlight for careena specif...
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27021 ) Change subject: mainboard/google/kahlee: Enable keyboard backlight for careena specific SKU ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28971/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74869/ : SUCCESS -- To view, visit https://review.coreboot.org/27021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7d302c4f50528b0e6b7ef4d990f342a69cff34f5 Gerrit-Change-Number: 27021 Gerrit-PatchSet: 6 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 15:35:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit June 2018