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Change in coreboot[master]: cpu/intel/model_206ax: Use postcar stage to tear down CAR
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26713 ) Change subject: cpu/intel/model_206ax: Use postcar stage to tear down CAR ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/73718/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/27840/ : SUCCESS -- To view, visit https://review.coreboot.org/26713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0f19bbddbf23cbf29a7846479c854980a5286547 Gerrit-Change-Number: 26713 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 22:17:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: cpu/intel/cache_as_ram: Compute number var MTRR's
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26712 ) Change subject: cpu/intel/cache_as_ram: Compute number var MTRR's ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/73717/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/27839/ : SUCCESS -- To view, visit https://review.coreboot.org/26712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia4afdacc2d12db5ea49eb7ae2b4f4295981a6d8b Gerrit-Change-Number: 26712 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 22:16:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: cpu/intel/model_206ax: Use postcar stage to tear down CAR
by Arthur Heymans (Code Review) 30 May '18

30 May '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26713 Change subject: cpu/intel/model_206ax: Use postcar stage to tear down CAR ...................................................................... cpu/intel/model_206ax: Use postcar stage to tear down CAR Tested on Lenovo Thinkpad X220. Postcar get's loaded by romstage which in turn loads the ramstage. On S3 both get loaded from the external stage cache. Change-Id: I0f19bbddbf23cbf29a7846479c854980a5286547 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_206ax/cache_as_ram.inc A src/cpu/intel/model_206ax/teardown_car.S M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/ram_calc.c 6 files changed, 68 insertions(+), 127 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/26713/1 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index b30cfa1..0bcf228 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -23,6 +23,8 @@ select TSC_SYNC_MFENCE select CPU_INTEL_COMMON select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select POSTCAR_STAGE + select POSTCAR_CONSOLE config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index 1e04554..a7ae02c 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -13,9 +13,11 @@ romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc romstage-y += ../car/romstage.c +postcar-y += teardown_car.S diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 92d2663..4b0016e 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -189,126 +189,7 @@ post_code(0x29) /* Call romstage.c main function. */ call romstage_main - /* Save return value from romstage_main. It contains the stack to use - * after cache-as-ram is torn down. It also contains the information - * for setting up MTRRs. */ - movl %eax, %esp - - post_code(0x30) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x31) - - /* Disable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - andl $(~MTRR_DEF_TYPE_EN), %eax - wrmsr - - post_code(0x32) - - /* Disable the no eviction run state */ - movl $NoEvictMod_MSR, %ecx - rdmsr - andl $~2, %eax - wrmsr - - invd - - /* Disable the no eviction mode */ - rdmsr - andl $~1, %eax - wrmsr - - post_code(0x33) - - /* Enable cache. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x36) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x38) - - /* Clear all of the variable MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx - clr %eax - clr %edx - -1: - testl %ebx, %ebx - jz 1f - wrmsr /* Write MTRR base. */ - inc %ecx - wrmsr /* Write MTRR mask. */ - inc %ecx - dec %ebx - jmp 1b - -1: - /* Get number of MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx -2: - testl %ebx, %ebx - jz 2f - - /* Low 32 bits of MTRR base. */ - popl %eax - /* Upper 32 bits of MTRR base. */ - popl %edx - /* Write MTRR base. */ - wrmsr - inc %ecx - /* Low 32 bits of MTRR mask. */ - popl %eax - /* Upper 32 bits of MTRR mask. */ - popl %edx - /* Write MTRR mask. */ - wrmsr - inc %ecx - - dec %ebx - jmp 2b -2: - - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x3a) - - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr - - post_code(0x3b) - - /* Invalidate the cache again. */ - invd - - post_code(0x3c) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - call romstage_after_car + /* We don't return here */ .Lhlt: post_code(POST_DEAD_CODE) diff --git a/src/cpu/intel/model_206ax/teardown_car.S b/src/cpu/intel/model_206ax/teardown_car.S new file mode 100644 index 0000000..28f0cff --- /dev/null +++ b/src/cpu/intel/model_206ax/teardown_car.S @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> + +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + +#define NoEvictMod_MSR 0x2e0 + +.global chipset_teardown_car +chipset_teardown_car: + pop %esp + + post_code(0x30) + + /* Disable cache. */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + post_code(0x31) + + /* Disable MTRR. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + andl $(~MTRR_DEF_TYPE_EN), %eax + wrmsr + + /* Disable the no eviction run state */ + movl $NoEvictMod_MSR, %ecx + rdmsr + andl $~2, %eax + wrmsr + andl $~1, %eax + wrmsr + + post_code(0x32) + + /* Return to caller. */ + jmp *%esp diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index d08b141..3d8da0c 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -46,4 +46,6 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +postcar-y += ram_calc.c + endif diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c index 43442f1..9e3816f 100644 --- a/src/northbridge/intel/sandybridge/ram_calc.c +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -44,8 +44,6 @@ return (void *) smm_region_start(); } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* setup_stack_and_mtrrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ void *setup_stack_and_mtrrs(void) @@ -53,7 +51,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ @@ -77,8 +75,8 @@ * handler as well as using the TSEG region for other purposes. */ postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. - */ - return postcar_commit_mtrrs(&pcf); + run_postcar_phase(&pcf); + + /* We don't return here */ + return NULL; } -- To view, visit https://review.coreboot.org/26713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0f19bbddbf23cbf29a7846479c854980a5286547 Gerrit-Change-Number: 26713 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: cpu/intel/cache_as_ram: Compute number var MTRR's
by Arthur Heymans (Code Review) 30 May '18

30 May '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26712 Change subject: cpu/intel/cache_as_ram: Compute number var MTRR's ...................................................................... cpu/intel/cache_as_ram: Compute number var MTRR's Compute the number of variable MTRR's during runtime. Change-Id: Ia4afdacc2d12db5ea49eb7ae2b4f4295981a6d8b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/cache_as_ram_ht.inc M src/cpu/intel/haswell/cache_as_ram.inc M src/cpu/intel/model_206ax/cache_as_ram.inc M src/cpu/intel/model_6ex/cache_as_ram.inc 4 files changed, 156 insertions(+), 97 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/26712/1 diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index e716caf..1497169 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -39,21 +39,32 @@ andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax jz ap_init - /* Zero out all fixed range and variable range MTRRs. - * For hyper-threaded CPUs these are shared. - */ - movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) >> 1), %edi - xorl %eax, %eax - xorl %edx, %edx -clear_mtrrs: - movw (%esi), %bx - movzx %bx, %ecx - wrmsr - add $2, %esi - dec %edi - jnz clear_mtrrs + /* Clear/disable fixed MTRRs */ + mov $fixed_mtrr_list_size, %ebx + xor %eax, %eax + xor %edx, %edx +clear_fixed_mtrr: + add $-2, %ebx + movzwl fixed_mtrr_list(%ebx), %ecx + wrmsr + jnz clear_fixed_mtrr + + /* Figure put how many MTRRs we have, and clear them out */ + mov $MTRR_CAP_MSR, %ecx + rdmsr + movzb %al, %ebx /* Number of variable MTRRs */ + mov $MTRR_PHYS_BASE(0), %ecx + xor %eax, %eax + xor %edx, %edx + +clear_var_mtrr: + wrmsr + inc %ecx + wrmsr + inc %ecx + dec %ebx + jnz clear_var_mtrr post_code(0x21) /* Configure the default memory type to uncacheable. */ @@ -452,15 +463,16 @@ hlt jmp .Lhlt -mtrr_table: - /* Fixed MTRRs */ - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F - /* Variable MTRRs */ - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F -mtrr_table_end: +fixed_mtrr_list: + .word MTRR_FIX_64K_00000 + .word MTRR_FIX_16K_80000 + .word MTRR_FIX_16K_A0000 + .word MTRR_FIX_4K_C0000 + .word MTRR_FIX_4K_C8000 + .word MTRR_FIX_4K_D0000 + .word MTRR_FIX_4K_D8000 + .word MTRR_FIX_4K_E0000 + .word MTRR_FIX_4K_E8000 + .word MTRR_FIX_4K_F0000 + .word MTRR_FIX_4K_F8000 +fixed_mtrr_list_size = . - fixed_mtrr_list \ No newline at end of file diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 388c2ea..98bf3e3 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -52,18 +52,32 @@ jc wait_for_sipi post_code(0x21) - /* Zero out all fixed range and variable range MTRRs. */ - movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) >> 1), %edi - xorl %eax, %eax - xorl %edx, %edx -clear_mtrrs: - movw (%esi), %bx - movzx %bx, %ecx + /* Clear/disable fixed MTRRs */ + mov $fixed_mtrr_list_size, %ebx + xor %eax, %eax + xor %edx, %edx + +clear_fixed_mtrr: + add $-2, %ebx + movzwl fixed_mtrr_list(%ebx), %ecx wrmsr - add $2, %esi - dec %edi - jnz clear_mtrrs + jnz clear_fixed_mtrr + + /* Figure put how many MTRRs we have, and clear them out */ + mov $MTRR_CAP_MSR, %ecx + rdmsr + movzb %al, %ebx /* Number of variable MTRRs */ + mov $MTRR_PHYS_BASE(0), %ecx + xor %eax, %eax + xor %edx, %edx + +clear_var_mtrr: + wrmsr + inc %ecx + wrmsr + inc %ecx + dec %ebx + jnz clear_var_mtrr post_code(0x22) /* Configure the default memory type to uncacheable. */ @@ -282,16 +296,16 @@ hlt jmp .Lhlt -mtrr_table: - /* Fixed MTRRs */ - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F - /* Variable MTRRs */ - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F - .word 0x210, 0x211, 0x212, 0x213 -mtrr_table_end: +fixed_mtrr_list: + .word MTRR_FIX_64K_00000 + .word MTRR_FIX_16K_80000 + .word MTRR_FIX_16K_A0000 + .word MTRR_FIX_4K_C0000 + .word MTRR_FIX_4K_C8000 + .word MTRR_FIX_4K_D0000 + .word MTRR_FIX_4K_D8000 + .word MTRR_FIX_4K_E0000 + .word MTRR_FIX_4K_E8000 + .word MTRR_FIX_4K_F0000 + .word MTRR_FIX_4K_F8000 +fixed_mtrr_list_size = . - fixed_mtrr_list \ No newline at end of file diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index d1678bf..92d2663 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -52,18 +52,33 @@ jc wait_for_sipi post_code(0x21) - /* Zero out all fixed range and variable range MTRRs. */ - movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) >> 1), %edi - xorl %eax, %eax - xorl %edx, %edx -clear_mtrrs: - movw (%esi), %bx - movzx %bx, %ecx + + /* Clear/disable fixed MTRRs */ + mov $fixed_mtrr_list_size, %ebx + xor %eax, %eax + xor %edx, %edx + +clear_fixed_mtrr: + add $-2, %ebx + movzwl fixed_mtrr_list(%ebx), %ecx wrmsr - add $2, %esi - dec %edi - jnz clear_mtrrs + jnz clear_fixed_mtrr + + /* Figure put how many MTRRs we have, and clear them out */ + mov $MTRR_CAP_MSR, %ecx + rdmsr + movzb %al, %ebx /* Number of variable MTRRs */ + mov $MTRR_PHYS_BASE(0), %ecx + xor %eax, %eax + xor %edx, %edx + +clear_var_mtrr: + wrmsr + inc %ecx + wrmsr + inc %ecx + dec %ebx + jnz clear_var_mtrr post_code(0x22) /* Configure the default memory type to uncacheable. */ @@ -300,16 +315,16 @@ hlt jmp .Lhlt -mtrr_table: - /* Fixed MTRRs */ - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F - /* Variable MTRRs */ - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F - .word 0x210, 0x211, 0x212, 0x213 -mtrr_table_end: +fixed_mtrr_list: + .word MTRR_FIX_64K_00000 + .word MTRR_FIX_16K_80000 + .word MTRR_FIX_16K_A0000 + .word MTRR_FIX_4K_C0000 + .word MTRR_FIX_4K_C8000 + .word MTRR_FIX_4K_D0000 + .word MTRR_FIX_4K_D8000 + .word MTRR_FIX_4K_E0000 + .word MTRR_FIX_4K_E8000 + .word MTRR_FIX_4K_F0000 + .word MTRR_FIX_4K_F8000 +fixed_mtrr_list_size = . - fixed_mtrr_list \ No newline at end of file diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 4b85c07..3f048a5 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -34,18 +34,35 @@ movl $0xFEE00300, %esi movl %eax, (%esi) - /* Zero out all fixed range and variable range MTRRs. */ - movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) >> 1), %edi - xorl %eax, %eax - xorl %edx, %edx -clear_mtrrs: - movw (%esi), %bx - movzx %bx, %ecx + post_code(0x21) + + /* Clear/disable fixed MTRRs */ + mov $fixed_mtrr_list_size, %ebx + xor %eax, %eax + xor %edx, %edx + +clear_fixed_mtrr: + add $-2, %ebx + movzwl fixed_mtrr_list(%ebx), %ecx wrmsr - add $2, %esi - dec %edi - jnz clear_mtrrs + jnz clear_fixed_mtrr + + /* Figure put how many MTRRs we have, and clear them out */ + mov $MTRR_CAP_MSR, %ecx + rdmsr + movzb %al, %ebx /* Number of variable MTRRs */ + mov $MTRR_PHYS_BASE(0), %ecx + xor %eax, %eax + xor %edx, %edx + +clear_var_mtrr: + wrmsr + inc %ecx + wrmsr + inc %ecx + dec %ebx + jnz clear_var_mtrr + post_code(0x21) post_code(0x22) /* Configure the default memory type to uncacheable. */ @@ -253,15 +270,16 @@ hlt jmp .Lhlt -mtrr_table: - /* Fixed MTRRs */ - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F - /* Variable MTRRs */ - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F -mtrr_table_end: +fixed_mtrr_list: + .word MTRR_FIX_64K_00000 + .word MTRR_FIX_16K_80000 + .word MTRR_FIX_16K_A0000 + .word MTRR_FIX_4K_C0000 + .word MTRR_FIX_4K_C8000 + .word MTRR_FIX_4K_D0000 + .word MTRR_FIX_4K_D8000 + .word MTRR_FIX_4K_E0000 + .word MTRR_FIX_4K_E8000 + .word MTRR_FIX_4K_F0000 + .word MTRR_FIX_4K_F8000 +fixed_mtrr_list_size = . - fixed_mtrr_list \ No newline at end of file -- To view, visit https://review.coreboot.org/26712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia4afdacc2d12db5ea49eb7ae2b4f4295981a6d8b Gerrit-Change-Number: 26712 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: security/tpm: Unify the coreboot TPM software stack
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24903 ) Change subject: security/tpm: Unify the coreboot TPM software stack ...................................................................... Patch Set 32: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73701/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27823/ : SUCCESS -- To view, visit https://review.coreboot.org/24903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Gerrit-Change-Number: 24903 Gerrit-PatchSet: 32 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 30 May 2018 21:15:39 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/crossgcc: update to gcc 8.1.0 and binutils 2.30
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25997 ) Change subject: util/crossgcc: update to gcc 8.1.0 and binutils 2.30 ...................................................................... Patch Set 15: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-toolchain/421/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/73697/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27818/ : SUCCESS -- To view, visit https://review.coreboot.org/25997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1e8074954d5d7a4eff590abb7439e9be7d3762aa Gerrit-Change-Number: 25997 Gerrit-PatchSet: 15 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Comment-Date: Wed, 30 May 2018 20:31:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/tpm: Unify the coreboot TPM software stack
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24903 ) Change subject: security/tpm: Unify the coreboot TPM software stack ...................................................................... Patch Set 31: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/73700/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/27822/ : SUCCESS -- To view, visit https://review.coreboot.org/24903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Gerrit-Change-Number: 24903 Gerrit-PatchSet: 31 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 30 May 2018 20:22:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: WIP: soc/amd/stoneyridge/southbridge.c: Fix saving _SWS parameters
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26547 ) Change subject: WIP: soc/amd/stoneyridge/southbridge.c: Fix saving _SWS parameters ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73699/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27820/ : SUCCESS -- To view, visit https://review.coreboot.org/26547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8bafc7bb7dd66e7f0eb8499e748535bbdcac5f53 Gerrit-Change-Number: 26547 Gerrit-PatchSet: 4 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 20:12:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: Swap PCI devfn resides in same PCI device
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26479 ) Change subject: soc/intel/skylake: Swap PCI devfn resides in same PCI device ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73698/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27819/ : SUCCESS -- To view, visit https://review.coreboot.org/26479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibbc5d6e979977011f5904c8bd4b2f1be16bd23dc Gerrit-Change-Number: 26479 Gerrit-PatchSet: 8 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 20:03:08 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/tpm: Unify the coreboot TPM software stack
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24903 ) Change subject: security/tpm: Unify the coreboot TPM software stack ...................................................................... Patch Set 30: Verified+1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/27821/ : SUCCESS -- To view, visit https://review.coreboot.org/24903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Gerrit-Change-Number: 24903 Gerrit-PatchSet: 30 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 30 May 2018 20:00:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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