coreboot-gerrit May 2018

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Change in coreboot[master]: cpu/intel/cache_as_ram_ht.inc: Compute the #var_mtrr during runtime
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26705 ) Change subject: cpu/intel/cache_as_ram_ht.inc: Compute the #var_mtrr during runtime ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73688/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27809/ : SUCCESS -- To view, visit https://review.coreboot.org/26705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I51bd5ba3072837d64b46cd64cf609efc160e80fb Gerrit-Change-Number: 26705 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 18:41:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: cpu/intel/car/cache_as_ram_ht.inc: Allow setting non eviction mode
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26706 ) Change subject: cpu/intel/car/cache_as_ram_ht.inc: Allow setting non eviction mode ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/73690/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/27811/ : SUCCESS -- To view, visit https://review.coreboot.org/26706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iefd484a95fff8d1cb78b4dcf5b31df7086e4431f Gerrit-Change-Number: 26706 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 18:35:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: arch/x86: Set the SIPI vector to a lower address
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26704 ) Change subject: arch/x86: Set the SIPI vector to a lower address ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73689/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27810/ : SUCCESS -- To view, visit https://review.coreboot.org/26704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I75a5e515bf5e7d0b8a496a882d20fe02cc30c253 Gerrit-Change-Number: 26704 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 18:35:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP]cpu/intel/model_206ax: Use cache_as_ram_ht.inc
by Arthur Heymans (Code Review) 30 May '18

30 May '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26708 Change subject: [WIP]cpu/intel/model_206ax: Use cache_as_ram_ht.inc ...................................................................... [WIP]cpu/intel/model_206ax: Use cache_as_ram_ht.inc Change-Id: I8f73271721072fb3ea4aaaf0b09141d83cf5ff5f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/cache_as_ram_ht.inc M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/Makefile.inc D src/cpu/intel/model_206ax/cache_as_ram.inc 4 files changed, 14 insertions(+), 320 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/26708/1 diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 7fc92fc..452f052 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -133,6 +133,10 @@ andl $LAPIC_ICR_BUSY, %ecx jnz 1b +#if IS_ENABLED(CONFIG_CPU_CAR_SKIP_HALT_AP) + jmp sipi_complete +#endif + post_code(0x24) movl $1, %eax diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index b30cfa1..6857b54 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -23,15 +23,12 @@ select TSC_SYNC_MFENCE select CPU_INTEL_COMMON select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select SIPI_VECTOR_IN_ROM config BOOTBLOCK_CPU_INIT string default "cpu/intel/model_206ax/bootblock.c" -config XIP_ROM_SIZE - hex - default 0x20000 if USE_NATIVE_RAMINIT - config SMM_TSEG_SIZE hex default 0x800000 @@ -45,4 +42,12 @@ hex default 0x400000 +config CPU_HAS_NO_EVICT_MODE + bool + default y + +config CPU_CAR_SKIP_HALT_AP + bool + default y + endif diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index 1e04554..3e290c1 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -17,5 +17,5 @@ cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin -cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc deleted file mode 100644 index d1678bf..0000000 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ /dev/null @@ -1,315 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/post_code.h> - -/* The full cache-as-ram size includes the cache-as-ram portion from coreboot - * and the space used by the reference code. These 2 values combined should - * be a power of 2 because the MTRR setup assumes that. */ -#define CACHE_AS_RAM_SIZE \ - (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE) -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - -/* Cache 4GB - MRC_SIZE_KB for MRC */ -#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) -#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) -#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) - -#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) - -#define NoEvictMod_MSR 0x2e0 - - /* Save the BIST result. */ - movl %eax, %ebp - -cache_as_ram: - post_code(0x20) - - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - /* All CPUs need to be in Wait for SIPI state */ -wait_for_sipi: - movl (%esi), %eax - bt $12, %eax - jc wait_for_sipi - - post_code(0x21) - /* Zero out all fixed range and variable range MTRRs. */ - movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) >> 1), %edi - xorl %eax, %eax - xorl %edx, %edx -clear_mtrrs: - movw (%esi), %bx - movzx %bx, %ecx - wrmsr - add $2, %esi - dec %edi - jnz clear_mtrrs - - post_code(0x22) - /* Configure the default memory type to uncacheable. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - andl $(~0x00000cff), %eax - wrmsr - - post_code(0x23) - /* Set Cache-as-RAM base address. */ - movl $(MTRR_PHYS_BASE(0)), %ecx - movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - - post_code(0x24) - /* Set Cache-as-RAM mask. */ - movl $(MTRR_PHYS_MASK(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - post_code(0x25) - - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - invd - movl %eax, %cr0 - - /* enable the 'no eviction' mode */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $1, %eax - andl $~2, %eax - wrmsr - - /* Clear the cache memory region. This will also fill up the cache. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE >> 2), %ecx - // movl $0x23322332, %eax - xorl %eax, %eax - rep stosl - - /* enable the 'no eviction run' state */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $3, %eax - wrmsr - - post_code(0x26) - /* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRR_PHYS_BASE(1), %ecx - xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html - */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRPROT, %eax - wrmsr - - movl $MTRR_PHYS_MASK(1), %ecx - movl $CPU_PHYSMASK_HI, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - post_code(0x27) - /* Enable caching for RAM init code to run faster */ - movl $MTRR_PHYS_BASE(2), %ecx - movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax - xorl %edx, %edx - wrmsr - movl $MTRR_PHYS_MASK(2), %ecx - movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - post_code(0x28) - /* Enable cache. */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - movl %eax, %cr0 - - /* Setup the stack. */ - movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax - movl %eax, %esp - - /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp - pushl %eax - -before_romstage: - post_code(0x29) - /* Call romstage.c main function. */ - call romstage_main - /* Save return value from romstage_main. It contains the stack to use - * after cache-as-ram is torn down. It also contains the information - * for setting up MTRRs. */ - movl %eax, %esp - - post_code(0x30) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x31) - - /* Disable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - andl $(~MTRR_DEF_TYPE_EN), %eax - wrmsr - - post_code(0x32) - - /* Disable the no eviction run state */ - movl $NoEvictMod_MSR, %ecx - rdmsr - andl $~2, %eax - wrmsr - - invd - - /* Disable the no eviction mode */ - rdmsr - andl $~1, %eax - wrmsr - - post_code(0x33) - - /* Enable cache. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x36) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x38) - - /* Clear all of the variable MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx - clr %eax - clr %edx - -1: - testl %ebx, %ebx - jz 1f - wrmsr /* Write MTRR base. */ - inc %ecx - wrmsr /* Write MTRR mask. */ - inc %ecx - dec %ebx - jmp 1b - -1: - /* Get number of MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx -2: - testl %ebx, %ebx - jz 2f - - /* Low 32 bits of MTRR base. */ - popl %eax - /* Upper 32 bits of MTRR base. */ - popl %edx - /* Write MTRR base. */ - wrmsr - inc %ecx - /* Low 32 bits of MTRR mask. */ - popl %eax - /* Upper 32 bits of MTRR mask. */ - popl %edx - /* Write MTRR mask. */ - wrmsr - inc %ecx - - dec %ebx - jmp 2b -2: - - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x3a) - - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr - - post_code(0x3b) - - /* Invalidate the cache again. */ - invd - - post_code(0x3c) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - call romstage_after_car - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt - -mtrr_table: - /* Fixed MTRRs */ - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F - /* Variable MTRRs */ - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F - .word 0x210, 0x211, 0x212, 0x213 -mtrr_table_end: -- To view, visit https://review.coreboot.org/26708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8f73271721072fb3ea4aaaf0b09141d83cf5ff5f Gerrit-Change-Number: 26708 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: cpu/intel/car/cache_as_ram_ht.inc: cache the whole ROM_SIZE
by Arthur Heymans (Code Review) 30 May '18

30 May '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26707 Change subject: cpu/intel/car/cache_as_ram_ht.inc: cache the whole ROM_SIZE ...................................................................... cpu/intel/car/cache_as_ram_ht.inc: cache the whole ROM_SIZE Change-Id: Ieeaee7b47fc9c31e9abae8c49e16f62bee7c76d5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/cache_as_ram_ht.inc 1 file changed, 2 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/26707/1 diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 58dbf29..7fc92fc 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -334,18 +334,13 @@ /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html - */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + movl $(-CACHE_ROM_SIZE), %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr post_code(0x2e) -- To view, visit https://review.coreboot.org/26707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ieeaee7b47fc9c31e9abae8c49e16f62bee7c76d5 Gerrit-Change-Number: 26707 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: cpu/intel/car/cache_as_ram_ht.inc: Allow setting non eviction mode
by Arthur Heymans (Code Review) 30 May '18

30 May '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26706 Change subject: cpu/intel/car/cache_as_ram_ht.inc: Allow setting non eviction mode ...................................................................... cpu/intel/car/cache_as_ram_ht.inc: Allow setting non eviction mode This is needed on CPU's from model_2065x on. Change-Id: Iefd484a95fff8d1cb78b4dcf5b31df7086e4431f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/cache_as_ram_ht.inc 1 file changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/26706/1 diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 0eb58d1..58dbf29 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -28,6 +28,8 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE +#define NoEvictMod_MSR 0x2e0 + /* Save the BIST result. */ movl %eax, %ebp @@ -299,6 +301,15 @@ invd movl %eax, %cr0 +#if IS_ENABLED(CONFIG_CPU_HAS_NO_EVICT_MODE) + /* enable the 'no eviction' mode */ + movl $NoEvictMod_MSR, %ecx + rdmsr + orl $1, %eax + andl $~2, %eax + wrmsr +#endif + /* Clear the cache memory region. This will also fill up the cache. */ cld xorl %eax, %eax @@ -306,6 +317,14 @@ movl $(CACHE_AS_RAM_SIZE >> 2), %ecx rep stosl +#if IS_ENABLED(CONFIG_CPU_HAS_NO_EVICT_MODE) + /* enable the 'no eviction run' state */ + movl $NoEvictMod_MSR, %ecx + rdmsr + orl $3, %eax + wrmsr +#endif + post_code(0x2d) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax @@ -370,8 +389,23 @@ post_code(0x32) +#if IS_ENABLED(CONFIG_CPU_HAS_NO_EVICT_MODE) + /* Disable the no eviction run state */ + movl $NoEvictMod_MSR, %ecx + rdmsr + andl $~2, %eax + wrmsr +#endif + invd +#if IS_ENABLED(CONFIG_CPU_HAS_NO_EVICT_MODE) + /* Disable the no eviction mode */ + rdmsr + andl $~1, %eax + wrmsr +#endif + post_code(0x33) /* Enable cache. */ -- To view, visit https://review.coreboot.org/26706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iefd484a95fff8d1cb78b4dcf5b31df7086e4431f Gerrit-Change-Number: 26706 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: cpu/intel/cache_as_ram_ht.inc: Compute the #var_mtrr during runtime
by Arthur Heymans (Code Review) 30 May '18

30 May '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26705 Change subject: cpu/intel/cache_as_ram_ht.inc: Compute the #var_mtrr during runtime ...................................................................... cpu/intel/cache_as_ram_ht.inc: Compute the #var_mtrr during runtime When clearing all MTRR, compute the amount of variable MTRR's during runtime instead of hardcoding it. Change-Id: I51bd5ba3072837d64b46cd64cf609efc160e80fb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/cache_as_ram_ht.inc 1 file changed, 38 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/26705/1 diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index e716caf..0eb58d1 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -39,21 +39,32 @@ andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax jz ap_init - /* Zero out all fixed range and variable range MTRRs. - * For hyper-threaded CPUs these are shared. - */ - movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) >> 1), %edi - xorl %eax, %eax - xorl %edx, %edx -clear_mtrrs: - movw (%esi), %bx - movzx %bx, %ecx - wrmsr - add $2, %esi - dec %edi - jnz clear_mtrrs + /* Clear/disable fixed MTRRs */ + mov $fixed_mtrr_list_size, %ebx + xor %eax, %eax + xor %edx, %edx +clear_fixed_mtrr: + add $-2, %ebx + movzwl fixed_mtrr_list(%ebx), %ecx + wrmsr + jnz clear_fixed_mtrr + + /* Figure put how many MTRRs we have, and clear them out */ + mov $MTRR_CAP_MSR, %ecx + rdmsr + movzb %al, %ebx /* Number of variable MTRRs */ + mov $MTRR_PHYS_BASE(0), %ecx + xor %eax, %eax + xor %edx, %edx + +clear_var_mtrr: + wrmsr + inc %ecx + wrmsr + inc %ecx + dec %ebx + jnz clear_var_mtrr post_code(0x21) /* Configure the default memory type to uncacheable. */ @@ -452,15 +463,16 @@ hlt jmp .Lhlt -mtrr_table: - /* Fixed MTRRs */ - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F - /* Variable MTRRs */ - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F -mtrr_table_end: +fixed_mtrr_list: + .word MTRR_FIX_64K_00000 + .word MTRR_FIX_16K_80000 + .word MTRR_FIX_16K_A0000 + .word MTRR_FIX_4K_C0000 + .word MTRR_FIX_4K_C8000 + .word MTRR_FIX_4K_D0000 + .word MTRR_FIX_4K_D8000 + .word MTRR_FIX_4K_E0000 + .word MTRR_FIX_4K_E8000 + .word MTRR_FIX_4K_F0000 + .word MTRR_FIX_4K_F8000 +fixed_mtrr_list_size = . - fixed_mtrr_list -- To view, visit https://review.coreboot.org/26705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I51bd5ba3072837d64b46cd64cf609efc160e80fb Gerrit-Change-Number: 26705 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: arch/x86: Set the SIPI vector to a lower address
by Arthur Heymans (Code Review) 30 May '18

30 May '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26704 Change subject: arch/x86: Set the SIPI vector to a lower address ...................................................................... arch/x86: Set the SIPI vector to a lower address This allows for ROMCC_bootblocks that are larger than 4KiB. Change-Id: I75a5e515bf5e7d0b8a496a882d20fe02cc30c253 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/failover.ld M src/cpu/Kconfig 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/26704/1 diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld index e9613d9..2f844ad 100644 --- a/src/arch/x86/failover.ld +++ b/src/arch/x86/failover.ld @@ -28,7 +28,7 @@ * boundary anyway, so no pad byte appears between _rom and _start. */ .bogus ROMLOC_MIN : { - . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4); + . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(8192) : ALIGN(4); ROMLOC = .; } >rom = 0xff @@ -51,7 +51,7 @@ * address gets applied. */ ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - - (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); + (CONFIG_SIPI_VECTOR_IN_ROM ? 8192 : 0); /* Post-check proper SIPI vector. */ _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || ((ap_sipi_vector & 0x0fff) == 0x0), diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index e10a702..affa18c 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -44,7 +44,7 @@ config AP_SIPI_VECTOR hex - default 0xfffff000 + default 0xffffe000 help This must equal address of ap_sipi_vector from bootblock build. -- To view, visit https://review.coreboot.org/26704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I75a5e515bf5e7d0b8a496a882d20fe02cc30c253 Gerrit-Change-Number: 26704 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: soc/amd/stoneyridge: Add ACPI device name lookup
by Martin Roth (Code Review) 30 May '18

30 May '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/26698 ) Change subject: soc/amd/stoneyridge: Add ACPI device name lookup ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/26698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5117e0d39db831364173c9c61ccdab6e34f18c59 Gerrit-Change-Number: 26698 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 18:03:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/crossgcc: update to gcc 8.1.0 and binutils 2.30
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25997 ) Change subject: util/crossgcc: update to gcc 8.1.0 and binutils 2.30 ...................................................................... Patch Set 14: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-toolchain/420/ : FAILURE https://qa.coreboot.org/job/coreboot-gerrit/73687/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27808/ : SUCCESS -- To view, visit https://review.coreboot.org/25997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1e8074954d5d7a4eff590abb7439e9be7d3762aa Gerrit-Change-Number: 25997 Gerrit-PatchSet: 14 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Comment-Date: Wed, 30 May 2018 17:44:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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