coreboot-gerrit May 2018

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Change in coreboot[master]: nb/intel/i945: Use postcar stage to tear down CAR
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26717 ) Change subject: nb/intel/i945: Use postcar stage to tear down CAR ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73723/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27845/ : SUCCESS -- To view, visit https://review.coreboot.org/26717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifa3a90b5ba3c873683ba3e5b8faa5025b64929de Gerrit-Change-Number: 26717 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 23:01:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: cpu/intel/model_206ax: Use postcar stage to tear down CAR
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26713 ) Change subject: cpu/intel/model_206ax: Use postcar stage to tear down CAR ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73721/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27843/ : SUCCESS -- To view, visit https://review.coreboot.org/26713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0f19bbddbf23cbf29a7846479c854980a5286547 Gerrit-Change-Number: 26713 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 22:57:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/pineview: Use postcar stage to tear down CAR
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26714 ) Change subject: nb/intel/pineview: Use postcar stage to tear down CAR ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73720/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27842/ : SUCCESS -- To view, visit https://review.coreboot.org/26714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5ce488d92cffabad1c73b60e23ded090b07b0a9d Gerrit-Change-Number: 26714 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 22:55:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: cpu/intel/cache_as_ram: Compute number var MTRR's
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26712 ) Change subject: cpu/intel/cache_as_ram: Compute number var MTRR's ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73719/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27841/ : SUCCESS -- To view, visit https://review.coreboot.org/26712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia4afdacc2d12db5ea49eb7ae2b4f4295981a6d8b Gerrit-Change-Number: 26712 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 22:52:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/i945: Use postcar stage to tear down CAR
by Arthur Heymans (Code Review) 31 May '18

31 May '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26717 Change subject: nb/intel/i945: Use postcar stage to tear down CAR ...................................................................... nb/intel/i945: Use postcar stage to tear down CAR Also remove unused code in model_6e/cache_as_ram.inc Change-Id: Ifa3a90b5ba3c873683ba3e5b8faa5025b64929de Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_6ex/cache_as_ram.inc M src/cpu/intel/socket_441/Makefile.inc M src/cpu/intel/socket_LGA775/Makefile.inc M src/cpu/intel/socket_mFCPGA478/Makefile.inc M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/i945/Makefile.inc M src/northbridge/intel/i945/ram_calc.c 7 files changed, 12 insertions(+), 117 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/26717/1 diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index e4ff0fc..b2d7628 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -155,115 +155,6 @@ post_code(0x29) /* Call romstage.c main function. */ call romstage_main - /* Save return value from romstage_main. It contains the stack to use - * after cache-as-ram is torn down. It also contains the information - * for setting up MTRRs. */ - movl %eax, %esp - - post_code(0x30) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x31) - - /* Disable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - andl $(~MTRR_DEF_TYPE_EN), %eax - wrmsr - - post_code(0x32) - - invd - - post_code(0x33) - - /* Enable cache. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x36) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x38) - - /* Clear all of the variable MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx - clr %eax - clr %edx - -1: - testl %ebx, %ebx - jz 1f - wrmsr /* Write MTRR base. */ - inc %ecx - wrmsr /* Write MTRR mask. */ - inc %ecx - dec %ebx - jmp 1b - -1: - /* Get number of MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx -2: - testl %ebx, %ebx - jz 2f - - /* Low 32 bits of MTRR base. */ - popl %eax - /* Upper 32 bits of MTRR base. */ - popl %edx - /* Write MTRR base. */ - wrmsr - inc %ecx - /* Low 32 bits of MTRR mask. */ - popl %eax - /* Upper 32 bits of MTRR mask. */ - popl %edx - /* Write MTRR mask. */ - wrmsr - inc %ecx - - dec %ebx - jmp 2b -2: - - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x3a) - - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr - - post_code(0x3b) - - /* Invalidate the cache again. */ - invd - - post_code(0x3c) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - call romstage_after_car .Lhlt: post_code(POST_DEAD_CODE) diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc index dbf300b..63d373e 100644 --- a/src/cpu/intel/socket_441/Makefile.inc +++ b/src/cpu/intel/socket_441/Makefile.inc @@ -9,4 +9,5 @@ subdirs-y += ../speedstep cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc +postcar-y += ../car/teardown_car.S romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index 78a2f32..e81ecc4 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -14,5 +14,5 @@ subdirs-y += ../speedstep cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc -postcar-$(CONFIG_POSTCAR_STAGE) += ../car/teardown_car.S +postcar-y += ../car/teardown_car.S romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/socket_mFCPGA478/Makefile.inc b/src/cpu/intel/socket_mFCPGA478/Makefile.inc index 6056d3c..14f96a9 100644 --- a/src/cpu/intel/socket_mFCPGA478/Makefile.inc +++ b/src/cpu/intel/socket_mFCPGA478/Makefile.inc @@ -12,4 +12,5 @@ subdirs-y += ../speedstep cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc +postcar-y += ../car/teardown_car.S romstage-y += ../car/romstage.c diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 482f98a..e04d0c3 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -28,6 +28,8 @@ select RELOCATABLE_RAMSTAGE select INTEL_EDID select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT + select POSTCAR_STAGE + select POSTCAR_CONSOLE config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 0e4fcfc..ffeabdc 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -29,4 +29,6 @@ smm-y += udelay.c +postcar-y += ram_calc.c + endif diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index 990df97..6b04f50 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -78,8 +78,6 @@ return ggc2uma[gms] << 10; } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* setup_stack_and_mtrrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ void *setup_stack_and_mtrrs(void) @@ -87,7 +85,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ @@ -106,8 +104,8 @@ postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. - */ - return postcar_commit_mtrrs(&pcf); + run_postcar_phase(&pcf); + + /* We don't return here */ + return NULL; } -- To view, visit https://review.coreboot.org/26717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifa3a90b5ba3c873683ba3e5b8faa5025b64929de Gerrit-Change-Number: 26717 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/x4x: Use postcar stage to tear down CAR
by Arthur Heymans (Code Review) 31 May '18

31 May '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26716 Change subject: nb/intel/x4x: Use postcar stage to tear down CAR ...................................................................... nb/intel/x4x: Use postcar stage to tear down CAR Change-Id: I4c5c5648fd6e54e61f2bd532624331cdd0d52ece Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/cache_as_ram_ht.inc M src/cpu/intel/socket_LGA775/Makefile.inc M src/northbridge/intel/x4x/Kconfig M src/northbridge/intel/x4x/Makefile.inc M src/northbridge/intel/x4x/ram_calc.c 5 files changed, 14 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/26716/1 diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 0eb58d1..5f2a91a 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -348,6 +348,10 @@ post_code(0x2f) /* Call romstage.c main function. */ call romstage_main +#if IS_ENABLED(CONFIG_POSTCAR_STAGE) + /* Should never be reached */ + jmp .Lhlt +#endif /* Save return value from romstage_main. It contains the stack to use * after cache-as-ram is torn down. It also contains the information * for setting up MTRRs. */ diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index ffcd1cb..78a2f32 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -14,5 +14,5 @@ subdirs-y += ../speedstep cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc -romstage-y += ../car/romstage.c +postcar-$(CONFIG_POSTCAR_STAGE) += ../car/teardown_car.S romstage-y += ../car/romstage.c diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index d9dbdc9..610f785 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -29,6 +29,8 @@ select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select CACHE_MRC_SETTINGS + select POSTCAR_STAGE + select POSTCAR_CONSOLE config CBFS_SIZE hex diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index 1f7e483..3118b09 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -29,4 +29,6 @@ ramstage-y += gma.c ramstage-y += northbridge.c +postcar-y += ram_calc.c + endif diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 1009372..b5efabe 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -103,8 +103,6 @@ return (void *) top_of_ram; } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* setup_stack_and_mtrrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ void *setup_stack_and_mtrrs(void) @@ -112,7 +110,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ @@ -131,8 +129,8 @@ postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. - */ - return postcar_commit_mtrrs(&pcf); + run_postcar_phase(&pcf); + + /* We don't return here */ + return NULL; } -- To view, visit https://review.coreboot.org/26716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4c5c5648fd6e54e61f2bd532624331cdd0d52ece Gerrit-Change-Number: 26716 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/gm45: Use postcar stage to tear down CAR
by Arthur Heymans (Code Review) 31 May '18

31 May '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26715 Change subject: nb/intel/gm45: Use postcar stage to tear down CAR ...................................................................... nb/intel/gm45: Use postcar stage to tear down CAR Change-Id: I5261f73a2d4890a0f005958ddee2716179bbf9b5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/socket_BGA956/Makefile.inc M src/cpu/intel/socket_mPGA478MN/Makefile.inc M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/Makefile.inc M src/northbridge/intel/gm45/ram_calc.c 5 files changed, 11 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/26715/1 diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc index 22c1a7c..bc2019e 100644 --- a/src/cpu/intel/socket_BGA956/Makefile.inc +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -10,4 +10,5 @@ # Use Intel Core (not Core 2) code for CAR init, any CPU might be used. cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc +postcar-y += ../car/teardown_car.S romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/socket_mPGA478MN/Makefile.inc b/src/cpu/intel/socket_mPGA478MN/Makefile.inc index 407861e..ee60187 100644 --- a/src/cpu/intel/socket_mPGA478MN/Makefile.inc +++ b/src/cpu/intel/socket_mPGA478MN/Makefile.inc @@ -11,4 +11,5 @@ # Use Intel Core (not Core 2) code for CAR init, any CPU might be used. cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc +postcar-y += ../car/teardown_car.S romstage-y += ../car/romstage.c diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 85902d3..193ec70 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -29,6 +29,8 @@ select RELOCATABLE_RAMSTAGE select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT + select POSTCAR_STAGE + select POSTCAR_CONSOLE config CBFS_SIZE hex diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index fdf0012..c12bbf1 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -36,4 +36,6 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/lapic/apic_timer.c +postcar-y += ram_calc.c + endif diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 1e434c7..6ddb290 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -116,8 +116,6 @@ return (void *) top_of_ram; } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* setup_stack_and_mtrrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ void *setup_stack_and_mtrrs(void) @@ -125,7 +123,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ @@ -144,8 +142,8 @@ postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. - */ - return postcar_commit_mtrrs(&pcf); + run_postcar_phase(&pcf); + + /* We don't return here */ + return NULL; } -- To view, visit https://review.coreboot.org/26715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5261f73a2d4890a0f005958ddee2716179bbf9b5 Gerrit-Change-Number: 26715 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/pineview: Use postcar stage to tear down CAR
by Arthur Heymans (Code Review) 31 May '18

31 May '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26714 Change subject: nb/intel/pineview: Use postcar stage to tear down CAR ...................................................................... nb/intel/pineview: Use postcar stage to tear down CAR Change-Id: I5ce488d92cffabad1c73b60e23ded090b07b0a9d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/cpu/intel/car/teardown_car.S M src/cpu/intel/socket_FCBGA559/Makefile.inc M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/Makefile.inc M src/northbridge/intel/pineview/ram_calc.c 5 files changed, 53 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/26714/1 diff --git a/src/cpu/intel/car/teardown_car.S b/src/cpu/intel/car/teardown_car.S new file mode 100644 index 0000000..024fc6b --- /dev/null +++ b/src/cpu/intel/car/teardown_car.S @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> + +.global chipset_teardown_car +chipset_teardown_car: + pop %esp + + post_code(0x30) + + /* Disable cache. */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + post_code(0x31) + + /* Disable MTRR. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + andl $(~MTRR_DEF_TYPE_EN), %eax + wrmsr + + post_code(0x32) + + /* Return to caller. */ + jmp *%esp diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index dbf300b..6f5ef5c 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -9,4 +9,5 @@ subdirs-y += ../speedstep cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc +postcar-$(CONFIG_POSTCAR_STAGE) += ../car/teardown_car.S romstage-y += ../car/romstage.c diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index e8ef9d9..80f566a 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -29,6 +29,8 @@ select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT select RELOCATABLE_RAMSTAGE select INTEL_GMA_ACPI + select POSTCAR_STAGE + select POSTCAR_CONSOLE config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index a4c08c8..d7936c1 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -25,4 +25,6 @@ romstage-y += raminit.c romstage-y += early_init.c +postcar-y += ram_calc.c + endif diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index 63f3942..d2fa66e 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -105,8 +105,6 @@ return (void *) top_of_ram; } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* setup_stack_and_mtrrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ void *setup_stack_and_mtrrs(void) @@ -114,7 +112,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ @@ -133,8 +131,8 @@ postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. - */ - return postcar_commit_mtrrs(&pcf); + run_postcar_phase(&pcf); + + /* We don't return here */ + return NULL; } -- To view, visit https://review.coreboot.org/26714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5ce488d92cffabad1c73b60e23ded090b07b0a9d Gerrit-Change-Number: 26714 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: cpu/intel/cache_as_ram: Compute number var MTRR's
by Arthur Heymans (Code Review) 31 May '18

31 May '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/26712 to look at the new patch set (#2). Change subject: cpu/intel/cache_as_ram: Compute number var MTRR's ...................................................................... cpu/intel/cache_as_ram: Compute number var MTRR's Compute the number of variable MTRR's during runtime. Change-Id: Ia4afdacc2d12db5ea49eb7ae2b4f4295981a6d8b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/cache_as_ram_ht.inc M src/cpu/intel/haswell/cache_as_ram.inc M src/cpu/intel/model_206ax/cache_as_ram.inc M src/cpu/intel/model_6ex/cache_as_ram.inc 4 files changed, 156 insertions(+), 97 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/26712/2 -- To view, visit https://review.coreboot.org/26712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia4afdacc2d12db5ea49eb7ae2b4f4295981a6d8b Gerrit-Change-Number: 26712 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: cpu/intel/model_206ax: Use postcar stage to tear down CAR
by Arthur Heymans (Code Review) 31 May '18

31 May '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/26713 to look at the new patch set (#2). Change subject: cpu/intel/model_206ax: Use postcar stage to tear down CAR ...................................................................... cpu/intel/model_206ax: Use postcar stage to tear down CAR Tested on Lenovo Thinkpad X220. Postcar get's loaded by romstage which in turn loads the ramstage. On S3 both get loaded from the external stage cache. Change-Id: I0f19bbddbf23cbf29a7846479c854980a5286547 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_206ax/cache_as_ram.inc A src/cpu/intel/model_206ax/teardown_car.S M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/ram_calc.c 6 files changed, 65 insertions(+), 127 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/26713/2 -- To view, visit https://review.coreboot.org/26713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0f19bbddbf23cbf29a7846479c854980a5286547 Gerrit-Change-Number: 26713 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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