coreboot-gerrit May 2018

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Change in coreboot[master]: google/kukui: Add new board
by Tristan Hsieh (Code Review) 31 May '18

31 May '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/26722 Change subject: google/kukui: Add new board ...................................................................... google/kukui: Add new board BUG=none BRANCH=none TEST=timer and uart work fine Change-Id: I08644892d34925574f791b000b0035d5afad7022 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- A src/mainboard/google/kukui/Kconfig A src/mainboard/google/kukui/Kconfig.name A src/mainboard/google/kukui/Makefile.inc A src/mainboard/google/kukui/board_info.txt A src/mainboard/google/kukui/chromeos.c A src/mainboard/google/kukui/chromeos.fmd A src/mainboard/google/kukui/devicetree.cb A src/mainboard/google/kukui/memlayout.ld A src/mainboard/google/kukui/romstage.c 9 files changed, 165 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/26722/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig new file mode 100644 index 0000000..91e7aa9 --- /dev/null +++ b/src/mainboard/google/kukui/Kconfig @@ -0,0 +1,22 @@ +if BOARD_GOOGLE_KUKUI + +config BOARD_SPECIFIC_OPTIONS #dummy + def_bool y + select SOC_MEDIATEK_MT8183 + select BOARD_ROMSIZE_KB_4096 + select MAINBOARD_HAS_CHROMEOS + select CHROMEOS + select COMMON_CBFS_SPI_WRAPPER + select SPI_FLASH + select FATAL_ASSERTS + select VBOOT_MOCK_SECDATA + +config MAINBOARD_DIR + string + default google/kukui + +config MAINBOARD_PART_NUMBER + string + default "KUKUI" + +endif diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name new file mode 100644 index 0000000..c568891 --- /dev/null +++ b/src/mainboard/google/kukui/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_KUKUI + bool "KUKUI" diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc new file mode 100644 index 0000000..44a60b5 --- /dev/null +++ b/src/mainboard/google/kukui/Makefile.inc @@ -0,0 +1,11 @@ +bootblock-y += memlayout.ld + +verstage-y += chromeos.c +verstage-y += memlayout.ld + +romstage-y += chromeos.c +romstage-y += memlayout.ld +romstage-y += romstage.c + +ramstage-y += chromeos.c +ramstage-y += memlayout.ld diff --git a/src/mainboard/google/kukui/board_info.txt b/src/mainboard/google/kukui/board_info.txt new file mode 100644 index 0000000..c3688c1 --- /dev/null +++ b/src/mainboard/google/kukui/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Kukui MediaTek MT8183 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c new file mode 100644 index 0000000..7f9946a --- /dev/null +++ b/src/mainboard/google/kukui/chromeos.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootmode.h> +#include <boot/coreboot_tables.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +int get_write_protect_state(void) +{ + return 0; +} diff --git a/src/mainboard/google/kukui/chromeos.fmd b/src/mainboard/google/kukui/chromeos.fmd new file mode 100644 index 0000000..9c618e3 --- /dev/null +++ b/src/mainboard/google/kukui/chromeos.fmd @@ -0,0 +1,29 @@ +FLASH@0x0 0x400000 { + WP_RO@0x0 0x200000 { + RO_SECTION@0x0 0x1f0000 { + BOOTBLOCK@0 128K + COREBOOT(CBFS)@0x20000 0xe0000 + FMAP@0x100000 0x1000 + GBB@0x101000 0xeef00 + RO_FRID@0x1eff00 0x100 + } + RO_VPD@0x1f0000 0x10000 + } + RW_SECTION_A@0x200000 0x78000 { + VBLOCK_A@0x0 0x2000 + FW_MAIN_A(CBFS)@0x2000 0x75f00 + RW_FWID_A@0x77f00 0x100 + } + RW_SHARED@0x278000 0x2000 { + SHARED_DATA@0x0 0x2000 + } + RW_NVRAM@0x27a000 0x2000 + RW_ELOG@0x27c000 0x4000 + RW_SECTION_B@0x280000 0x78000 { + VBLOCK_B@0x0 0x2000 + FW_MAIN_B(CBFS)@0x2000 0x75f00 + RW_FWID_B@0x77f00 0x100 + } + RW_VPD@0x2f8000 0x8000 + RW_LEGACY(CBFS)@0x300000 0x100000 +} diff --git a/src/mainboard/google/kukui/devicetree.cb b/src/mainboard/google/kukui/devicetree.cb new file mode 100644 index 0000000..e2f2be3 --- /dev/null +++ b/src/mainboard/google/kukui/devicetree.cb @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2018 MediaTek Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/mediatek/mt8183 + device cpu_cluster 0 on + device cpu 0 on end + end +end diff --git a/src/mainboard/google/kukui/memlayout.ld b/src/mainboard/google/kukui/memlayout.ld new file mode 100644 index 0000000..2c33306 --- /dev/null +++ b/src/mainboard/google/kukui/memlayout.ld @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/memlayout.ld> diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c new file mode 100644 index 0000000..76a587d --- /dev/null +++ b/src/mainboard/google/kukui/romstage.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/exception.h> +#include <console/console.h> +#include <program_loading.h> +#include <timestamp.h> + +void main(void) +{ + timestamp_add_now(TS_START_ROMSTAGE); + + /* init uart baudrate when pll on */ + console_init(); + exception_init(); + + run_ramstage(); +} -- To view, visit https://review.coreboot.org/26722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I08644892d34925574f791b000b0035d5afad7022 Gerrit-Change-Number: 26722 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Add ACPI device name lookup
by Kevin Chiu (Code Review) 31 May '18

31 May '18

Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/26698 ) Change subject: soc/amd/stoneyridge: Add ACPI device name lookup ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/26698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5117e0d39db831364173c9c61ccdab6e34f18c59 Gerrit-Change-Number: 26698 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 00:41:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee: Remove #include <soc/smi.h> from GPIO code and header
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26721 ) Change subject: mb/google/kahlee: Remove #include <soc/smi.h> from GPIO code and header ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73732/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27852/ : SUCCESS -- To view, visit https://review.coreboot.org/26721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I64cf0796103a5226ddace03d05d94160bf93aa69 Gerrit-Change-Number: 26721 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 00:33:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee: Remove #include <soc/smi.h> from GPIO code and header
by Richard Spiegel (Code Review) 31 May '18

31 May '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/26721 Change subject: mb/google/kahlee: Remove #include <soc/smi.h> from GPIO code and header ...................................................................... mb/google/kahlee: Remove #include <soc/smi.h> from GPIO code and header Because of struct sci_source table of events that have to generate SCI or SMI, #include <soc/smi.h> was added to kahlee/grunt gpio.c files. It was also added to variants.h. However, new code transfered most of SCI/SMI/interrupt programming (with exception of events not associated to a GPIO pin). Because of this, soc/amd/stoneyridge/include/soc/gpio.h now have the header inclusion "#include <soc/smi.h>", and files within motherboard related to GPIO don't need it anymore. For some unknown reason, mainboard.c also has the smi.h include and don't need it. Only smihandler.c truly needs it. Remove the includes. BUG=b:78139413 TEST=build and boot grunt. Change-Id: I64cf0796103a5226ddace03d05d94160bf93aa69 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/kahlee/variants/kahlee/gpio.c 4 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/26721/1 diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index e090401..6f7882f 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -26,7 +26,6 @@ #include <smbios.h> #include <soc/nvs.h> #include <soc/pci_devs.h> -#include <soc/smi.h> #include <soc/southbridge.h> #include <variant/ec.h> #include <variant/thermal.h> diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index c7bd6a5..4a7cfae 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -16,7 +16,6 @@ #include <compiler.h> #include <baseboard/variants.h> #include <soc/gpio.h> -#include <soc/smi.h> #include <soc/southbridge.h> #include <stdlib.h> #include <boardid.h> diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index fc754b5..23f9cb0 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -18,7 +18,6 @@ #define __BASEBOARD_VARIANTS_H__ #include <stddef.h> -#include <soc/smi.h> #include <soc/southbridge.h> const struct sci_source *get_gpe_table(size_t *num); diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c index 3072350..75354de 100644 --- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c +++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c @@ -14,7 +14,6 @@ */ #include <baseboard/variants.h> -#include <soc/smi.h> #include <soc/southbridge.h> #include <stdlib.h> #include <variant/gpio.h> -- To view, visit https://review.coreboot.org/26721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I64cf0796103a5226ddace03d05d94160bf93aa69 Gerrit-Change-Number: 26721 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: util/sconfig: Re-factor sconfig to not assume chip as device
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26720 ) Change subject: util/sconfig: Re-factor sconfig to not assume chip as device ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73731/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27851/ : SUCCESS -- To view, visit https://review.coreboot.org/26720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I255092f527c8eecb144385eb681df20e54caf8f5 Gerrit-Change-Number: 26720 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 00:19:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/sconfig: Re-factor sconfig to not assume chip as device
by Furquan Shaikh (Code Review) 31 May '18

31 May '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/26720 to look at the new patch set (#3). Change subject: util/sconfig: Re-factor sconfig to not assume chip as device ...................................................................... util/sconfig: Re-factor sconfig to not assume chip as device This change adds a new structure "struct chip" to identify elements of type chip rather than re-using the structure for device. Until now chip was treated as a device while generating the parse tree and then device tree postprocessing skipped over all the chip entries in children and sibling pointers of device nodes. With this change, the device tree will only contain struct device in the parsed tree. It helps by avoiding unnecessary pointers to chip structure as children or next_sibling and then skipping those elements in post processing. Every device can then hold a pointer to its chip. When generating static.c, chip structure is emitted before device structure to ensure that the device structure has chip within its scope. Externally, the only visible change in static.c should be the order in which chip/device elements are emitted i.e. previously all chips under a particular device were emitted to static.c and then the devices using those chips. Now, a chip is emitted just before device that is using it. BUG=b:80081934 TEST=Verified that abuild is successful for all boards. Also, verified that static.c generated for eve, kahlee, scarlet, asrock imb_a180 is unchanged from before in node definitions. Change-Id: I255092f527c8eecb144385eb681df20e54caf8f5 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M util/sconfig/main.c M util/sconfig/sconfig.h M util/sconfig/sconfig.tab.c_shipped M util/sconfig/sconfig.tab.h_shipped M util/sconfig/sconfig.y 5 files changed, 183 insertions(+), 111 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/26720/3 -- To view, visit https://review.coreboot.org/26720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I255092f527c8eecb144385eb681df20e54caf8f5 Gerrit-Change-Number: 26720 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: util/sconfig: Re-factor sconfig to not assume chip as device
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26720 ) Change subject: util/sconfig: Re-factor sconfig to not assume chip as device ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73730/ : SUCCESS -- To view, visit https://review.coreboot.org/26720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I255092f527c8eecb144385eb681df20e54caf8f5 Gerrit-Change-Number: 26720 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 23:41:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/sconfig: Re-factor sconfig to not assume chip as device
by Furquan Shaikh (Code Review) 31 May '18

31 May '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/26720 ) Change subject: util/sconfig: Re-factor sconfig to not assume chip as device ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/26720/2/util/sconfig/sconfig.tab.c_shipped File util/sconfig/sconfig.tab.c_shipped: https://review.coreboot.org/#/c/26720/2/util/sconfig/sconfig.tab.c_shipped@… PS2, Line 112: USR_LOCAL_GOOGLE_HOME_FURQUAN_COREBOOT_ This needs to be fixed. https://review.coreboot.org/#/c/26720/2/util/sconfig/sconfig.tab.h_shipped File util/sconfig/sconfig.tab.h_shipped: https://review.coreboot.org/#/c/26720/2/util/sconfig/sconfig.tab.h_shipped@… PS2, Line 33: YY_YY_USR_LOCAL_GOOGLE_HOME_FURQUAN_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED this too. -- To view, visit https://review.coreboot.org/26720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I255092f527c8eecb144385eb681df20e54caf8f5 Gerrit-Change-Number: 26720 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 23:38:50 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: util/sconfig: Re-factor sconfig to not assume chip as device
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26720 ) Change subject: util/sconfig: Re-factor sconfig to not assume chip as device ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/73729/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/27850/ : SUCCESS -- To view, visit https://review.coreboot.org/26720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I255092f527c8eecb144385eb681df20e54caf8f5 Gerrit-Change-Number: 26720 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 23:37:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/sconfig: Re-factor sconfig to not assume chip as device
by Furquan Shaikh (Code Review) 31 May '18

31 May '18

Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/26720 ) Change subject: util/sconfig: Re-factor sconfig to not assume chip as device ...................................................................... util/sconfig: Re-factor sconfig to not assume chip as device This change adds a new structure "struct chip" to identify elements of type chip rather than re-using the structure for device. It helps clean up the devicetree by avoiding unnecessary pointers to chip structure as children or next_sibling and then skipping those elements in post processing. With this change, the devicetree will only contain struct device in the tree. Every device can then hold a pointer to its chip. When generating static.c, chip structure is emitted before device structure to ensure that the device structure has chip within its scope. Externally, the only visible change in static.c should be the order in which chip elements are emitted i.e. previously all chips under a particular device were emitted to static.c and then the devices using those chips. Now, a chip is emitted just before device that is using it. This clean up is part of a bigger change required to support overriding of devicetree by variants. BUG=b:80081934 TEST=Verified that abuild is successful for all boards. Also, verified that static.c generated for eve, kahlee, scarlet is unchanged from before. Change-Id: I255092f527c8eecb144385eb681df20e54caf8f5 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M util/sconfig/main.c M util/sconfig/sconfig.h M util/sconfig/sconfig.tab.c_shipped M util/sconfig/sconfig.tab.h_shipped M util/sconfig/sconfig.y 5 files changed, 189 insertions(+), 117 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/26720/2 -- To view, visit https://review.coreboot.org/26720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I255092f527c8eecb144385eb681df20e54caf8f5 Gerrit-Change-Number: 26720 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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coreboot-gerrit May 2018