coreboot-gerrit April 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: util/crossgcc: Build Linux toolchain
by build bot (Jenkins) (Code Review) 27 Apr '18

27 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25151 ) Change subject: util/crossgcc: Build Linux toolchain ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/25100/ : SUCCESS -- To view, visit https://review.coreboot.org/25151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3bb0c39077859551568f2945f6475f9b241f7ccc Gerrit-Change-Number: 25151 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 27 Apr 2018 17:11:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: arch/x86: Relocating GDT in romstage
by build bot (Jenkins) (Code Review) 27 Apr '18

27 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25895 ) Change subject: arch/x86: Relocating GDT in romstage ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/70918/ : UNSTABLE -- To view, visit https://review.coreboot.org/25895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I01ded6e9b358b23e04d92bef5263bfe8c2a5ec5a Gerrit-Change-Number: 25895 Gerrit-PatchSet: 1 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Apr 2018 15:48:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: arch/x86: Relocating GDT in romstage
by build bot (Jenkins) (Code Review) 27 Apr '18

27 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25895 ) Change subject: arch/x86: Relocating GDT in romstage ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/25098/ : SUCCESS -- To view, visit https://review.coreboot.org/25895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I01ded6e9b358b23e04d92bef5263bfe8c2a5ec5a Gerrit-Change-Number: 25895 Gerrit-PatchSet: 1 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Apr 2018 15:36:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: arch/x86: Relocating GDT in romstage
by Hannah Williams (Code Review) 27 Apr '18

27 Apr '18

Hannah Williams has uploaded this change for review. ( https://review.coreboot.org/25895 Change subject: arch/x86: Relocating GDT in romstage ...................................................................... arch/x86: Relocating GDT in romstage While in Cache as RAM, move the GDT from Flash to CAR Change-Id: I01ded6e9b358b23e04d92bef5263bfe8c2a5ec5a Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- M src/arch/x86/Makefile.inc M src/arch/x86/assembly_entry.S A src/arch/x86/gdt_init.S 3 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/25895/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 07bef93..f45295c 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -206,6 +206,7 @@ romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c romstage-y += boot.c +romstage-y += gdt_init.S romstage-y += cbmem.c romstage-y += cbfs_and_run.c romstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += cpu_common.c diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index e5e7d48..5a8a57e 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -64,6 +64,9 @@ #endif andl $0xfffffff0, %esp +#if ENV_ROMSTAGE + call _gdt_init +#endif #if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE) call exception_init #endif diff --git a/src/arch/x86/gdt_init.S b/src/arch/x86/gdt_init.S new file mode 100644 index 0000000..bfc5e45 --- /dev/null +++ b/src/arch/x86/gdt_init.S @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + .code32 + .globl _gdt_init +_gdt_init: + cli + lgdt %cs:gdtptr + ret + + .text + .align 4 +.globl gdtptr +gdt: +gdtptr: + .word gdt_end - gdt -1 /* compute the table limit */ + .long gdt /* we know the offset */ + .word 0 + + /* selgdt 0x08, flat code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes + for limit */ + + /* selgdt 0x10,flat data segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x93, 0xcf, 0x00 + + /* selgdt 0x18, flat code segment (64-bit) */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xaf, 0x00 + +gdt_end: + +.code32 -- To view, visit https://review.coreboot.org/25895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I01ded6e9b358b23e04d92bef5263bfe8c2a5ec5a Gerrit-Change-Number: 25895 Gerrit-PatchSet: 1 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com>

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Change in coreboot[master]: cros-ec: Avoid infinitely looping in google_chromeec_pd_get_amode
by build bot (Jenkins) (Code Review) 27 Apr '18

27 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25878 ) Change subject: cros-ec: Avoid infinitely looping in google_chromeec_pd_get_amode ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70917/ : SUCCESS -- To view, visit https://review.coreboot.org/25878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I388ed4bdfac9176d8e690c429e99674ed267004f Gerrit-Change-Number: 25878 Gerrit-PatchSet: 4 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Fri, 27 Apr 2018 15:20:07 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: cros-ec: Avoid infinitely looping in google_chromeec_pd_get_amode
by build bot (Jenkins) (Code Review) 27 Apr '18

27 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25878 ) Change subject: cros-ec: Avoid infinitely looping in google_chromeec_pd_get_amode ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/25097/ : SUCCESS -- To view, visit https://review.coreboot.org/25878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I388ed4bdfac9176d8e690c429e99674ed267004f Gerrit-Change-Number: 25878 Gerrit-PatchSet: 4 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Fri, 27 Apr 2018 15:10:07 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Use common pmc utility instead of soc
by Maulik V Vaghela (Code Review) 27 Apr '18

27 Apr '18

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/25894 Change subject: soc/intel/cannonlake: Use common pmc utility instead of soc ...................................................................... soc/intel/cannonlake: Use common pmc utility instead of soc Switch to common pmc utility functionality which is now common across multiple socs instead of using it from cannonlake soc. Removed pmutil.c file from cannonlake as we no longer need it and we'll use it from common. Also implemented soc dependent function in chip_config.c file which is required by common pmc block. BUG=none BRANCH=none TEST=code compiles with different configurations. Change-Id: I0eb3c4c75d25554a8829da71e32438c3458ccbfb Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/chip_config.c D src/soc/intel/cannonlake/pmutil.c 4 files changed, 20 insertions(+), 239 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/25894/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index c9b3bd3..a962ba4 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -61,7 +61,7 @@ select SOC_INTEL_COMMON_BLOCK_LPSS select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PCR - select SOC_INTEL_COMMON_BLOCK_PMC + select SOC_INTEL_COMMON_BLOCK_PMC_V2 select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SATA diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 1e463c2..94c4548 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -11,7 +11,6 @@ bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c -bootblock-y += pmutil.c bootblock-y += bootblock/report_platform.c bootblock-y += chip_config.c bootblock-y += gpio.c @@ -25,7 +24,6 @@ romstage-y += gpio.c romstage-y += lpc.c romstage-y += memmap.c -romstage-y += pmutil.c romstage-y += reset.c romstage-y += spi.c romstage-$(CONFIG_UART_DEBUG) += uart.c @@ -41,7 +39,6 @@ ramstage-y += memmap.c ramstage-y += nhlt.c ramstage-y += pmc.c -ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-y += smmrelocate.c ramstage-y += spi.c @@ -52,16 +49,13 @@ ramstage-y += chip_config.c smm-y += gpio.c -smm-y += pmutil.c smm-y += smihandler.c smm-$(CONFIG_UART_DEBUG) += uart.c postcar-y += memmap.c -postcar-y += pmutil.c postcar-$(CONFIG_UART_DEBUG) += uart.c verstage-y += chip_config.c -verstage-y += pmutil.c verstage-y += spi.c verstage-$(CONFIG_UART_DEBUG) += uart.c diff --git a/src/soc/intel/cannonlake/chip_config.c b/src/soc/intel/cannonlake/chip_config.c index f3d710c..123f8c2 100644 --- a/src/soc/intel/cannonlake/chip_config.c +++ b/src/soc/intel/cannonlake/chip_config.c @@ -18,6 +18,7 @@ #include <drivers/i2c/designware/dw_i2c.h> #include <intelbasecode/lockdown.h> #include <intelblocks/gspi.h> +#include <intelblocks/pmclib.h> /* * This function will return SOC specific lockdown configuration. * Function can return 3 possible values: @@ -70,3 +71,21 @@ return &config->gspi[0]; } + +void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) +{ + DEVTREE_CONST struct soc_intel_cannonlake_config *config; + + /* Look up the device in devicetree */ + DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC); + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + config = dev->chip_info; + + /* Assign to out variable */ + *dw0 = config->gpe0_dw0; + *dw1 = config->gpe0_dw1; + *dw2 = config->gpe0_dw2; +} diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c deleted file mode 100644 index 951d886..0000000 --- a/src/soc/intel/cannonlake/pmutil.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Helper functions for dealing with power management registers - * and the differences between PCH variants. - */ - -#define __SIMPLE_DEVICE__ - -#include <arch/io.h> -#include <cbmem.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_def.h> -#include <console/console.h> -#include <intelblocks/pmclib.h> -#include <intelblocks/rtc.h> -#include <halt.h> -#include <rules.h> -#include <stdlib.h> -#include <soc/gpe.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/smbus.h> -#include <timer.h> -#include <security/vboot/vbnv.h> -#include "chip.h" - -/* - * SMI - */ - -const char *const *soc_smi_sts_array(size_t *a) -{ - static const char *const smi_sts_bits[] = { - [BIOS_STS_BIT] = "BIOS", - [LEGACY_USB_STS_BIT] = "LEGACY_USB", - [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI", - [APM_STS_BIT] = "APM", - [SWSMI_TMR_STS_BIT] = "SWSMI_TMR", - [PM1_STS_BIT] = "PM1", - [GPE0_STS_BIT] = "GPE0", - [GPIO_STS_BIT] = "GPI", - [MCSMI_STS_BIT] = "MCSMI", - [DEVMON_STS_BIT] = "DEVMON", - [TCO_STS_BIT] = "TCO", - [PERIODIC_STS_BIT] = "PERIODIC", - [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI", - [SMBUS_SMI_STS_BIT] = "SMBUS_SMI", - [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI", - [MONITOR_STS_BIT] = "MONITOR", - [SPI_SMI_STS_BIT] = "SPI", - [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK", - [ESPI_SMI_STS_BIT] = "ESPI_SMI", - }; - - *a = ARRAY_SIZE(smi_sts_bits); - return smi_sts_bits; -} - -/* - * TCO - */ - -const char *const *soc_tco_sts_array(size_t *a) -{ - static const char *const tco_sts_bits[] = { - [0] = "NMI2SMI", - [1] = "SW_TCO", - [2] = "TCO_INT", - [3] = "TIMEOUT", - [7] = "NEWCENTURY", - [8] = "BIOSWR", - [9] = "DMISCI", - [10] = "DMISMI", - [12] = "DMISERR", - [13] = "SLVSEL", - [16] = "INTRD_DET", - [17] = "SECOND_TO", - [18] = "BOOT", - [20] = "SMLINK_SLV" - }; - - *a = ARRAY_SIZE(tco_sts_bits); - return tco_sts_bits; -} - -/* - * GPE0 - */ - -const char *const *soc_std_gpe_sts_array(size_t *a) -{ - static const char *const gpe_sts_bits[] = { - [1] = "HOTPLUG", - [2] = "SWGPE", - [6] = "TCO_SCI", - [7] = "SMB_WAK", - [9] = "PCI_EXP", - [10] = "BATLOW", - [11] = "PME", - [12] = "ME", - [13] = "PME_B0", - [14] = "eSPI", - [15] = "GPIO Tier-2", - [16] = "LAN_WAKE", - [18] = "WADT" - }; - - *a = ARRAY_SIZE(gpe_sts_bits); - return gpe_sts_bits; -} - -void pmc_set_disb(void) -{ - /* Set the DISB after DRAM init */ - uint8_t disb_val; - /* Only care about bits [23:16] of register GEN_PMCON_A */ - uint8_t *addr = (void *)(pmc_mmio_regs() + GEN_PMCON_A + 2); - - disb_val = read8(addr); - disb_val |= (DISB >> 16); - - /* Don't clear bits that are write-1-to-clear */ - disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16); - write8(addr, disb_val); -} - -/* - * PMC controller gets hidden from PCI bus - * during FSP-Silicon init call. Hence PWRMBASE - * can't be accessible using PCI configuration space - * read/write. - */ -uint8_t *pmc_mmio_regs(void) -{ - return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS; -} - -uint16_t smbus_tco_regs(void) -{ - uint16_t reg16; - - reg16 = pci_read_config16(PCH_DEV_SMBUS, TCOBASE); - - return ALIGN_DOWN(reg16, 0x20); -} - -uint32_t soc_reset_tco_status(void) -{ - u16 tco1_sts; - u16 tco2_sts; - u16 tcobase; - - tcobase = smbus_tco_regs(); - - /* TCO Status 2 register */ - tco2_sts = inw(tcobase + TCO2_STS); - tco2_sts |= TCO2_STS_SECOND_TO; - outw(tco2_sts, tcobase + TCO2_STS); - - /* TCO Status 1 register */ - tco1_sts = inw(tcobase + TCO1_STS); - - /* Clear SECOND_TO_STS bit */ - if (tco2_sts & TCO2_STS_SECOND_TO) - outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS); - - return (tco2_sts << 16) | tco1_sts; -} - -uintptr_t soc_read_pmc_base(void) -{ - return (uintptr_t)pmc_mmio_regs(); -} - -void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) -{ - DEVTREE_CONST struct soc_intel_cannonlake_config *config; - - /* Look up the device in devicetree */ - DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC); - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); - return; - } - config = dev->chip_info; - - /* Assign to out variable */ - *dw0 = config->gpe0_dw0; - *dw1 = config->gpe0_dw1; - *dw2 = config->gpe0_dw2; -} - -static int rtc_failed(uint32_t gen_pmcon_b) -{ - return !!(gen_pmcon_b & RTC_BATTERY_DEAD); -} - -int soc_get_rtc_failed(void) -{ - const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); - - if (!ps) { - printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n"); - return 1; - } - - return rtc_failed(ps->gen_pmcon_b); -} - -int vbnv_cmos_failed(void) -{ - return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B)); -} -- To view, visit https://review.coreboot.org/25894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0eb3c4c75d25554a8829da71e32438c3458ccbfb Gerrit-Change-Number: 25894 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>

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Change in coreboot[master]: soc/intel/common: Create new common block pmc version 2
by Maulik V Vaghela (Code Review) 27 Apr '18

27 Apr '18

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/25893 Change subject: soc/intel/common: Create new common block pmc version 2 ...................................................................... soc/intel/common: Create new common block pmc version 2 Currently many soc uses pmc utility file named pmutil.c which has code which is common across many soc. We can make this file common and push it into common pmc block. Only SOC dependent function will be moved to chip_config file since this function returns soc related config for pmc. To use common functionality for pmc, use "select SOC_INTEL_COMMON_BLOCK_PMC_V2" Change-Id: I7c39666a48b813211e681272ed978db2a91c1bbf Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- A src/soc/intel/common/block/pmc_v2/Kconfig A src/soc/intel/common/block/pmc_v2/Makefile.inc A src/soc/intel/common/block/pmc_v2/pmutil.c 3 files changed, 225 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/25893/1 diff --git a/src/soc/intel/common/block/pmc_v2/Kconfig b/src/soc/intel/common/block/pmc_v2/Kconfig new file mode 100644 index 0000000..03a04c9 --- /dev/null +++ b/src/soc/intel/common/block/pmc_v2/Kconfig @@ -0,0 +1,8 @@ +config SOC_INTEL_COMMON_BLOCK_PMC_V2 + bool + default n + select SOC_INTEL_COMMON_BLOCK_PMC + help + This will use pm utility functionality from common pool instead of SOC. + This will enable common code for pmc utility functions and SOC must + implement function which returns SOC specific configuration. diff --git a/src/soc/intel/common/block/pmc_v2/Makefile.inc b/src/soc/intel/common/block/pmc_v2/Makefile.inc new file mode 100644 index 0000000..44a5e39 --- /dev/null +++ b/src/soc/intel/common/block/pmc_v2/Makefile.inc @@ -0,0 +1,6 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_V2)+=pmutil.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_V2)+=pmutil.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_V2)+=pmutil.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_V2)+=pmutil.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_V2)+=pmutil.c +verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_V2)+=pmutil.c diff --git a/src/soc/intel/common/block/pmc_v2/pmutil.c b/src/soc/intel/common/block/pmc_v2/pmutil.c new file mode 100644 index 0000000..ebda412 --- /dev/null +++ b/src/soc/intel/common/block/pmc_v2/pmutil.c @@ -0,0 +1,211 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Helper functions for dealing with power management registers + * and the differences between PCH variants. + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cbmem.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <console/console.h> +#include <intelblocks/pmclib.h> +#include <intelblocks/rtc.h> +#include <halt.h> +#include <rules.h> +#include <stdlib.h> +#include <soc/gpe.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <soc/smbus.h> +#include <timer.h> +#include <security/vboot/vbnv.h> + +/* + * SMI + */ + +const char *const *soc_smi_sts_array(size_t *a) +{ + static const char *const smi_sts_bits[] = { + [BIOS_STS_BIT] = "BIOS", + [LEGACY_USB_STS_BIT] = "LEGACY_USB", + [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI", + [APM_STS_BIT] = "APM", + [SWSMI_TMR_STS_BIT] = "SWSMI_TMR", + [PM1_STS_BIT] = "PM1", + [GPE0_STS_BIT] = "GPE0", + [GPIO_STS_BIT] = "GPI", + [MCSMI_STS_BIT] = "MCSMI", + [DEVMON_STS_BIT] = "DEVMON", + [TCO_STS_BIT] = "TCO", + [PERIODIC_STS_BIT] = "PERIODIC", + [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI", + [SMBUS_SMI_STS_BIT] = "SMBUS_SMI", + [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI", + [MONITOR_STS_BIT] = "MONITOR", + [SPI_SMI_STS_BIT] = "SPI", + [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK", + [ESPI_SMI_STS_BIT] = "ESPI_SMI", + }; + + *a = ARRAY_SIZE(smi_sts_bits); + return smi_sts_bits; +} + +/* + * TCO + */ + +const char *const *soc_tco_sts_array(size_t *a) +{ + static const char *const tco_sts_bits[] = { + [0] = "NMI2SMI", + [1] = "SW_TCO", + [2] = "TCO_INT", + [3] = "TIMEOUT", + [7] = "NEWCENTURY", + [8] = "BIOSWR", + [9] = "DMISCI", + [10] = "DMISMI", + [12] = "DMISERR", + [13] = "SLVSEL", + [16] = "INTRD_DET", + [17] = "SECOND_TO", + [18] = "BOOT", + [20] = "SMLINK_SLV" + }; + + *a = ARRAY_SIZE(tco_sts_bits); + return tco_sts_bits; +} + +/* + * GPE0 + */ + +const char *const *soc_std_gpe_sts_array(size_t *a) +{ + static const char *const gpe_sts_bits[] = { + [1] = "HOTPLUG", + [2] = "SWGPE", + [6] = "TCO_SCI", + [7] = "SMB_WAK", + [9] = "PCI_EXP", + [10] = "BATLOW", + [11] = "PME", + [12] = "ME", + [13] = "PME_B0", + [14] = "eSPI", + [15] = "GPIO Tier-2", + [16] = "LAN_WAKE", + [18] = "WADT" + }; + + *a = ARRAY_SIZE(gpe_sts_bits); + return gpe_sts_bits; +} + +void pmc_set_disb(void) +{ + /* Set the DISB after DRAM init */ + uint8_t disb_val; + /* Only care about bits [23:16] of register GEN_PMCON_A */ + uint8_t *addr = (void *)(pmc_mmio_regs() + GEN_PMCON_A + 2); + + disb_val = read8(addr); + disb_val |= (DISB >> 16); + + /* Don't clear bits that are write-1-to-clear */ + disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16); + write8(addr, disb_val); +} + +/* + * PMC controller gets hidden from PCI bus + * during FSP-Silicon init call. Hence PWRMBASE + * can't be accessible using PCI configuration space + * read/write. + */ +uint8_t *pmc_mmio_regs(void) +{ + return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS; +} + +uint16_t smbus_tco_regs(void) +{ + uint16_t reg16; + + reg16 = pci_read_config16(PCH_DEV_SMBUS, TCOBASE); + + return ALIGN_DOWN(reg16, 0x20); +} + +uint32_t soc_reset_tco_status(void) +{ + u16 tco1_sts; + u16 tco2_sts; + u16 tcobase; + + tcobase = smbus_tco_regs(); + + /* TCO Status 2 register */ + tco2_sts = inw(tcobase + TCO2_STS); + tco2_sts |= TCO2_STS_SECOND_TO; + outw(tco2_sts, tcobase + TCO2_STS); + + /* TCO Status 1 register */ + tco1_sts = inw(tcobase + TCO1_STS); + + /* Clear SECOND_TO_STS bit */ + if (tco2_sts & TCO2_STS_SECOND_TO) + outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS); + + return (tco2_sts << 16) | tco1_sts; +} + +uintptr_t soc_read_pmc_base(void) +{ + return (uintptr_t)pmc_mmio_regs(); +} + +static int rtc_failed(uint32_t gen_pmcon_b) +{ + return !!(gen_pmcon_b & RTC_BATTERY_DEAD); +} + +int soc_get_rtc_failed(void) +{ + const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + + if (!ps) { + printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n"); + return 1; + } + + return rtc_failed(ps->gen_pmcon_b); +} + +int vbnv_cmos_failed(void) +{ + return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B)); +} -- To view, visit https://review.coreboot.org/25893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7c39666a48b813211e681272ed978db2a91c1bbf Gerrit-Change-Number: 25893 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>

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Change in coreboot[master]: google/kahlee: Remove VBOOT_VBNV_CMOS
by build bot (Jenkins) (Code Review) 27 Apr '18

27 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25844 ) Change subject: google/kahlee: Remove VBOOT_VBNV_CMOS ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70910/ : SUCCESS -- To view, visit https://review.coreboot.org/25844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I30e517e06ab9d8f7d4a93bf82f12726756c44966 Gerrit-Change-Number: 25844 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 27 Apr 2018 09:33:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: google/kahlee: Add RW_NVRAM to FMAP
by build bot (Jenkins) (Code Review) 27 Apr '18

27 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25843 ) Change subject: google/kahlee: Add RW_NVRAM to FMAP ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70909/ : SUCCESS -- To view, visit https://review.coreboot.org/25843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id8c6f54634b94bf6ae3755a827e80d0862a42dd2 Gerrit-Change-Number: 25843 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Apr 2018 09:23:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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