coreboot-gerrit April 2018

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Change in coreboot[master]: [WIP] src/intel/apollolake: Unify name for uart debug config flag
by build bot (Jenkins) (Code Review) 27 Apr '18

27 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25904 ) Change subject: [WIP] src/intel/apollolake: Unify name for uart debug config flag ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/70951/ : FAILURE -- To view, visit https://review.coreboot.org/25904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0db5b034fa8cf62141ab16e916df21f941e1c2ae Gerrit-Change-Number: 25904 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Apr 2018 23:34:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP] src/intel/apollolake: Unify name for uart debug config flag
by build bot (Jenkins) (Code Review) 27 Apr '18

27 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25904 ) Change subject: [WIP] src/intel/apollolake: Unify name for uart debug config flag ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/25131/ : SUCCESS -- To view, visit https://review.coreboot.org/25904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0db5b034fa8cf62141ab16e916df21f941e1c2ae Gerrit-Change-Number: 25904 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Apr 2018 23:34:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP] src/intel/apollolake: Unify name for uart debug config flag
by Bora Guvendik (Code Review) 27 Apr '18

27 Apr '18

Bora Guvendik has uploaded a new patch set (#2). ( https://review.coreboot.org/25904 ) Change subject: [WIP] src/intel/apollolake: Unify name for uart debug config flag ...................................................................... [WIP] src/intel/apollolake: Unify name for uart debug config flag Big core defined CONFIG_UART_DEBUG and small core defined it as CONFIG_SOC_UART_DEBUG. Change small core to use CONFIG_UART_DEBUG as well so that common code for big/small cores can take advantage of it. Change-Id: I0db5b034fa8cf62141ab16e916df21f941e1c2ae Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/intel/leafhill/Kconfig M src/mainboard/intel/minnow3/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/romstage.c M src/soc/intel/apollolake/uart.c 6 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/25904/2 -- To view, visit https://review.coreboot.org/25904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0db5b034fa8cf62141ab16e916df21f941e1c2ae Gerrit-Change-Number: 25904 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com>

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Change in coreboot[master]: [WIP] src/soc/intel/apollolake: Unify name for uart debug config flag
by Bora Guvendik (Code Review) 27 Apr '18

27 Apr '18

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/25904 Change subject: [WIP] src/soc/intel/apollolake: Unify name for uart debug config flag ...................................................................... [WIP] src/soc/intel/apollolake: Unify name for uart debug config flag Big core defined CONFIG_UART_DEBUG and small core defined it as CONFIG_SOC_UART_DEBUG. Change small core to use CONFIG_UART_DEBUG as well so that common code for big/small cores can take advantage of it. Change-Id: I0db5b034fa8cf62141ab16e916df21f941e1c2ae Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/intel/leafhill/Kconfig M src/mainboard/intel/minnow3/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/romstage.c M src/soc/intel/apollolake/uart.c 6 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/25904/1 diff --git a/src/mainboard/intel/leafhill/Kconfig b/src/mainboard/intel/leafhill/Kconfig index c344615..1e5d5aa 100644 --- a/src/mainboard/intel/leafhill/Kconfig +++ b/src/mainboard/intel/leafhill/Kconfig @@ -55,7 +55,7 @@ depends on NEED_IFWI default y -config SOC_UART_DEBUG +config UART_DEBUG bool "use serial port debugging" default y diff --git a/src/mainboard/intel/minnow3/Kconfig b/src/mainboard/intel/minnow3/Kconfig index 76c9343..5b065ed 100644 --- a/src/mainboard/intel/minnow3/Kconfig +++ b/src/mainboard/intel/minnow3/Kconfig @@ -47,7 +47,7 @@ depends on NEED_IFWI default y -config SOC_UART_DEBUG +config UART_DEBUG bool "use serial port debugging" default y diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index a5842ec..3cb3e7a 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -175,8 +175,8 @@ hex default 0xde000000 -config SOC_UART_DEBUG - bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE." +config UART_DEBUG + bool "Enable UART debug port selected by UART_FOR_CONSOLE." default n select CONSOLE_SERIAL select DRIVERS_UART diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 854f328..0e2aaeb 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -18,7 +18,7 @@ bootblock-y += mmap_boot.c bootblock-y += pmutil.c bootblock-y += spi.c -bootblock-$(CONFIG_SOC_UART_DEBUG) += uart.c +bootblock-$(CONFIG_UART_DEBUG) += uart.c bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S romstage-y += car.c @@ -26,7 +26,7 @@ romstage-y += gspi.c romstage-y += heci.c romstage-y += i2c.c -romstage-$(CONFIG_SOC_UART_DEBUG) += uart.c +romstage-$(CONFIG_UART_DEBUG) += uart.c romstage-y += memmap.c romstage-y += meminit.c ifeq ($(CONFIG_SOC_INTEL_GLK),y) @@ -43,7 +43,7 @@ smm-y += pmutil.c smm-y += smihandler.c smm-y += spi.c -smm-$(CONFIG_SOC_UART_DEBUG) += uart.c +smm-$(CONFIG_UART_DEBUG) += uart.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c @@ -57,7 +57,7 @@ ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += mmap_boot.c -ramstage-$(CONFIG_SOC_UART_DEBUG) += uart.c +ramstage-$(CONFIG_UART_DEBUG) += uart.c ramstage-y += nhlt.c ramstage-y += spi.c ramstage-y += systemagent.c @@ -71,7 +71,7 @@ postcar-y += memmap.c postcar-y += mmap_boot.c postcar-y += spi.c -postcar-$(CONFIG_SOC_UART_DEBUG) += uart.c +postcar-$(CONFIG_UART_DEBUG) += uart.c postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S @@ -81,7 +81,7 @@ verstage-y += heci.c verstage-y += memmap.c verstage-y += mmap_boot.c -verstage-$(CONFIG_SOC_UART_DEBUG) += uart.c +verstage-$(CONFIG_UART_DEBUG) += uart.c verstage-y += pmutil.c verstage-y += reset.c verstage-y += spi.c diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index a8a0dd1..755f936 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -251,7 +251,7 @@ static void fill_console_params(FSPM_UPD *mupd) { if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { - if (IS_ENABLED(CONFIG_SOC_UART_DEBUG)) { + if (IS_ENABLED(CONFIG_UART_DEBUG)) { mupd->FspmConfig.SerialDebugPortDevice = CONFIG_UART_FOR_CONSOLE; /* use MMIO port type */ diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index 54b280d..0fce587 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -81,7 +81,7 @@ { pci_dev_read_resources(dev); - if (IS_ENABLED(CONFIG_SOC_UART_DEBUG) && + if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) { /* will override existing resource. */ fixed_mem_resource(dev, PCI_BASE_ADDRESS_0, -- To view, visit https://review.coreboot.org/25904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0db5b034fa8cf62141ab16e916df21f941e1c2ae Gerrit-Change-Number: 25904 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com>

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Change in coreboot[master]: cubieboard/qemu-armv7/am335x: Add fake TTB region for consistency
by build bot (Jenkins) (Code Review) 27 Apr '18

27 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25903 ) Change subject: cubieboard/qemu-armv7/am335x: Add fake TTB region for consistency ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/25130/ : SUCCESS -- To view, visit https://review.coreboot.org/25903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I51aa259fbb7a9c0ade72db905b1762c1c721f387 Gerrit-Change-Number: 25903 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Apr 2018 23:29:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: cubieboard/qemu-armv7/am335x: Add fake TTB region for consistency
by Julius Werner (Code Review) 27 Apr '18

27 Apr '18

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/25903 Change subject: cubieboard/qemu-armv7/am335x: Add fake TTB region for consistency ...................................................................... cubieboard/qemu-armv7/am335x: Add fake TTB region for consistency All ARM architecture boards are supposed to have a TTB region for their page tables. ARM systems cannot use the data cache without enabling paging, so it is imperative to do that as soon as possible. They will also fault on unaligned accesses when not using the cache, which breaks assumptions in CBFS code. Unfortunately, we have some old boards in various stages of disrepair in the tree that don't always follow these sorts of standard conventions. It's not clear whether they actually boot anymore and if anyone still has the respective hardware available to maintain them. I cannot really fix and test them right now, but we should at least create a fake TTB section for them so that common architecture code may make the correct assumptions about which regions exist. Change-Id: I51aa259fbb7a9c0ade72db905b1762c1c721f387 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/cpu/ti/am335x/memlayout.ld M src/mainboard/cubietech/cubieboard/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld 3 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/25903/1 diff --git a/src/cpu/ti/am335x/memlayout.ld b/src/cpu/ti/am335x/memlayout.ld index a6f41eb..9efb710 100644 --- a/src/cpu/ti/am335x/memlayout.ld +++ b/src/cpu/ti/am335x/memlayout.ld @@ -25,6 +25,9 @@ STACK(0x4030be00, 4K) RAMSTAGE(0x80200000, 192K) + /* TODO: Implement MMU support and move TTB to a better location. */ + TTB(0x81000000, 16K) + #ifdef OMAP_HEADER .header : { *(.header); diff --git a/src/mainboard/cubietech/cubieboard/memlayout.ld b/src/mainboard/cubietech/cubieboard/memlayout.ld index 55ba70a..b9bf10b 100644 --- a/src/mainboard/cubietech/cubieboard/memlayout.ld +++ b/src/mainboard/cubietech/cubieboard/memlayout.ld @@ -28,4 +28,7 @@ DRAM_START(0x40000000) RAMSTAGE(0x40000000, 16M) ROMSTAGE(0x41000000, 108K) + + /* TODO: Implement MMU support and move TTB to a better location. */ + TTB(0x42000000, 16K) } diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index 1b3a48b..776e051 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -47,4 +47,7 @@ STACK(0x60000000, 64K) ROMSTAGE(0x60010000, 128K) RAMSTAGE(0x60030000, 16M) + + /* TODO: Implement MMU support and move TTB to a better location. */ + TTB(0x61030000, 16K) } -- To view, visit https://review.coreboot.org/25903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I51aa259fbb7a9c0ade72db905b1762c1c721f387 Gerrit-Change-Number: 25903 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>

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Change in coreboot[master]: mb/google/octopus: Fix crossystem wpsw_cur error
by build bot (Jenkins) (Code Review) 27 Apr '18

27 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25892 ) Change subject: mb/google/octopus: Fix crossystem wpsw_cur error ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70949/ : SUCCESS -- To view, visit https://review.coreboot.org/25892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ica60f342420d95d09a45580f2f940443c03601de Gerrit-Change-Number: 25892 Gerrit-PatchSet: 2 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Apr 2018 22:45:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: buildgcc: Add missing '\'
by build bot (Jenkins) (Code Review) 27 Apr '18

27 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25901 ) Change subject: buildgcc: Add missing '\' ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70948/ : SUCCESS -- To view, visit https://review.coreboot.org/25901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I94521eb73cefdc5ed01fbf10122966a54cc28166 Gerrit-Change-Number: 25901 Gerrit-PatchSet: 2 Gerrit-Owner: Anonymous Coward #1001977 Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Apr 2018 22:29:08 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: buildgcc: Add missing '\'
by Youness Alaoui (Code Review) 27 Apr '18

27 Apr '18

Youness Alaoui has posted comments on this change. ( https://review.coreboot.org/25901 ) Change subject: buildgcc: Add missing '\' ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/25901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I94521eb73cefdc5ed01fbf10122966a54cc28166 Gerrit-Change-Number: 25901 Gerrit-PatchSet: 2 Gerrit-Owner: Anonymous Coward #1001977 Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Apr 2018 22:25:08 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: buildgcc: Add missing '\'
by build bot (Jenkins) (Code Review) 27 Apr '18

27 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25901 ) Change subject: buildgcc: Add missing '\' ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-toolchain/403/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/70947/ : FAILURE -- To view, visit https://review.coreboot.org/25901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I94521eb73cefdc5ed01fbf10122966a54cc28166 Gerrit-Change-Number: 25901 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward #1001977 Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Apr 2018 22:24:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit April 2018