coreboot-gerrit April 2018

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Change in coreboot[master]: device/dram/ddr3: improve XMP support
by Dan Elkouby (Code Review) 14 Apr '18

14 Apr '18

Dan Elkouby has uploaded this change for review. ( https://review.coreboot.org/25663 Change subject: device/dram/ddr3: improve XMP support ...................................................................... device/dram/ddr3: improve XMP support - Fix offsets for supported CAS latencies - Add support for reading CWL and CMD rate from the profile Change-Id: Ie4f545ed1df92c146be02f56fea0ca9037478649 Signed-off-by: Dan Elkouby <streetwalkermc(a)gmail.com> --- M src/device/dram/ddr3.c M src/include/device/dram/ddr3.h 2 files changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/25663/1 diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 67f3009..94061bf 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -295,6 +295,10 @@ dimm->tRTP = spd[27] * mtb; /* Minimum Four Activate Window Delay Time (tFAWmin) */ dimm->tFAW = (((spd[28] & 0x0f) << 8) + spd[29]) * mtb; + /* Minimum CAS Write Latency Time (tCWLmin) - not present in standard SPD */ + dimm->tCWL = 0; + /* Minimum CMD rate - not present in standard SPD */ + dimm->tCMD = 0; printram(" FTB timings :"); /* FTB is introduced in SPD revision 1.1 */ @@ -484,7 +488,7 @@ /* SDRAM Minimum Cycle Time (tCKmin) */ dimm->tCK = xmp[1] * mtb; /* CAS Latencies Supported */ - dimm->cas_supported = (xmp[9] << 8) + xmp[8]; + dimm->cas_supported = (xmp[4] << 8) + xmp[3]; /* Minimum CAS Latency Time (tAAmin) */ dimm->tAA = xmp[2] * mtb; /* Minimum Write Recovery Time (tWRmin) */ @@ -507,6 +511,10 @@ dimm->tRTP = xmp[16] * mtb; /* Minimum Four Activate Window Delay Time (tFAWmin) */ dimm->tFAW = (((xmp[18] & 0x0f) << 8) + xmp[19]) * mtb; + /* Minimum CAS Write Latency Time (tCWLmin) */ + dimm->tCWL = xmp[5] * mtb;; + /* Minimum CMD rate */ + dimm->tCMD = xmp[23] * mtb;; return ret; } @@ -568,6 +576,11 @@ print_ns(" tWTRmin : ", dimm->tWTR); print_ns(" tRTPmin : ", dimm->tRTP); print_ns(" tFAWmin : ", dimm->tFAW); + /* Those values are only relevant if an XMP profile sets them */ + if (dimm->tCWL) + print_ns(" tCWLmin : ", dimm->tCWL); + if (dimm->tCMD) + print_ns(" tCMDmin : ", dimm->tCMD); } /*============================================================================== diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 0756095..8ffdf0d 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -162,6 +162,8 @@ u32 tWTR; u32 tRTP; u32 tFAW; + u32 tCWL; + u32 tCMD; u8 reference_card; /* XMP: Module voltage in mV */ -- To view, visit https://review.coreboot.org/25663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie4f545ed1df92c146be02f56fea0ca9037478649 Gerrit-Change-Number: 25663 Gerrit-PatchSet: 1 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com>

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Change in coreboot[master]: mb/asus/p8z77-v_pro: Add ASUS P8Z77-V Pro
by Dan Elkouby (Code Review) 14 Apr '18

14 Apr '18

Dan Elkouby has uploaded this change for review. ( https://review.coreboot.org/25662 Change subject: mb/asus/p8z77-v_pro: Add ASUS P8Z77-V Pro ...................................................................... mb/asus/p8z77-v_pro: Add ASUS P8Z77-V Pro Working: - S3 - USB - GBE - PCIe - PCIe graphics - All SATA ports - HWM (PECI missing) - Native memory init with XMP - flashrom with the internal programmer, vendor firmware locks the BIOS region Untested: - EHCI debug - PCIe 1x slots, probably need enabling - The PCIe 4x slot from the southbridge shares lanes with some of the ASMedia chips on this board, and defaults to 1x or 2x mode, 4x mode untested - WiFi, I don't have the module installed - Onboard audio, mine is partially broken but it shows up in Linux - PCIe to PCI bridge, shows up in Linux but not tested - PS/2, enabled in devicetree but untested Not working: - Integrated graphics - Blinking the front panel LED in S3 - ASM1042 "charging mode" for 1A USB power Change-Id: I10baf73a848576a0ce7e18c6b36bcd605f80b211 Signed-off-by: Dan Elkouby <streetwalkermc(a)gmail.com> --- A src/mainboard/asus/p8z77-v_pro/Kconfig A src/mainboard/asus/p8z77-v_pro/Kconfig.name A src/mainboard/asus/p8z77-v_pro/Makefile.inc A src/mainboard/asus/p8z77-v_pro/acpi/ec.asl A src/mainboard/asus/p8z77-v_pro/acpi/platform.asl A src/mainboard/asus/p8z77-v_pro/acpi/superio.asl A src/mainboard/asus/p8z77-v_pro/acpi_tables.c A src/mainboard/asus/p8z77-v_pro/board_info.txt A src/mainboard/asus/p8z77-v_pro/devicetree.cb A src/mainboard/asus/p8z77-v_pro/dsdt.asl A src/mainboard/asus/p8z77-v_pro/gpio.c A src/mainboard/asus/p8z77-v_pro/hda_verb.c A src/mainboard/asus/p8z77-v_pro/mainboard.c A src/mainboard/asus/p8z77-v_pro/romstage.c 14 files changed, 830 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/25662/1 diff --git a/src/mainboard/asus/p8z77-v_pro/Kconfig b/src/mainboard/asus/p8z77-v_pro/Kconfig new file mode 100644 index 0000000..543e15a --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/Kconfig @@ -0,0 +1,73 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Dan Elkouby <streetwalkermc(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ASUS_P8Z77_V_PRO + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_SOCKET_LGA1155 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SANDYBRIDGE_IVYBRIDGE_LVDS + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select USE_NATIVE_RAMINIT + select SUPERIO_NUVOTON_NCT6779D + select DRIVERS_ASMEDIA_ASPM_BLACKLIST + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default asus/p8z77-v_pro + +config MAINBOARD_PART_NUMBER + string + default "P8Z77-V Pro" + +config VGA_BIOS_FILE + string + default "pci8086,0162.rom" + +config VGA_BIOS_ID + string + default "8086,0162" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x84ca + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1043 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: EHCI debug untested + int + default 2 +endif diff --git a/src/mainboard/asus/p8z77-v_pro/Kconfig.name b/src/mainboard/asus/p8z77-v_pro/Kconfig.name new file mode 100644 index 0000000..798ddb6 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P8Z77_V_PRO + bool "P8Z77-V Pro" diff --git a/src/mainboard/asus/p8z77-v_pro/Makefile.inc b/src/mainboard/asus/p8z77-v_pro/Makefile.inc new file mode 100644 index 0000000..0fd85ed --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Dan Elkouby <streetwalkermc(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += gpio.c diff --git a/src/mainboard/asus/p8z77-v_pro/acpi/ec.asl b/src/mainboard/asus/p8z77-v_pro/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/acpi/ec.asl diff --git a/src/mainboard/asus/p8z77-v_pro/acpi/platform.asl b/src/mainboard/asus/p8z77-v_pro/acpi/platform.asl new file mode 100644 index 0000000..2dc7e6e --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/acpi/platform.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Dan Elkouby <streetwalkermc(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/asus/p8z77-v_pro/acpi/superio.asl b/src/mainboard/asus/p8z77-v_pro/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/acpi/superio.asl diff --git a/src/mainboard/asus/p8z77-v_pro/acpi_tables.c b/src/mainboard/asus/p8z77-v_pro/acpi_tables.c new file mode 100644 index 0000000..345177f --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/acpi_tables.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Dan Elkouby <streetwalkermc(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asus/p8z77-v_pro/board_info.txt b/src/mainboard/asus/p8z77-v_pro/board_info.txt new file mode 100644 index 0000000..32f7a9e --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/board_info.txt @@ -0,0 +1,9 @@ +Category: desktop +Vendor name: ASUS +Board name: P8Z77-V Pro +ROM package: DIP8 +ROM socketed: y +ROM protocol: SPI +Flashrom support: y +Release year: 2012 + diff --git a/src/mainboard/asus/p8z77-v_pro/devicetree.cb b/src/mainboard/asus/p8z77-v_pro/devicetree.cb new file mode 100644 index 0000000..c6747f4 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/devicetree.cb @@ -0,0 +1,175 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Dan Elkouby <streetwalkermc(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "4" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/socket_LGA1155 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x00000000" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "p_cnt_throttling_supported" = "0" + register "pcie_hotplug_map" = "{ 1, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x1043 0x84ca + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1043 0x84ca + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1043 0x849c + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1043 0x84ca + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x1043 0x84fb + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1043 0x84ca + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x1043 0x84ca + end + device pci 1c.3 on # PCIe Port #4 + subsystemid 0x1043 0x84ca + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x1043 0x84ca + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 on # PCIe Port #8 + subsystemid 0x1043 0x84ca + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1043 0x84ca + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-8 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 + device pnp 2e.9 off end # GPIO1-8 + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware Monitor, Front Panel LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO Push-pull/Open-drain selection + device pnp 2e.14 off end # PORT80 UART + device pnp 2e.16 off end # Deep Sleep + device pnp 2e.108 off end # GPIO0 + device pnp 2e.109 on end # GPIO1 + device pnp 2e.209 on end # GPIO2 + device pnp 2e.309 on end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 on end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1043 0x84ca + end + device pci 1f.3 on # SMBus + subsystemid 0x1043 0x84ca + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1043 0x84ca + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x1043 0x84ca + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x1043 0x84ca + end + device pci 01.1 on + subsystemid 0x1043 0x84ca + end + end +end diff --git a/src/mainboard/asus/p8z77-v_pro/dsdt.asl b/src/mainboard/asus/p8z77-v_pro/dsdt.asl new file mode 100644 index 0000000..ab31a0c --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/dsdt.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Dan Elkouby <streetwalkermc(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } +} diff --git a/src/mainboard/asus/p8z77-v_pro/gpio.c b/src/mainboard/asus/p8z77-v_pro/gpio.c new file mode 100644 index 0000000..01356e6 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/gpio.c @@ -0,0 +1,195 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Dan Elkouby <streetwalkermc(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8z77-v_pro/hda_verb.c b/src/mainboard/asus/p8z77-v_pro/hda_verb.c new file mode 100644 index 0000000..6ac44eb --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/hda_verb.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Dan Elkouby <streetwalkermc(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x104384fb, /* Subsystem ID */ + + 0x0000000f, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x104384fb), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0x99430140), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x01014010), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x01011012), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x0, 0x16, 0x01016011), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x01012014), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x01a19850), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19c60), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x0181305f), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214c20), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x4005e601), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x01456130), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x58560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p8z77-v_pro/mainboard.c b/src/mainboard/asus/p8z77-v_pro/mainboard.c new file mode 100644 index 0000000..14a056c --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/mainboard.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Dan Elkouby <streetwalkermc(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(device_t dev) +{ + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/p8z77-v_pro/romstage.c b/src/mainboard/asus/p8z77-v_pro/romstage.c new file mode 100644 index 0000000..3c85804 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/romstage.c @@ -0,0 +1,137 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Dan Elkouby <streetwalkermc(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> + +#define SIO_PORT 0x2e +#define SIO_DEV PNP_DEV(SIO_PORT, 0) +#define GPIO_PPOD_DEV PNP_DEV(SIO_PORT, NCT6779D_GPIO_PP_OD) +#define ACPI_DEV PNP_DEV(SIO_PORT, NCT6779D_ACPI) +#define HWM_DEV PNP_DEV(SIO_PORT, NCT6779D_HWM_FPLED) +#define GPIO_DEV PNP_DEV(SIO_PORT, NCT6779D_GPIO12345678_V) +#define GPIO01_DEV PNP_DEV(SIO_PORT, NCT6779D_WDT1_GPIO01_V) + +void pch_enable_lpc(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 2, 0 }, + { 1, 2, 0 }, + { 1, 2, 1 }, + { 1, 2, 1 }, + { 1, 2, 2 }, + { 1, 2, 2 }, + { 1, 2, 3 }, + { 1, 2, 3 }, + { 1, 2, 4 }, + { 1, 2, 4 }, + { 1, 2, 6 }, + { 1, 2, 5 }, + { 1, 2, 5 }, + { 1, 2, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(SIO_DEV); + + /* Pin function selection */ + pnp_write_config(SIO_DEV, 0x1a, 0x00); + pnp_write_config(SIO_DEV, 0x2a, 0x40); + pnp_write_config(SIO_DEV, 0x2c, 0x00); + + pnp_set_logical_device(GPIO_PPOD_DEV); + pnp_write_config(SIO_DEV, 0xe4, 0xfc); + pnp_write_config(SIO_DEV, 0xe6, 0x7f); + + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(SIO_DEV, 0xe2, 0x76); + + /* Power RAM in S3 */ + pnp_write_config(SIO_DEV, 0xe4, 0x10); + + pnp_set_logical_device(HWM_DEV); + pnp_write_config(SIO_DEV, 0xe2, 0x7f); + pnp_write_config(SIO_DEV, 0xe4, 0xf1); + pnp_write_config(SIO_DEV, 0xf0, 0x3e); + + pnp_set_logical_device(GPIO_DEV); + pnp_write_config(SIO_DEV, 0x30, 0x2e); + + /* GPIO2 */ + pnp_write_config(SIO_DEV, 0xe0, 0xdf); + pnp_write_config(SIO_DEV, 0xe2, 0x00); + pnp_write_config(SIO_DEV, 0xe9, 0x00); + pnp_write_config(SIO_DEV, 0xe1, 0xc0); + + /* GPIO3 */ + pnp_write_config(SIO_DEV, 0xe4, 0x7f); + pnp_write_config(SIO_DEV, 0xe6, 0x00); + pnp_write_config(SIO_DEV, 0xea, 0x00); + pnp_write_config(SIO_DEV, 0xe5, 0x70); + + /* GPIO5 */ + pnp_write_config(SIO_DEV, 0xf4, 0xfc); + pnp_write_config(SIO_DEV, 0xf6, 0x00); + pnp_write_config(SIO_DEV, 0xeb, 0x00); + pnp_write_config(SIO_DEV, 0xf5, 0x88); + + pnp_set_logical_device(GPIO01_DEV); + + /* GPIO1 */ + pnp_write_config(SIO_DEV, 0xf0, 0x7f); + pnp_write_config(SIO_DEV, 0xf2, 0x00); + pnp_write_config(SIO_DEV, 0xf4, 0x00); + pnp_write_config(SIO_DEV, 0xf1, 0x03); + + nuvoton_pnp_exit_conf_state(SIO_DEV); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} -- To view, visit https://review.coreboot.org/25662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I10baf73a848576a0ce7e18c6b36bcd605f80b211 Gerrit-Change-Number: 25662 Gerrit-PatchSet: 1 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com>

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Change in coreboot[master]: autoport: add missing PCIIDs
by Dan Elkouby (Code Review) 14 Apr '18

14 Apr '18

Dan Elkouby has uploaded this change for review. ( https://review.coreboot.org/25661 Change subject: autoport: add missing PCIIDs ...................................................................... autoport: add missing PCIIDs As seen on ASUS P8Z77-V Pro Change-Id: I9fce9a35174b5120f67c2345a0807db1b843eb48 Signed-off-by: Dan Elkouby <streetwalkermc(a)gmail.com> --- M util/autoport/bd82x6x.go 1 file changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/25661/1 diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 26c8b91..31f7ced 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -433,11 +433,12 @@ /* PCIe bridge */ for _, id := range []uint16{ - 0x0151, 0x1c10, 0x1c12, 0x1c14, - 0x1c16, 0x1c18, 0x1c1a, 0x1c1c, - 0x1c1e, 0x1e10, 0x1e12, 0x1e14, - 0x1e16, 0x1e18, 0x1e1a, 0x1e1c, - 0x1e1e, 0x1e25, 0x244e, 0x2448, + 0x0151, 0x0155, 0x1c10, 0x1c12, + 0x1c14, 0x1c16, 0x1c18, 0x1c1a, + 0x1c1c, 0x1c1e, 0x1e10, 0x1e12, + 0x1e14, 0x1e16, 0x1e18, 0x1e1a, + 0x1e1c, 0x1e1e, 0x1e25, 0x244e, + 0x2448, } { RegisterPCI(0x8086, id, GenericPCI{}) } @@ -474,5 +475,6 @@ /* Ethernet */ RegisterPCI(0x8086, 0x1502, GenericPCI{}) + RegisterPCI(0x8086, 0x1503, GenericPCI{}) } -- To view, visit https://review.coreboot.org/25661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9fce9a35174b5120f67c2345a0807db1b843eb48 Gerrit-Change-Number: 25661 Gerrit-PatchSet: 1 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com>

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Change in coreboot[master]: sb/intel/bd82x6x: re-init SPI after lockdown
by Dan Elkouby (Code Review) 14 Apr '18

14 Apr '18

Dan Elkouby has uploaded this change for review. ( https://review.coreboot.org/25660 Change subject: sb/intel/bd82x6x: re-init SPI after lockdown ...................................................................... sb/intel/bd82x6x: re-init SPI after lockdown SMM final locks the SPI BAR, which causes e.g. flashconsole to hang Change-Id: Ib802d7ee32f1fb0a68a84b0280480dcaefa9831f Signed-off-by: Dan Elkouby <streetwalkermc(a)gmail.com> --- M src/southbridge/intel/bd82x6x/lpc.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/25660/1 diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index c57eeca..8d8d177 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -862,6 +862,7 @@ if (IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) { outb(APM_CNT_FINALIZE, APM_CNT); + spi_init(); } } } -- To view, visit https://review.coreboot.org/25660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib802d7ee32f1fb0a68a84b0280480dcaefa9831f Gerrit-Change-Number: 25660 Gerrit-PatchSet: 1 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com>

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Change in coreboot[master]: mb/asrock/g41c-gs: Add the revision 1 variant
by build bot (Jenkins) (Code Review) 14 Apr '18

14 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21292 ) Change subject: mb/asrock/g41c-gs: Add the revision 1 variant ...................................................................... Patch Set 15: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24371/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/70122/ : SUCCESS -- To view, visit https://review.coreboot.org/21292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib69c2ac0a9dc1b5c46220d2d2d5239edc99b0516 Gerrit-Change-Number: 21292 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: AndiR <andir(a)memeware.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 18:59:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/asus/p5qpl-am: Add support for ASUS P5QPL-AM
by build bot (Jenkins) (Code Review) 14 Apr '18

14 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25659 ) Change subject: mb/asus/p5qpl-am: Add support for ASUS P5QPL-AM ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/70123/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/24372/ : SUCCESS -- To view, visit https://review.coreboot.org/25659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I160f9201e812f44ef9842caef851750fb7690c9e Gerrit-Change-Number: 25659 Gerrit-PatchSet: 1 Gerrit-Owner: AndiR <andir(a)memeware.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 18:49:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/asus/p5qpl-am: Add support for ASUS P5QPL-AM
by AndiR (Code Review) 14 Apr '18

14 Apr '18

AndiR has uploaded this change for review. ( https://review.coreboot.org/25659 Change subject: mb/asus/p5qpl-am: Add support for ASUS P5QPL-AM ...................................................................... mb/asus/p5qpl-am: Add support for ASUS P5QPL-AM Adding support for https://www.asus.com/Motherboards/P5QPLAM/ The board have a Intel G41 chipset and a Winbond W83627DHG SuperIO. Code is been taken from the Asrock G41C-GS Rev 1 from https://review.coreboot.org/#/c/coreboot/+/21292/ The only required change was a new gpio.c file. Tested and working: PS2, USB, Sound, CPU, GPU, RAM(both dimms) - on Linux 4.14 Change-Id: I160f9201e812f44ef9842caef851750fb7690c9e --- A src/mainboard/asus/p5qpl-am/Kconfig A src/mainboard/asus/p5qpl-am/Kconfig.name A src/mainboard/asus/p5qpl-am/Makefile.inc A src/mainboard/asus/p5qpl-am/acpi/ec.asl A src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl A src/mainboard/asus/p5qpl-am/acpi/platform.asl A src/mainboard/asus/p5qpl-am/acpi/superio.asl A src/mainboard/asus/p5qpl-am/acpi/x4x_pci_irqs.asl A src/mainboard/asus/p5qpl-am/acpi_tables.c A src/mainboard/asus/p5qpl-am/board_info.txt A src/mainboard/asus/p5qpl-am/cmos.default A src/mainboard/asus/p5qpl-am/cmos.layout A src/mainboard/asus/p5qpl-am/cstates.c A src/mainboard/asus/p5qpl-am/devicetree.cb A src/mainboard/asus/p5qpl-am/dsdt.asl A src/mainboard/asus/p5qpl-am/gpio.c A src/mainboard/asus/p5qpl-am/hda_verb.c A src/mainboard/asus/p5qpl-am/romstage.c 18 files changed, 868 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/25659/1 diff --git a/src/mainboard/asus/p5qpl-am/Kconfig b/src/mainboard/asus/p5qpl-am/Kconfig new file mode 100644 index 0000000..e69a773 --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/Kconfig @@ -0,0 +1,54 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ASUS_P5QPL_AM + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_X4X + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627DHG + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_1024 + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_L1_SUB_STATE + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select DRIVERS_I2C_CK505 + +config MAINBOARD_DIR + string + default "asus/p5qpl-am" + +config MAINBOARD_PART_NUMBER + string + default "P5QPL-AM" + +config DEVICETREE + string + default "p5qpl-am/devicetree.cb" + +config MAX_CPUS + int + default 4 + +endif # BOARD_ASUS_P5QPL_AM diff --git a/src/mainboard/asus/p5qpl-am/Kconfig.name b/src/mainboard/asus/p5qpl-am/Kconfig.name new file mode 100644 index 0000000..7a101b9 --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_ASUS_P5QPL_AM + bool "P5QPL-AM" + diff --git a/src/mainboard/asus/p5qpl-am/Makefile.inc b/src/mainboard/asus/p5qpl-am/Makefile.inc new file mode 100644 index 0000000..f3d7e76 --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/Makefile.inc @@ -0,0 +1,2 @@ +ramstage-y += cstates.c +romstage-y += gpio.c diff --git a/src/mainboard/asus/p5qpl-am/acpi/ec.asl b/src/mainboard/asus/p5qpl-am/acpi/ec.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl b/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..bb8745e --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + /* PCI1 SLOT 1 */ + Package() { 0x0001ffff, 0, 0, 0x16}, + Package() { 0x0001ffff, 1, 0, 0x17}, + Package() { 0x0001ffff, 2, 0, 0x14}, + Package() { 0x0001ffff, 3, 0, 0x15}, + + /* PCI1 SLOT 2 */ + Package() { 0x0002ffff, 0, 0, 0x17}, + Package() { 0x0002ffff, 1, 0, 0x14}, + Package() { 0x0002ffff, 2, 0, 0x15}, + Package() { 0x0002ffff, 3, 0, 0x16}, + + /* device not in lspci but in vendor DSDT */ + /* Package() { 0x0008ffff, 0, 0, 0x14}, */ + }) +} Else { + Return (Package() { + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKF, 0}, + + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKG, 0}, + + /* device not in lspci but in vendor DSDT */ + /* Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, */ + }) +} diff --git a/src/mainboard/asus/p5qpl-am/acpi/platform.asl b/src/mainboard/asus/p5qpl-am/acpi/platform.asl new file mode 100644 index 0000000..6c92a4e --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} diff --git a/src/mainboard/asus/p5qpl-am/acpi/superio.asl b/src/mainboard/asus/p5qpl-am/acpi/superio.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/acpi/superio.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/asus/p5qpl-am/acpi/x4x_pci_irqs.asl b/src/mainboard/asus/p5qpl-am/acpi/x4x_pci_irqs.asl new file mode 100644 index 0000000..5bec150 --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/acpi/x4x_pci_irqs.asl @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for x4x */ + +/* PCI Interrupt Routing */ +Method(_PRT) +{ + If (PICM) { + Return (Package() { + /* PEG */ + Package() { 0x0001ffff, 0, 0, 0x10 }, + /* Internal GFX */ + Package() { 0x0002ffff, 0, 0, 0x10 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, 0, 0x10 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, 0, 0x10 }, + Package() { 0x001cffff, 1, 0, 0x11 }, + Package() { 0x001cffff, 2, 0, 0x12 }, + Package() { 0x001cffff, 3, 0, 0x13 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, 0, 0x17 }, + Package() { 0x001dffff, 1, 0, 0x13 }, + Package() { 0x001dffff, 2, 0, 0x12 }, + Package() { 0x001dffff, 3, 0, 0x10 }, + /* PATA/SATA/SMBUS 0:1f.1-3 */ + Package() { 0x001fffff, 0, 0, 0x12 }, + Package() { 0x001fffff, 1, 0, 0x13 }, + }) + } Else { + Return (Package() { + /* PEG */ + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* Internal GFX */ + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + /* PATA/SATA/SMBUS 0:1f.1-3 */ + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} diff --git a/src/mainboard/asus/p5qpl-am/acpi_tables.c b/src/mainboard/asus/p5qpl-am/acpi_tables.c new file mode 100644 index 0000000..d80fb4c --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/acpi_tables.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <stdint.h> + +#include "southbridge/intel/i82801gx/nvs.h" + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + + gnvs->pwrs = 1; /* Power state (AC = 1) */ + gnvs->cmap = 0x01; /* Enable COM 1 port */ +} diff --git a/src/mainboard/asus/p5qpl-am/board_info.txt b/src/mainboard/asus/p5qpl-am/board_info.txt new file mode 100644 index 0000000..cae9f22 --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/P5QPLAM/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2009 diff --git a/src/mainboard/asus/p5qpl-am/cmos.default b/src/mainboard/asus/p5qpl-am/cmos.default new file mode 100644 index 0000000..1519fe1 --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Spew +power_on_after_fail=Disable +nmi=Enable +gfx_uma_size=64M diff --git a/src/mainboard/asus/p5qpl-am/cmos.layout b/src/mainboard/asus/p5qpl-am/cmos.layout new file mode 100644 index 0000000..57c30ae --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/cmos.layout @@ -0,0 +1,105 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 5 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: cpu +#424 1 e 2 hyper_threading +#425 7 r 0 unused + +# coreboot config options: northbridge +432 4 e 11 gfx_uma_size +#435 549 r 0 unused + + +# coreboot config options: check sums +984 16 h 0 check_sum + +1024 144 r 0 recv_enable_results +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/p5qpl-am/cstates.c b/src/mainboard/asus/p5qpl-am/cstates.c new file mode 100644 index 0000000..128f655 --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/cstates.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb new file mode 100644 index 0000000..911e6fc --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/devicetree.cb @@ -0,0 +1,139 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xACAC off end + end + end + device domain 0 on # PCI domain + subsystemid 0x1458 0x5000 inherit + device pci 0.0 on # Host Bridge + subsystemid 0x1849 0x2e30 + end + device pci 1.0 on end # PEG + + device pci 2.0 on # Integrated graphics controller + subsystemid 0x1849 0x2e32 + end + device pci 3.0 off end # ME + device pci 3.1 off end # ME + chip southbridge/intel/i82801gx # Southbridge + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x0b" + + register "ide_enable_primary" = "0x1" + register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant + register "sata_ports_implemented" = "0x3" + register "gpe0_en" = "0x440" + + device pci 1b.0 on # Audio + subsystemid 0x1849 0x3662 + end + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on end # PCIe 2 + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1d.0 on # USB + subsystemid 0x1849 0x27c8 + end + device pci 1d.1 on # USB + subsystemid 0x1849 0x27c9 + end + device pci 1d.2 on # USB + subsystemid 0x1849 0x27ca + end + device pci 1d.3 on # USB + subsystemid 0x1849 0x27cb + end + device pci 1d.7 on # USB + subsystemid 0x1849 0x27cc + end + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # ISA bridge + subsystemid 0x1849 0x27b8 + chip superio/winbond/w83627dhg + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + # global + irq 0x28 = 0x70 + irq 0x2c = 0xd2 + # parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2 + device pnp 2e.5 on # Keyboard & MOUSE + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 0x0C + end + device pnp 2e.6 off end # SPI + device pnp 2e.7 off end # GPIO6 + device pnp 2e.8 off end # WDT0#, PLED + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 on # GPIO4 + irq 0xf4 = 0x73 + end + device pnp 2e.309 off end # GPIO5 + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # Power dram during s3 + end + device pnp 2e.b on # HWM, front pannel LED + io 0x60 = 0x290 + irq 0x70 = 0 + end + device pnp 2e.c off end # PECI, SST + end + end + device pci 1f.1 on # PATA/IDE + subsystemid 0x1849 0x27df + end + device pci 1f.2 on # SATA + subsystemid 0x1849 0x27c0 + end + device pci 1f.3 on # SMbus + subsystemid 0x1849 0x27da + chip drivers/i2c/ck505 # W83115RG-965 + # set SATA to fixed 100Mhz refclk + register "mask" = "{ 0x02 }" + register "regs" = "{ 0x02 }" + device i2c 69 on end + end + end + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 off end + end + end +end diff --git a/src/mainboard/asus/p5qpl-am/dsdt.asl b/src/mainboard/asus/p5qpl-am/dsdt.asl new file mode 100644 index 0000000..e11eb39 --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/dsdt.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/i82801gx/i82801gx.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // global NVS and variables + #include "acpi/platform.asl" + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/x4x/acpi/x4x.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/asus/p5qpl-am/gpio.c b/src/mainboard/asus/p5qpl-am/gpio.c new file mode 100644 index 0000000..97d553a --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/gpio.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio16 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, +}; + + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/asus/p5qpl-am/hda_verb.c b/src/mainboard/asus/p5qpl-am/hda_verb.c new file mode 100644 index 0000000..1c0474b --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/hda_verb.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + /* Realtek ALC662 rev1 */ + 0x10ec0662, /* Vendor ID */ + 0x18493662, /* Subsystem ID */ + 10, /* Number of entries */ + + /* Pin Widget Verb Table */ + + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19830), + AZALIA_PIN_CFG(0, 0x19, 0x02a19940), + AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214120), + AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* coreboot specific header */ + /* Intel Eaglelake HDMI */ + 0x80862803, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 0x00000001, /* Number of entries */ + + /* Pin Widget Verb Table */ + + AZALIA_PIN_CFG(1, 0x03, 0x18560010), + + + /* coreboot specific header */ + /* Realtek ALC662 rev1 */ + 0x10ec0662, /* Vendor ID */ + 0x1565821e, /* Subsystem ID */ + 10, /* Number of entries */ + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(2, 0x14, 0x01014410), + AZALIA_PIN_CFG(2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(2, 0x18, 0x01a19c30), + AZALIA_PIN_CFG(2, 0x19, 0x02a19c40), + AZALIA_PIN_CFG(2, 0x1a, 0x0181343f), + AZALIA_PIN_CFG(2, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); +const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data); diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c new file mode 100644 index 0000000..4f8078e --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/gpio.h> +#include <northbridge/intel/x4x/x4x.h> +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> +#include <superio/winbond/common/winbond.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <lib.h> +#include <arch/stages.h> +#include <cbmem.h> +#include <northbridge/intel/x4x/iomap.h> +#include <device/pnp_def.h> +#include <timestamp.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) +#define SUPERIO_DEV PNP_DEV(0x2e, 0) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +static void mb_lpc_setup(void) +{ + u32 reg32; + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); + pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); + + setup_pch_gpios(&mainboard_gpio_map); + + /* Set GPIOs on superio, enable UART */ + winbond_enable_serial(SERIAL_DEV_R1, CONFIG_TTYS0_BASE); + + /* IRQ routing */ + RCBA16(D31IR) = 0x0132; + RCBA16(D29IR) = 0x0237; + + /* Enable IOAPIC */ + RCBA8(OIC) = 0x03; + RCBA8(OIC); + + reg32 = RCBA32(GCS); + reg32 |= (1 << 5); + RCBA32(GCS) = reg32; + RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD + | FD_ACAUD | 1; + RCBA32(CG) = 0x00000001; +} + +static void ich7_enable_lpc(void) +{ + pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + /* Decode range */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN + | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0291); +} + +void mainboard_romstage_entry(unsigned long bist) +{ + // ch0 ch1 + const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; + u8 boot_path = 0; + u8 s3_resume; + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + + /* Set southbridge and Super I/O GPIOs. */ + ich7_enable_lpc(); + mb_lpc_setup(); + + console_init(); + + report_bist_failure(bist); + enable_smbus(); + + x4x_early_init(); + + s3_resume = southbridge_detect_s3_resume(); + if (s3_resume) + boot_path = BOOT_PATH_RESUME; + if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) + boot_path = BOOT_PATH_WARM_RESET; + + printk(BIOS_DEBUG, "Initializing memory\n"); + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_initialize(boot_path, spd_addrmap); + timestamp_add_now(TS_AFTER_INITRAM); + quick_ram_check(); + printk(BIOS_DEBUG, "Memory initialized\n"); + + x4x_late_init(s3_resume); + + printk(BIOS_DEBUG, "x4x late init complete\n"); + +} -- To view, visit https://review.coreboot.org/25659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I160f9201e812f44ef9842caef851750fb7690c9e Gerrit-Change-Number: 25659 Gerrit-PatchSet: 1 Gerrit-Owner: AndiR <andir(a)memeware.net>

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Change in coreboot[master]: nb/intel/sandybridge/peg: Add PEG driver stub
by build bot (Jenkins) (Code Review) 14 Apr '18

14 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22337 ) Change subject: nb/intel/sandybridge/peg: Add PEG driver stub ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24370/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/70121/ : SUCCESS -- To view, visit https://review.coreboot.org/22337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I96835c43522580c95fd4f250c56bf9438e993bc1 Gerrit-Change-Number: 22337 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christoph Pomaska <cp_public(a)posteo.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Renze Nicolai <renze(a)rnplus.nl> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Comment-Date: Fri, 13 Apr 2018 16:54:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge/lpc.c: Fix bit definitions
by build bot (Jenkins) (Code Review) 14 Apr '18

14 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25658 ) Change subject: soc/amd/stoneyridge/lpc.c: Fix bit definitions ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24369/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/70120/ : SUCCESS -- To view, visit https://review.coreboot.org/25658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie8d3fcccb8443c1a6db828bdc2624778bad6ba9f Gerrit-Change-Number: 25658 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 16:54:43 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge/lpc.c: Fix bit definitions
by Richard Spiegel (Code Review) 14 Apr '18

14 Apr '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25658 Change subject: soc/amd/stoneyridge/lpc.c: Fix bit definitions ...................................................................... soc/amd/stoneyridge/lpc.c: Fix bit definitions The latest public BKDG releases some previously undefined (reserved) bits, also some bits were wrongly named (possibly copied from previous chip). Fix these definitions, including header file where they are defined. BUG=b:77940747 TEST=Build and boot grunt. Change-Id: Ie8d3fcccb8443c1a6db828bdc2624778bad6ba9f Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/lpc.c 2 files changed, 17 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/25658/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index bdcb38f..c0a48b3 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -107,6 +107,9 @@ #define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) #define LPC_PCI_CONTROL 0x40 +#define IMC_PRESENT BIT(7) +#define IMC_TO_HOST_SEMAPHORE BIT(6) +#define HOST_TO_IMC_SEMAPHORE BIT(5) #define LEGACY_DMA_EN BIT(2) #define LPC_IO_PORT_DECODE_ENABLE 0x44 @@ -149,12 +152,17 @@ #define DECODE_IO_PORT_ENABLE6 BIT(23) #define DECODE_IO_PORT_ENABLE5 BIT(22) #define DECODE_IO_PORT_ENABLE4 BIT(21) +#define DECODE_MEM_PORT_ENABLE1 BIT(20) #define DECODE_IO_PORT_ENABLE3 BIT(19) #define DECODE_IO_PORT_ENABLE2 BIT(18) #define DECODE_IO_PORT_ENABLE1 BIT(17) #define DECODE_IO_PORT_ENABLE0 BIT(16) #define LPC_SYNC_TIMEOUT_COUNT_ENABLE BIT(7) +#define LPC_DECODE_RTC_IO_ENABLE BIT(6) +#define DECODE_MEM_PORT_ENABLE0 BIT(5) #define LPC_WIDEIO0_ENABLE BIT(2) +#define DECODE_ALTERNATE_SIO_ENABLE BIT(1) +#define DECODE_SIO_ENABLE BIT(0) /* Assuming word access to higher word (register 0x4a) */ #define LPC_IO_OR_MEM_DEC_EN_HIGH 0x4a #define LPC_WIDEIO2_ENABLE_H BIT(9) @@ -167,6 +175,9 @@ #define DECODE_IO_PORT_ENABLE1_H BIT(1) #define DECODE_IO_PORT_ENABLE0_H BIT(0) +#define LPC_MEM_PORT1 0x4c +#define LPC_MEM_PORT0 0x60 + /* * Register 0x64 is 32-bit, composed by two 16-bit sub-registers. * For ease of access, each sub-register is declared separetely. @@ -200,7 +211,8 @@ #define LPC_ROM_DMA_EC_HOST_CONTROL 0xb8 #define LPC_HOST_CONTROL 0xbb -#define SPI_FROM_HOST_PREFETCH_EN BIT(0) +#define IMC_PAGE_FROM_HOST_EN BIT(0) +#define IMC_PORT_FROM_HOST_EN BIT(3) /* SPI Controller */ #define SPI_CNTRL0 0x00 diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index 10f4a4b..eb51281 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -76,11 +76,12 @@ pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte); /* - * bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. - * todo: verify against BKDG + * IMC is not used, but some of its registers and ports need to be + * programmed/accessed. So enable CPU access to them. This fixes + * SPI_CS# timing issue when running at 66MHz. */ byte = pci_read_config8(dev, LPC_HOST_CONTROL); - byte |= SPI_FROM_HOST_PREFETCH_EN | 1 << 3; + byte |= IMC_PAGE_FROM_HOST_EN | IMC_PORT_FROM_HOST_EN; pci_write_config8(dev, LPC_HOST_CONTROL, byte); cmos_check_update_date(); -- To view, visit https://review.coreboot.org/25658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie8d3fcccb8443c1a6db828bdc2624778bad6ba9f Gerrit-Change-Number: 25658 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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coreboot-gerrit April 2018