coreboot-gerrit April 2018

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Change in coreboot[master]: autoport: add missing PCIIDs
by Patrick Rudolph (Code Review) 14 Apr '18

14 Apr '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/25661 ) Change subject: autoport: add missing PCIIDs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/25661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9fce9a35174b5120f67c2345a0807db1b843eb48 Gerrit-Change-Number: 25661 Gerrit-PatchSet: 1 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 14 Apr 2018 09:47:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/sandybridge: support more XMP timings
by Patrick Rudolph (Code Review) 14 Apr '18

14 Apr '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/25664 ) Change subject: nb/intel/sandybridge: support more XMP timings ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/#/c/25664/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/25664/1//COMMIT_MSG@8 PS1, Line 8: How did you test it ? Why introduce the change ? Does it improve performance or stability ? https://review.coreboot.org/#/c/25664/1/src/northbridge/intel/sandybridge/r… File src/northbridge/intel/sandybridge/raminit_common.c: https://review.coreboot.org/#/c/25664/1/src/northbridge/intel/sandybridge/r… PS1, Line 2362: cmdrate = MIN(DIV_ROUND_UP(ctrl->tCMD, ctrl->tCK) - 1, 1); As long as you can't prove that it'll work on any board (see comment above): No. I would accept cmdrate = MAX(cmdrage, DIV_ROUND_UP(ctrl->tCMD, ctrl->tCK)); Also please make sure that DIV_ROUND_UP(ctrl->tCMD, ctrl->tCK) never exceeds 2. https://review.coreboot.org/#/c/25664/1/src/northbridge/intel/sandybridge/r… File src/northbridge/intel/sandybridge/raminit_ivy.c: https://review.coreboot.org/#/c/25664/1/src/northbridge/intel/sandybridge/r… PS1, Line 485: ctrl->CWL = get_CWL(ctrl->tCK); why not MAX(get_CWL(ctrl->tCK), DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK)) ? -- To view, visit https://review.coreboot.org/25664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I634bed764d76345c27f02a2fae5abb2d81b38fd9 Gerrit-Change-Number: 25664 Gerrit-PatchSet: 1 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 14 Apr 2018 09:45:43 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: device/dram/ddr3: improve XMP support
by Patrick Rudolph (Code Review) 14 Apr '18

14 Apr '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/25663 ) Change subject: device/dram/ddr3: improve XMP support ...................................................................... Patch Set 1: (5 comments) https://review.coreboot.org/#/c/25663/1/src/device/dram/ddr3.c File src/device/dram/ddr3.c: https://review.coreboot.org/#/c/25663/1/src/device/dram/ddr3.c@298 PS1, Line 298: /* Minimum CAS Write Latency Time (tCWLmin) - not present in standard SPD */ over line https://review.coreboot.org/#/c/25663/1/src/device/dram/ddr3.c@491 PS1, Line 491: dimm->cas_supported = (xmp[4] << 8) + xmp[3]; According to spec 1.1 it's ((xmp[4] << 8) + xmp[3]) & 0x7fff https://review.coreboot.org/#/c/25663/1/src/device/dram/ddr3.c@515 PS1, Line 515: dimm->tCWL = xmp[5] * mtb;; Remove second semicolon https://review.coreboot.org/#/c/25663/1/src/device/dram/ddr3.c@516 PS1, Line 516: /* Minimum CMD rate */ "System CMD Rate Mode" https://review.coreboot.org/#/c/25663/1/src/include/device/dram/ddr3.h File src/include/device/dram/ddr3.h: https://review.coreboot.org/#/c/25663/1/src/include/device/dram/ddr3.h@166 PS1, Line 166: u32 tCMD; u16 should be sufficient -- To view, visit https://review.coreboot.org/25663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie4f545ed1df92c146be02f56fea0ca9037478649 Gerrit-Change-Number: 25663 Gerrit-PatchSet: 1 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 14 Apr 2018 09:30:46 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/octopus: Add Write Protect GPIO to cros_gpios
by build bot (Jenkins) (Code Review) 14 Apr '18

14 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25673 ) Change subject: mb/google/octopus: Add Write Protect GPIO to cros_gpios ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24389/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/70143/ : SUCCESS -- To view, visit https://review.coreboot.org/25673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iedd0057d6bdfd5a666ff282bc784f7b98e8c96e8 Gerrit-Change-Number: 25673 Gerrit-PatchSet: 1 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)google.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 14 Apr 2018 04:20:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Add Write Protect GPIO to cros_gpios
by Hannah Williams (Code Review) 14 Apr '18

14 Apr '18

Hannah Williams has uploaded this change for review. ( https://review.coreboot.org/25673 Change subject: mb/google/octopus: Add Write Protect GPIO to cros_gpios ...................................................................... mb/google/octopus: Add Write Protect GPIO to cros_gpios BUG=b:78009842 TEST= wpsw_cur in crossystem reads the correct gpio Change-Id: Iedd0057d6bdfd5a666ff282bc784f7b98e8c96e8 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- M src/mainboard/google/octopus/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/25673/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 8fe1205..bdf8529 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -299,6 +299,7 @@ } static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_SCC_NAME), }; const struct cros_gpio *__attribute__((weak)) variant_cros_gpios(size_t *num) -- To view, visit https://review.coreboot.org/25673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iedd0057d6bdfd5a666ff282bc784f7b98e8c96e8 Gerrit-Change-Number: 25673 Gerrit-PatchSet: 1 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Force LPC IO decode settings
by build bot (Jenkins) (Code Review) 14 Apr '18

14 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25668 ) Change subject: soc/intel/cannonlake: Force LPC IO decode settings ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24383/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/70136/ : SUCCESS -- To view, visit https://review.coreboot.org/25668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I72a40360ba67f443f24468f10504d8cfd0b099ca Gerrit-Change-Number: 25668 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 23:48:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Force LPC IO decode settings
by build bot (Jenkins) (Code Review) 14 Apr '18

14 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25668 ) Change subject: soc/intel/cannonlake: Force LPC IO decode settings ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/24382/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/70135/ : ABORTED -- To view, visit https://review.coreboot.org/25668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I72a40360ba67f443f24468f10504d8cfd0b099ca Gerrit-Change-Number: 25668 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 23:44:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Force LPC IO decode settings
by Lijian Zhao (Code Review) 14 Apr '18

14 Apr '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/25668 Change subject: soc/intel/cannonlake: Force LPC IO decode settings ...................................................................... soc/intel/cannonlake: Force LPC IO decode settings Force PCH LPC generic IO ranges are identical between PCH LPC pci config space and DMI PCR registers. Reference documentation from 570374 chapter 2.4.1. Bug=77944335 TEST=Boot up in OS in meowth board, using iotools to read LPC pci config space offset 0x84~0x90 and compare with values read from DMI PCR private register offset 0x2730~0x273c are identical. Change-Id: I72a40360ba67f443f24468f10504d8cfd0b099ca Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/lpc.c 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/25668/1 diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index c02d66e..9d3488a 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -30,6 +30,7 @@ #include <intelblocks/pcr.h> #include <reg_script.h> #include <soc/iomap.h> +#include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> @@ -68,6 +69,19 @@ } #if ENV_RAMSTAGE +static void soc_mirror_dmi_pcr_io_dec(void) +{ + /* Mirror these same settings in DMI PCR */ + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, + pci_read_config32(PCH_DEV_LPC, LPC_GEN1_DEC)); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, + pci_read_config32(PCH_DEV_LPC, LPC_GEN2_DEC)); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, + pci_read_config32(PCH_DEV_LPC, LPC_GEN3_DEC)); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, + pci_read_config32(PCH_DEV_LPC, LPC_GEN4_DEC)); +} + static void pch_enable_ioapic(const struct device *dev) { u32 reg32; @@ -202,6 +216,7 @@ setup_i8259(); i8259_configure_irq_trigger(9, 1); clock_gate_8254(dev); + soc_mirror_dmi_pcr_io_dec(); } /* Fill up LPC IO resource structure inside SoC directory */ -- To view, visit https://review.coreboot.org/25668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I72a40360ba67f443f24468f10504d8cfd0b099ca Gerrit-Change-Number: 25668 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: soc/intel/common: Adjust LPC Generic IO setup
by build bot (Jenkins) (Code Review) 14 Apr '18

14 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25667 ) Change subject: soc/intel/common: Adjust LPC Generic IO setup ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24381/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/70134/ : SUCCESS -- To view, visit https://review.coreboot.org/25667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I89f9bb70320f91b16c6084384c4a0a53ede3760c Gerrit-Change-Number: 25667 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 23:40:51 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/common: Adjust LPC Generic IO setup
by Lijian Zhao (Code Review) 14 Apr '18

14 Apr '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/25667 Change subject: soc/intel/common: Adjust LPC Generic IO setup ...................................................................... soc/intel/common: Adjust LPC Generic IO setup Check same IO ranges get programmed first, if so just skip it to avoid double programming. BUG=b:77944335 TEST=Boot up with mewoth board, and check serial log, there's no error message about "LPC: Cannot Open IO Window: ". Change-Id: I89f9bb70320f91b16c6084384c4a0a53ede3760c Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/common/block/lpc/lpc_lib.c 1 file changed, 18 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/25667/1 diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index aeac441..58b588e 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -65,7 +65,7 @@ void lpc_open_pmio_window(uint16_t base, uint16_t size) { - int lgir_reg_num; + int i, lgir_reg_num; uint32_t lgir_reg_offset, lgir, window_size, alignment; resource_t bridged_size, bridge_base; @@ -76,16 +76,6 @@ bridge_base = base; while (bridged_size < size) { - lgir_reg_num = find_unused_pmio_window(); - if (lgir_reg_num < 0) { - printk(BIOS_ERR, - "LPC: Cannot open IO window: %llx size %llx\n", - bridge_base, size - bridged_size); - printk(BIOS_ERR, "No more IO windows\n"); - return; - } - lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num); - /* Each IO range register can only open a 256-byte window. */ window_size = MIN(size, LPC_LGIR_MAX_WINDOW_SIZE); @@ -97,6 +87,23 @@ lgir = (bridge_base & LPC_LGIR_ADDR_MASK) | LPC_LGIR_EN; lgir |= ((window_size - 1) << 16) & LPC_LGIR_AMASK_MASK; + /* Skip programming if same range already programmed. */ + for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) { + if (lgir == pci_read_config32(PCH_DEV_LPC, + LPC_GENERIC_IO_RANGE(i))) + return; + } + + lgir_reg_num = find_unused_pmio_window(); + if (lgir_reg_num < 0) { + printk(BIOS_ERR, + "LPC: Cannot open IO window: %llx size %llx\n", + bridge_base, size - bridged_size); + printk(BIOS_ERR, "No more IO windows\n"); + return; + } + lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num); + pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir); printk(BIOS_DEBUG, -- To view, visit https://review.coreboot.org/25667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I89f9bb70320f91b16c6084384c4a0a53ede3760c Gerrit-Change-Number: 25667 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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coreboot-gerrit April 2018