Richard Spiegel has uploaded a new patch set (#2). ( https://review.coreboot.org/25665 )
Change subject: soc/amd/stoneyridge/northbridge.c: Fix bit definitions
......................................................................
soc/amd/stoneyridge/northbridge.c: Fix bit definitions
The latest public BKDG releases some previously undefined (reserved) bits.
Fix these definitions, including header file where they are defined.
BUG=b:77940747
TEST=Build and boot grunt.
Change-Id: Icb5334110248d7806421200a161fa3befefcea8a
Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com>
---
M src/soc/amd/stoneyridge/include/soc/northbridge.h
M src/soc/amd/stoneyridge/northbridge.c
2 files changed, 7 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/25665/2
--
To view, visit https://review.coreboot.org/25665
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Icb5334110248d7806421200a161fa3befefcea8a
Gerrit-Change-Number: 25665
Gerrit-PatchSet: 2
Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>
Dan Elkouby has posted comments on this change. ( https://review.coreboot.org/25660 )
Change subject: sb/intel/bd82x6x: re-init SPI after lockdown
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/25660/1/src/southbridge/intel/bd82x6x/lpc.c
File src/southbridge/intel/bd82x6x/lpc.c:
https://review.coreboot.org/#/c/25660/1/src/southbridge/intel/bd82x6x/lpc.c…
PS1, Line 865: spi_init();
> better add the same comment here then. […]
Done
--
To view, visit https://review.coreboot.org/25660
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Ib802d7ee32f1fb0a68a84b0280480dcaefa9831f
Gerrit-Change-Number: 25660
Gerrit-PatchSet: 1
Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Dan Elkouby <streetwalkermc(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Fri, 13 Apr 2018 20:21:52 +0000
Gerrit-HasComments: Yes
Gerrit-HasLabels: No
Hello Arthur Heymans, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/25660
to look at the new patch set (#2).
Change subject: sb/intel/bd82x6x: re-init SPI after lockdown
......................................................................
sb/intel/bd82x6x: re-init SPI after lockdown
SMM final locks the SPI BAR, which causes e.g. flashconsole to hang
Change-Id: Ib802d7ee32f1fb0a68a84b0280480dcaefa9831f
Signed-off-by: Dan Elkouby <streetwalkermc(a)gmail.com>
---
M src/southbridge/intel/bd82x6x/lpc.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/25660/2
--
To view, visit https://review.coreboot.org/25660
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ib802d7ee32f1fb0a68a84b0280480dcaefa9831f
Gerrit-Change-Number: 25660
Gerrit-PatchSet: 2
Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Dan Elkouby <streetwalkermc(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/25660 )
Change subject: sb/intel/bd82x6x: re-init SPI after lockdown
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/25660/1/src/southbridge/intel/bd82x6x/lpc.c
File src/southbridge/intel/bd82x6x/lpc.c:
https://review.coreboot.org/#/c/25660/1/src/southbridge/intel/bd82x6x/lpc.c…
PS1, Line 865: spi_init();
better add the same comment here then. "/* Re-init SPI driver to handle locked BAR */"
--
To view, visit https://review.coreboot.org/25660
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Ib802d7ee32f1fb0a68a84b0280480dcaefa9831f
Gerrit-Change-Number: 25660
Gerrit-PatchSet: 1
Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Dan Elkouby <streetwalkermc(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Fri, 13 Apr 2018 20:12:55 +0000
Gerrit-HasComments: Yes
Gerrit-HasLabels: Yes
Dan Elkouby has posted comments on this change. ( https://review.coreboot.org/25660 )
Change subject: sb/intel/bd82x6x: re-init SPI after lockdown
......................................................................
Patch Set 1:
I have, that doesn't help. SMM does this with CONFIG_SPI_FLASH_SMM=y, and it needs to be done in ramstage as well, regardless of that option.
--
To view, visit https://review.coreboot.org/25660
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Ib802d7ee32f1fb0a68a84b0280480dcaefa9831f
Gerrit-Change-Number: 25660
Gerrit-PatchSet: 1
Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com>
Gerrit-Reviewer: Dan Elkouby <streetwalkermc(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Comment-Date: Fri, 13 Apr 2018 19:52:55 +0000
Gerrit-HasComments: No
Gerrit-HasLabels: No