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Change in coreboot[master]: mb/google/kahlee: Select BT I2S PAD on ACP_BT_UART mux
by build bot (Jenkins) (Code Review)
14 Apr '18
14 Apr '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/25653
) Change subject: mb/google/kahlee: Select BT I2S PAD on ACP_BT_UART mux ...................................................................... Patch Set 3: Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/70119/
: SUCCESS -- To view, visit
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id76bfa1fa1dde904f02a03b0c15986ecb1bbcc97 Gerrit-Change-Number: 25653 Gerrit-PatchSet: 3 Gerrit-Owner: Akshu Agrawal <akshu.agrawal(a)amd.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 16:27:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No
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Change in coreboot[master]: soc/intel/cannonlake: Assign Cpu Mp PPI FSP upd to handle feature pro...
by build bot (Jenkins) (Code Review)
13 Apr '18
13 Apr '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/25657
) Change subject: soc/intel/cannonlake: Assign Cpu Mp PPI FSP upd to handle feature programming ...................................................................... Patch Set 2: Verified+1 Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/70117/
: SUCCESS -- To view, visit
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iae1984cfd81cbaecf24bb82229e48b9f36abd110 Gerrit-Change-Number: 25657 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 13:48:08 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes
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Change in coreboot[master]: vendorcode/amd/pi/00670F00: Remove unused headers
by build bot (Jenkins) (Code Review)
13 Apr '18
13 Apr '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/25644
) Change subject: vendorcode/amd/pi/00670F00: Remove unused headers ...................................................................... Patch Set 4: Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/70115/
: SUCCESS -- To view, visit
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I99b77f6ba41ded30122a01bbe709681312561436 Gerrit-Change-Number: 25644 Gerrit-PatchSet: 4 Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 13:14:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No
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Change in coreboot[master]: vendorcode/amd/pi/00670F00: Remove unused headers
by build bot (Jenkins) (Code Review)
13 Apr '18
13 Apr '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/25626
) Change subject: vendorcode/amd/pi/00670F00: Remove unused headers ...................................................................... Patch Set 2: Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/70114/
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic38424d489dcc37a4074159e33fca0d49c71f701 Gerrit-Change-Number: 25626 Gerrit-PatchSet: 2 Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 13:10:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No
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Change in coreboot[master]: soc/intel/cannonlake: Assign Cpu Mp PPI FSP upd to handle feature pro...
by build bot (Jenkins) (Code Review)
13 Apr '18
13 Apr '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/25657
) Change subject: soc/intel/cannonlake: Assign Cpu Mp PPI FSP upd to handle feature programming ...................................................................... Patch Set 1: Verified-1 Build Failed
https://qa.coreboot.org/job/coreboot-gerrit/70113/
: FAILURE
https://qa.coreboot.org/job/coreboot-checkpatch/24366/
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iae1984cfd81cbaecf24bb82229e48b9f36abd110 Gerrit-Change-Number: 25657 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 12:18:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes
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Change in coreboot[master]: soc/intel/common: Implement EFI_MP_SERVICES_PPI structure APIs
by build bot (Jenkins) (Code Review)
13 Apr '18
13 Apr '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/25634
) Change subject: soc/intel/common: Implement EFI_MP_SERVICES_PPI structure APIs ...................................................................... Patch Set 7: Verified+1 Build Successful
https://qa.coreboot.org/job/coreboot-checkpatch/24365/
: SUCCESS
https://qa.coreboot.org/job/coreboot-gerrit/70112/
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie844e3f15f759ea09a8f3fd24825ee740151c956 Gerrit-Change-Number: 25634 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 12:18:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes
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Change in coreboot[master]: soc/intel/cannonlake: Assign Cpu Mp PPI FSP upd to handle feature pro...
by Subrata Banik (Code Review)
13 Apr '18
13 Apr '18
Subrata Banik has uploaded this change for review. (
https://review.coreboot.org/25657
Change subject: soc/intel/cannonlake: Assign Cpu Mp PPI FSP upd to handle feature programming ...................................................................... soc/intel/cannonlake: Assign Cpu Mp PPI FSP upd to handle feature programming BRANCH=none BUG=b:74436746 TEST=Able to make call between FSP to Coreboot. Change-Id: Iae1984cfd81cbaecf24bb82229e48b9f36abd110 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/chip.c M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h 3 files changed, 32 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/25657/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 541e516..071d703 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -60,6 +60,7 @@ select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_PMC + select SOC_INTEL_COMMON_BLOCK_PUBLISH_MP_SERVICES_PPI select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SATA diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 5fc3a55..371b4ef 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -19,6 +19,11 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_PUBLISH_MP_SERVICES_PPI) +#include <intelblocks/mp_service_ppi.h> +#include <cpu/x86/mp.h> +#include <intelblocks/cpulib.h> +#endif #include <intelblocks/xdci.h> #include <romstage_handoff.h> #include <soc/intel/common/vbt.h> @@ -200,6 +205,10 @@ params->Usb3OverCurrentPin[i] = 0; } +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_PUBLISH_MP_SERVICES_PPI) + params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); +#endif + mainboard_silicon_init_params(params); /* Unlock upper 8 bytes of RTC RAM */ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h index 4daf891..14fa8cd 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h @@ -1093,22 +1093,25 @@ **/ UINT16 ImonSlope1[5]; -/** Offset 0x0324 - CPU VR Power Delivery Design - Used to communicate the power delivery design capability of the board. This value - is an enum of the available power delivery segments that are defined in the Platform - Design Guide. +/** Offset 0x0324 - CpuMpPpi + Pointer for CpuMpPpi **/ - UINT32 VrPowerDeliveryDesign; + UINT32 CpuMpPpi; -/** Offset 0x0328 - ReservedCpuPostMemProduction +/** Offset 0x0328 - CpuInitMpLibHob + Pointer for CpuInitMpLibHob +**/ + UINT32 CpuInitMpLibHob; + +/** Offset 0x032C - ReservedCpuPostMemProduction Reserved for CPU Post-Mem Production $EN_DIS **/ UINT8 ReservedCpuPostMemProduction[1]; -/** Offset 0x0329 +/** Offset 0x032D **/ - UINT8 UnusedUpdSpace10[29]; + UINT8 UnusedUpdSpace10[25]; /** Offset 0x0346 - Enable DMI ASPM Deprecated. @@ -1876,6 +1879,7 @@ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. + 0x1:None, 0x13:1kOhm WPU, 0x15:5kOhm WPU, 0x19:20kOhm WPU **/ UINT8 PchSerialIoI2cPadsTermination[6]; @@ -2154,17 +2158,9 @@ **/ UINT8 SataRstCpuAttachedStorage; -/** Offset 0x0752 - Enable 8254 Static Clock Gating On S3 - This is only applicable when Enable8254ClockGating is disabled. FSP will do the - 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This - avoids the SMI requirement for the programming. - $EN_DIS +/** Offset 0x0752 **/ - UINT8 Enable8254ClockGatingOnS3; - -/** Offset 0x0753 -**/ - UINT8 UnusedUpdSpace25; + UINT8 UnusedUpdSpace25[2]; /** Offset 0x0754 - Pch PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. This @@ -2297,7 +2293,7 @@ **/ UINT8 ChapDeviceEnable; -/** Offset 0x07B2 - Skip PAM register lock +/** Offset 0x07B2 - Skip PAM regsiter lock Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC $EN_DIS @@ -2480,7 +2476,7 @@ /** Offset 0x07DA - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature - target; <b>0: Disabled</b>; 1: Enabled. + target; 0: Disabled; <b>1: Enabled </b>. $EN_DIS **/ UINT8 TccOffsetLock; @@ -2844,10 +2840,9 @@ **/ UINT16 PsysPmax; -/** Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0 - Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF +/** Offset 0x0858 **/ - UINT16 CstateLatencyControl0Irtl; + UINT8 Reserved0[2]; /** Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1 Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF @@ -2894,13 +2889,13 @@ /** Offset 0x0870 - Package PL4 power limit Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 + Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit4; /** Offset 0x0874 - Tcc Offset Time Window for RATL Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 + Range 0 to 4095875 in Step size of 125 **/ UINT32 TccOffsetTimeWindowForRatl; @@ -3089,7 +3084,8 @@ UINT8 PchUnlockGpioPads; /** Offset 0x08C2 - PCH Unlock SBI access - Deprecated + This unlock the SBI lock bit to allow SBI after post time. 0: Lock SBI access; 1: + Unlock SBI access. $EN_DIS **/ UINT8 PchSbiUnlock; -- To view, visit
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iae1984cfd81cbaecf24bb82229e48b9f36abd110 Gerrit-Change-Number: 25657 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
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Change in coreboot[master]: intel/fsp_broadwell_de: Remove buggy code for SMBus clock gating
by build bot (Jenkins) (Code Review)
13 Apr '18
13 Apr '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/25652
) Change subject: intel/fsp_broadwell_de: Remove buggy code for SMBus clock gating ...................................................................... Patch Set 2: Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/70111/
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icb86f4516f8a6e72552a44618737e682b0fdef33 Gerrit-Change-Number: 25652 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 10:22:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No
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Change in coreboot[master]: mb/google/kahlee: Selects BT I2S PAD on ACP_BT_UART mux
by build bot (Jenkins) (Code Review)
13 Apr '18
13 Apr '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/25653
) Change subject: mb/google/kahlee: Selects BT I2S PAD on ACP_BT_UART mux ...................................................................... Patch Set 2: Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/70110/
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id76bfa1fa1dde904f02a03b0c15986ecb1bbcc97 Gerrit-Change-Number: 25653 Gerrit-PatchSet: 2 Gerrit-Owner: Akshu Agrawal <akshu.agrawal(a)amd.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 10:10:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No
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Change in coreboot[master]: mb/google/poppy/variants/nami: Add SPD file for Pantheon
by build bot (Jenkins) (Code Review)
13 Apr '18
13 Apr '18
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https://review.coreboot.org/25654
) Change subject: mb/google/poppy/variants/nami: Add SPD file for Pantheon ...................................................................... Patch Set 1: Verified+1 Build Successful
https://qa.coreboot.org/job/coreboot-checkpatch/24363/
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia44e70948e57c2f19664d874ae005ac39d748f92 Gerrit-Change-Number: 25654 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 09:13:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes
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