coreboot-gerrit April 2018

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Change in coreboot[master]: soc/intel/common: Implement EFI_MP_SERVICES_PPI structure APIs
by Subrata Banik (Code Review) 13 Apr '18

13 Apr '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/25634 to look at the new patch set (#6). Change subject: soc/intel/common: Implement EFI_MP_SERVICES_PPI structure APIs ...................................................................... soc/intel/common: Implement EFI_MP_SERVICES_PPI structure APIs This patch ensures to implement all required APIs for EFI_MP_SERVICES_PPI as per EDK2 UefiPkg Open source specification More details here: https://github.com/tianocore/edk2/blob/master/MdePkg/Include/Ppi/MpServices… Supported SOC will call fill mp_services structure so that FSP can install the required PPI based on coreboot published structure. BRANCH=none BUG=b:74436746 TEST=Able to publish MP service PPI in coreboot. Change-Id: Ie844e3f15f759ea09a8f3fd24825ee740151c956 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/Makefile.inc A src/soc/intel/common/block/cpu/mp_service_ppi.c A src/soc/intel/common/block/include/intelblocks/mp_service_ppi.h 4 files changed, 749 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/25634/6 -- To view, visit https://review.coreboot.org/25634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie844e3f15f759ea09a8f3fd24825ee740151c956 Gerrit-Change-Number: 25634 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: include/memory_info.h: Change part number field from 19 bytes to 21
by build bot (Jenkins) (Code Review) 13 Apr '18

13 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25650 ) Change subject: include/memory_info.h: Change part number field from 19 bytes to 21 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24358/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/70102/ : SUCCESS -- To view, visit https://review.coreboot.org/25650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I57aa8e06d907a1e6b11ce88f612a0d6c14b7c65b Gerrit-Change-Number: 25650 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 01:39:55 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: include/memory_info.h: Change part number field from 19 bytes to 21
by Richard Spiegel (Code Review) 13 Apr '18

13 Apr '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25650 Change subject: include/memory_info.h: Change part number field from 19 bytes to 21 ...................................................................... include/memory_info.h: Change part number field from 19 bytes to 21 DDR4 reserves 20 bytes for part number without termination. Therefor coreboot buffer for part number has to be increased to 21 bytes, to account termination. BUG=b:77943312 TEST=Build kahlee. Change-Id: I57aa8e06d907a1e6b11ce88f612a0d6c14b7c65b Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/include/memory_info.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/25650/1 diff --git a/src/include/memory_info.h b/src/include/memory_info.h index d26d789..c9554b8 100644 --- a/src/include/memory_info.h +++ b/src/include/memory_info.h @@ -20,7 +20,7 @@ #include <compiler.h> #define DIMM_INFO_SERIAL_SIZE 4 -#define DIMM_INFO_PART_NUMBER_SIZE 19 +#define DIMM_INFO_PART_NUMBER_SIZE 21 #define DIMM_INFO_TOTAL 8 /* Maximum num of dimm is 8 */ /** -- To view, visit https://review.coreboot.org/25650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I57aa8e06d907a1e6b11ce88f612a0d6c14b7c65b Gerrit-Change-Number: 25650 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: mb/google/kahlee/variants/baseboard/gpio.c: move all non-critical gpios
by build bot (Jenkins) (Code Review) 13 Apr '18

13 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25395 ) Change subject: mb/google/kahlee/variants/baseboard/gpio.c: move all non-critical gpios ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24337/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/70081/ : SUCCESS -- To view, visit https://review.coreboot.org/25395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icbc9370050d619800026035caaac3e89536a460a Gerrit-Change-Number: 25395 Gerrit-PatchSet: 5 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Thu, 12 Apr 2018 22:23:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/kahlee: Resume on AC insertion
by build bot (Jenkins) (Code Review) 13 Apr '18

13 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25647 ) Change subject: google/kahlee: Resume on AC insertion ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24338/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/70082/ : SUCCESS -- To view, visit https://review.coreboot.org/25647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4bcaef2fe75283aaa6260b5b9efd408ff4b05f4c Gerrit-Change-Number: 25647 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Apr 2018 22:23:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/kahlee: Resume on AC insertion
by Marshall Dawson (Code Review) 13 Apr '18

13 Apr '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/25647 Change subject: google/kahlee: Resume on AC insertion ...................................................................... google/kahlee: Resume on AC insertion The EC should wake the system from S3 when the AC connector is plugged. BUG=b:77602394 TEST=verify resume on insert with Grunt Change-Id: I4bcaef2fe75283aaa6260b5b9efd408ff4b05f4c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/25647/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h index e93c2dd..c915ca7 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h @@ -44,10 +44,11 @@ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) -/* EC can wake from S3 with lid or power button or key press */ +/* EC can wake from S3 with lid, power button, key press, or AC connect */ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)) /* Log EC wake events plus EC shutdown events */ #define MAINBOARD_EC_LOG_EVENTS \ -- To view, visit https://review.coreboot.org/25647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4bcaef2fe75283aaa6260b5b9efd408ff4b05f4c Gerrit-Change-Number: 25647 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd/common/block/pi/amd_late_init.c: Fix illegal memory access
by build bot (Jenkins) (Code Review) 13 Apr '18

13 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25419 ) Change subject: soc/amd/common/block/pi/amd_late_init.c: Fix illegal memory access ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24336/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/70080/ : SUCCESS -- To view, visit https://review.coreboot.org/25419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I18fa5e9c73401575441b6810f1db80d11666368c Gerrit-Change-Number: 25419 Gerrit-PatchSet: 3 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Apr 2018 21:45:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: vendorcode/amd/pi/00670F00/ remove headers
by build bot (Jenkins) (Code Review) 13 Apr '18

13 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25644 ) Change subject: vendorcode/amd/pi/00670F00/ remove headers ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70079/ : SUCCESS -- To view, visit https://review.coreboot.org/25644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I99b77f6ba41ded30122a01bbe709681312561436 Gerrit-Change-Number: 25644 Gerrit-PatchSet: 3 Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Apr 2018 20:55:54 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variants/nami: Update GPIOs
by build bot (Jenkins) (Code Review) 13 Apr '18

13 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25646 ) Change subject: mb/google/poppy/variants/nami: Update GPIOs ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24335/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/70078/ : SUCCESS -- To view, visit https://review.coreboot.org/25646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7d912f4bc6765f065c75c68a45bdf9ee844e0c1d Gerrit-Change-Number: 25646 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Apr 2018 20:55:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nami: Update GPIOs
by Shelley Chen (Code Review) 13 Apr '18

13 Apr '18

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/25646 Change subject: mb/google/poppy/variants/nami: Update GPIOs ...................................................................... mb/google/poppy/variants/nami: Update GPIOs Updating some GPIOs based on changes in the latest schematics BUG=b:73749640 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: I7d912f4bc6765f065c75c68a45bdf9ee844e0c1d Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/poppy/variants/nami/gpio.c 1 file changed, 61 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/25646/1 diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index 37a9420..229c4ee 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -50,8 +50,8 @@ PAD_CFG_NC(GPP_A16), /* A17 : SD_PWR_EN# ==> NC */ PAD_CFG_NC(GPP_A17), - /* A18 : ISH_GP0 ==> NC */ - PAD_CFG_NC(GPP_A18), + /* A18 : ISH_GP0 ==> EMMC_RST#L_R_SOC */ + PAD_CFG_GPO(GPP_A18, 1, DEEP), /* A19 : ISH_GP1 ==> NC */ PAD_CFG_NC(GPP_A19), /* A20 : ISH_GP2 ==> NC */ @@ -91,8 +91,8 @@ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST#_PCH */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - /* B14 : SPKR ==> NC */ - PAD_CFG_NC(GPP_B14), + /* B14 : SPKR ==> EC_GPP_B14 / PP3300_S */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP), /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ @@ -109,21 +109,21 @@ PAD_CFG_NC(GPP_B21), /* B22 : GSPI1_MOSI ==> NC(TP30) */ PAD_CFG_NC(GPP_B22), - /* B23 : SM1ALERT# ==> NC */ - PAD_CFG_NC(GPP_B23), + /* B23 : SM1ALERT# ==> SOC_SML1ALERT# */ + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), - /* C0 : SMBCLK ==> NC */ - PAD_CFG_NC(GPP_C0), - /* C1 : SMBDATA ==> NC */ - PAD_CFG_NC(GPP_C1), + /* C0 : SMBCLK ==> SOC_SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : SMBDATA ==> SOC_SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* C2 : SMBALERT# ==> NC(TP917) */ PAD_CFG_NC(GPP_C2), /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */ PAD_CFG_GPO(GPP_C3, 0, DEEP), /* C4 : SML0DATA ==> NC */ PAD_CFG_NC(GPP_C4), - /* C5 : SML0ALERT# ==> NC */ - PAD_CFG_NC(GPP_C5), + /* C5 : SML0ALERT# ==> SOC_SML0ALERT# */ + PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), /* C6 : SM1CLK ==> EC_IN_RW_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* C7 : SM1DATA ==> TRACKPAD_DISABLE# */ @@ -156,13 +156,13 @@ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), - /* C22 : UART2_RTS# ==> NC */ + /* C22 : UART2_RTS# ==> NC(TP926) */ PAD_CFG_NC(GPP_C22), /* C23 : UART2_CTS# ==> PCH_WP */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), - /* D0 : SPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_D0), + /* D0 : SPI1_CS# ==> DDR_CHB_EN */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_D0, NONE, DEEP), /* D1 : SPI1_CLK ==> PEN_IRQ# */ PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST), /* D2 : SPI1_MISO ==> PEN_PDCT# */ @@ -181,45 +181,47 @@ PAD_CFG_NC(GPP_D8), /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */ PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST), - /* D10 : ISH_SPI_CLK ==> NC(TP29) */ - PAD_CFG_NC(GPP_D10), - /* D11 : ISH_SPI_MISO ==> NC */ - PAD_CFG_NC(GPP_D11), - /* D12 : ISH_SPI_MOSI ==> NC */ - PAD_CFG_NC(GPP_D12), - /* D13 : ISH_UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_D13), - /* D14 : ISH_UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_D14), + /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), + /* D11 : ISH_SPI_MISO ==> DCI_CLK */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP), + /* D12 : ISH_SPI_MOSI ==> DCI_DATA */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP), + /* D13 : ISH_UART0_RXD ==> H1_BOOT_UART_RX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> H1_BOOT_UART_TX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* D15 : ISH_UART0_RTS# ==> NC */ PAD_CFG_NC(GPP_D15), /* D16 : ISH_UART0_CTS# ==> NC */ PAD_CFG_NC(GPP_D16), - /* D18 : DMIC_DATA1 ==> SOC_DMIC_DATA1 */ + /* D17 : DMIC_DATA1 ==> SOC_DMIC_CLK1_R */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* D18 : DMIC_DATA1 ==> SOC_DMIC_DATA1_R */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), - /* D19 : DMIC_CLK0 ==> SOC_DMIC_CLK0 */ + /* D19 : DMIC_CLK0 ==> SOC_DMIC_CLK0_R */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), - /* D20 : DMIC_DATA0 ==> SOC_DMIC_DATA0 */ + /* D20 : DMIC_DATA0 ==> SOC_DMIC_DATA0_R */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), - /* D21 : SPI1_IO2 ==> NC */ - PAD_CFG_NC(GPP_D21), + /* D21 : SPI1_IO2 ==> DDR_CHA_EN */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_D21, NONE, DEEP), /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */ PAD_CFG_GPO(GPP_D22, 1, DEEP), - /* D23 : I2S_MCLK ==> NC */ + /* D23 : I2S_MCLK ==> I2S_1_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> PEN_EJECT_ODL - for wake event */ PAD_CFG_GPI_ACPI_SCI(GPP_E1, NONE, DEEP, NONE), - /* E2 : SATAXPCIE2 ==> NC(TP916) */ - PAD_CFG_NC(GPP_E2), + /* E2 : SATAXPCIE2 ==> WLAN_OFF# */ + PAD_CFG_GPO(GPP_E2, 0, DEEP), /* E3 : CPU_GP0 ==> TRACKPAD_INT# */ PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST), /* E4 : SATA_DEVSLP0 ==> NC(TP914) */ PAD_CFG_NC(GPP_E4), - /* E5 : SATA_DEVSLP1 ==> DEVSLP1 */ - PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 ==> NC(TP928) */ + PAD_CFG_NC(GPP_E5), /* E6 : SATA_DEVSLP2 ==> NC(TP915) */ PAD_CFG_NC(GPP_E6), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT# */ @@ -238,10 +240,10 @@ PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */ PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), - /* E15 : DDPD_HPD2 ==> PCH_MEM_CONFIG4 */ + /* E15 : DDPD_HPD2 ==> DDR_SEL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), - /* E16 : DDPE_HPD3 ==> PCH_GPP_E16 */ - PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, INVERT), + /* E16 : DDPE_HPD3 ==> TRACKPAD_INT# */ + PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, INVERT), /* E17 : EDP_HPD ==> EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> SOC_DP1_CTRL_CLK */ @@ -254,15 +256,15 @@ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* E22 : DDPD_CTRLCLK ==> WLAN_PCIE_WAKE# */ PAD_CFG_GPI_ACPI_SCI(GPP_E22, NONE, DEEP, INVERT), - /* E23 : DDPD_CTRLDATA ==> NC */ + /* E23 : DDPD_CTRLDATA ==> NC(TP17)*/ PAD_CFG_NC(GPP_E23), /* The next 4 pads are for bit banging the amplifiers, default to I2S */ - /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */ + /* F0 : I2S2_SCLK ==> I2S2_2_BCLK_R */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), - /* F1 : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */ + /* F1 : I2S2_SFRM ==> I2S2_2_FS_LRC */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), - /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */ + /* F2 : I2S2_TXD ==> I2S2_2_TX_DAC */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ PAD_CFG_NC(GPP_F3), @@ -274,35 +276,35 @@ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), /* F7 : I2C3_SCL ==> I2C_3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), - /* F8 : I2C4_SDA ==> NC */ - PAD_CFG_NC(GPP_F8), - /* F9 : I2C4_SCL ==> NC */ - PAD_CFG_NC(GPP_F9), + /* F8 : I2C4_SDA ==> I2C_4_SDA */ + PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), + /* F9 : I2C4_SCL ==> I2C_4_SCL */ + PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* F10 : I2C5_SDA ==> NC */ PAD_CFG_NC(GPP_F10), /* F11 : I2C5_SCL ==> NC */ PAD_CFG_NC(GPP_F11), - /* F12 : EMMC_CMD ==> EMMC_CMD */ + /* F12 : EMMC_CMD ==> EMMC_1_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - /* F13 : EMMC_DATA0 ==> EMMC_DATA0 */ + /* F13 : EMMC_DATA0 ==> EMMC_1_D0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - /* F14 : EMMC_DATA1 ==> EMMC_DATA1 */ + /* F14 : EMMC_DATA1 ==> EMMC_1_D1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), - /* F15 : EMMC_DATA2 ==> EMMC_DATA2 */ + /* F15 : EMMC_DATA2 ==> EMMC_1_D2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - /* F16 : EMMC_DATA3 ==> EMMC_DATA3 */ + /* F16 : EMMC_DATA3 ==> EMMC_1_D3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - /* F17 : EMMC_DATA4 ==> EMMC_DATA4 */ + /* F17 : EMMC_DATA4 ==> EMMC_1_D4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), - /* F18 : EMMC_DATA5 ==> EMMC_DATA5 */ + /* F18 : EMMC_DATA5 ==> EMMC_1_D5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), - /* F19 : EMMC_DATA6 ==> EMMC_DATA6 */ + /* F19 : EMMC_DATA6 ==> EMMC_1_D6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* F20 : EMMC_DATA7 ==> EMMC_DATA7 */ + /* F20 : EMMC_DATA7 ==> EMMC_1_D7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - /* F21 : EMMC_RCLK ==> EMMC_RCLK */ + /* F21 : EMMC_RCLK ==> EMMC_1_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - /* F22 : EMMC_CLK ==> EMMC_CLK */ + /* F22 : EMMC_CLK ==> EMMC_1_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ PAD_CFG_NC(GPP_F23), @@ -321,8 +323,8 @@ PAD_CFG_NC(GPP_G5), /* G6 : SD_CLK ==> NC */ PAD_CFG_NC(GPP_G6), - /* G7 : SD_WP ==> NC */ - PAD_CFG_NC(GPP_G7), + /* G7 : SD_WP ==> SD_WP */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_G7, NONE, DEEP), /* GPD0: BATLOW# ==> PCH_BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/25646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7d912f4bc6765f065c75c68a45bdf9ee844e0c1d Gerrit-Change-Number: 25646 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com>

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coreboot-gerrit April 2018