coreboot-gerrit April 2018

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Change in coreboot[master]: sb/intel/bd82x6x: re-init SPI after lockdown
by Arthur Heymans (Code Review) 14 Apr '18

14 Apr '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/25660 ) Change subject: sb/intel/bd82x6x: re-init SPI after lockdown ...................................................................... Patch Set 1: Have you tried CONFIG_SPI_FLASH_SMM=y? that enables a spi_init call in smm? -- To view, visit https://review.coreboot.org/25660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib802d7ee32f1fb0a68a84b0280480dcaefa9831f Gerrit-Change-Number: 25660 Gerrit-PatchSet: 1 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 13 Apr 2018 19:50:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/asus/p5qpl-am: Add support for ASUS P5QPL-AM
by Arthur Heymans (Code Review) 14 Apr '18

14 Apr '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/25659 ) Change subject: mb/asus/p5qpl-am: Add support for ASUS P5QPL-AM ...................................................................... Patch Set 1: (8 comments) Looks ok but there are a few thing to check that can be mainboard specific. https://review.coreboot.org/#/c/25659/1/src/mainboard/asus/p5qpl-am/acpi/ic… File src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl: https://review.coreboot.org/#/c/25659/1/src/mainboard/asus/p5qpl-am/acpi/ic… PS1, Line 20: This is mainboard dependent. Please check this in vendor DSDT or schematics if you're lucky enough to find those. https://review.coreboot.org/#/c/25659/1/src/mainboard/asus/p5qpl-am/devicet… File src/mainboard/asus/p5qpl-am/devicetree.cb: https://review.coreboot.org/#/c/25659/1/src/mainboard/asus/p5qpl-am/devicet… PS1, Line 59: device pci 1c.3 off end # PCIe 4 Better be complete and add 1c.4, 1c.5 off too. (does not matter with this code though) https://review.coreboot.org/#/c/25659/1/src/mainboard/asus/p5qpl-am/devicet… PS1, Line 75: device pci 1e.0 on end # PCI bridge add device pci 1e.2 off end and device pci 1e.3 off end please (Those are disabled in romstage but better be complete) https://review.coreboot.org/#/c/25659/1/src/mainboard/asus/p5qpl-am/devicet… PS1, Line 127: # W83115RG-965 you sure your device has this? https://review.coreboot.org/#/c/25659/1/src/mainboard/asus/p5qpl-am/hda_ver… File src/mainboard/asus/p5qpl-am/hda_verb.c: https://review.coreboot.org/#/c/25659/1/src/mainboard/asus/p5qpl-am/hda_ver… PS1, Line 16: could be different on this mainboard: please check /proc/asound/card0/codec# https://review.coreboot.org/#/c/25659/1/src/mainboard/asus/p5qpl-am/romstag… File src/mainboard/asus/p5qpl-am/romstage.c: https://review.coreboot.org/#/c/25659/1/src/mainboard/asus/p5qpl-am/romstag… PS1, Line 24: #include <superio/nuvoton/nct6776/nct6776.h> remove https://review.coreboot.org/#/c/25659/1/src/mainboard/asus/p5qpl-am/romstag… PS1, Line 27: #include <superio/nuvoton/common/nuvoton.h> remove https://review.coreboot.org/#/c/25659/1/src/mainboard/asus/p5qpl-am/romstag… PS1, Line 113: remove newline -- To view, visit https://review.coreboot.org/25659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I160f9201e812f44ef9842caef851750fb7690c9e Gerrit-Change-Number: 25659 Gerrit-PatchSet: 1 Gerrit-Owner: AndiR <andir(a)memeware.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 13 Apr 2018 19:42:50 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: autoport: add missing PCIIDs
by build bot (Jenkins) (Code Review) 14 Apr '18

14 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25661 ) Change subject: autoport: add missing PCIIDs ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24374/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/70126/ : SUCCESS -- To view, visit https://review.coreboot.org/25661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9fce9a35174b5120f67c2345a0807db1b843eb48 Gerrit-Change-Number: 25661 Gerrit-PatchSet: 1 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 19:15:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/sandybridge: support more XMP timings
by build bot (Jenkins) (Code Review) 14 Apr '18

14 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25664 ) Change subject: nb/intel/sandybridge: support more XMP timings ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/70129/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/24377/ : SUCCESS -- To view, visit https://review.coreboot.org/25664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I634bed764d76345c27f02a2fae5abb2d81b38fd9 Gerrit-Change-Number: 25664 Gerrit-PatchSet: 1 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 19:13:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: device/dram/ddr3: improve XMP support
by build bot (Jenkins) (Code Review) 14 Apr '18

14 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25663 ) Change subject: device/dram/ddr3: improve XMP support ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/70128/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/24376/ : SUCCESS -- To view, visit https://review.coreboot.org/25663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie4f545ed1df92c146be02f56fea0ca9037478649 Gerrit-Change-Number: 25663 Gerrit-PatchSet: 1 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 19:13:27 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: sb/intel/bd82x6x: re-init SPI after lockdown
by build bot (Jenkins) (Code Review) 14 Apr '18

14 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25660 ) Change subject: sb/intel/bd82x6x: re-init SPI after lockdown ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24375/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/70127/ : SUCCESS -- To view, visit https://review.coreboot.org/25660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib802d7ee32f1fb0a68a84b0280480dcaefa9831f Gerrit-Change-Number: 25660 Gerrit-PatchSet: 1 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 19:13:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/asus/p8z77-v_pro: Add ASUS P8Z77-V Pro
by Dan Elkouby (Code Review) 14 Apr '18

14 Apr '18

Dan Elkouby has posted comments on this change. ( https://review.coreboot.org/25662 ) Change subject: mb/asus/p8z77-v_pro: Add ASUS P8Z77-V Pro ...................................................................... Patch Set 1: This change depends on I491aa32a3ec954be87a474478609f0f3971d0fdf and I05f9789bc14db56d2ac085f4f14047d80c3aefb5 for the ASMedia SATA controller -- To view, visit https://review.coreboot.org/25662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I10baf73a848576a0ce7e18c6b36bcd605f80b211 Gerrit-Change-Number: 25662 Gerrit-PatchSet: 1 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 19:11:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/asus/p8z77-v_pro: Add ASUS P8Z77-V Pro
by build bot (Jenkins) (Code Review) 14 Apr '18

14 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25662 ) Change subject: mb/asus/p8z77-v_pro: Add ASUS P8Z77-V Pro ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/70125/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/24373/ : SUCCESS -- To view, visit https://review.coreboot.org/25662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I10baf73a848576a0ce7e18c6b36bcd605f80b211 Gerrit-Change-Number: 25662 Gerrit-PatchSet: 1 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 19:09:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/asrock/g41c-gs: Add the revision 1 variant
by build bot (Jenkins) (Code Review) 14 Apr '18

14 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21292 ) Change subject: mb/asrock/g41c-gs: Add the revision 1 variant ...................................................................... Patch Set 16: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70124/ : SUCCESS -- To view, visit https://review.coreboot.org/21292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib69c2ac0a9dc1b5c46220d2d2d5239edc99b0516 Gerrit-Change-Number: 21292 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: AndiR <andir(a)memeware.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Apr 2018 19:09:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/sandybridge: support more XMP timings
by Dan Elkouby (Code Review) 14 Apr '18

14 Apr '18

Dan Elkouby has uploaded this change for review. ( https://review.coreboot.org/25664 Change subject: nb/intel/sandybridge: support more XMP timings ...................................................................... nb/intel/sandybridge: support more XMP timings Change-Id: I634bed764d76345c27f02a2fae5abb2d81b38fd9 Signed-off-by: Dan Elkouby <streetwalkermc(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_ivy.c M src/northbridge/intel/sandybridge/raminit_sandy.c 4 files changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/25664/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 0a44220..d62927c 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -160,6 +160,8 @@ ctrl->tWTR = MAX(ctrl->tWTR, dimm->tWTR); ctrl->tRTP = MAX(ctrl->tRTP, dimm->tRTP); ctrl->tFAW = MAX(ctrl->tFAW, dimm->tFAW); + ctrl->tCWL = MAX(ctrl->tCWL, dimm->tCWL); + ctrl->tCMD = MAX(ctrl->tCMD, dimm->tCMD); } if (!ctrl->cas_supported) @@ -2356,6 +2358,8 @@ * Try command rate 1T and 2T */ cmdrate = ((ctrl->rankmap[channel] & 0x5) == 0x5); + if (ctrl->tCMD) + cmdrate = MIN(DIV_ROUND_UP(ctrl->tCMD, ctrl->tCK) - 1, 1); for (; cmdrate < 2; cmdrate++) { err = try_cmd_stretch(ctrl, channel, cmdrate << 1); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index ab6e592..1f32dcd 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -94,6 +94,8 @@ u32 tWTR; u32 tRTP; u32 tFAW; + u32 tCWL; + u32 tCMD; /* Latencies in terms of clock cycles * They are saved separately as they are needed for DRAM MRS commands*/ u8 CAS; /* CAS read latency */ diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 675ac71..19dea2f 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -479,7 +479,10 @@ /* DLL_CONFIG_MDLL_W_TIMER */ ctrl->reg_5064b0 = (128000 / ctrl->tCK) + 3; - ctrl->CWL = get_CWL(ctrl->tCK); + if (ctrl->tCWL) + ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK); + else + ctrl->CWL = get_CWL(ctrl->tCK); printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); /* Find tRCD */ diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c index 3acc563..99c107e 100644 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -251,7 +251,10 @@ /* DLL_CONFIG_MDLL_W_TIMER */ ctrl->reg_5064b0 = (128000 / ctrl->tCK) + 3; - ctrl->CWL = get_CWL(ctrl->tCK); + if (ctrl->tCWL) + ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK); + else + ctrl->CWL = get_CWL(ctrl->tCK); printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); /* Find tRCD */ -- To view, visit https://review.coreboot.org/25664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I634bed764d76345c27f02a2fae5abb2d81b38fd9 Gerrit-Change-Number: 25664 Gerrit-PatchSet: 1 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com>

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coreboot-gerrit April 2018