coreboot-gerrit March 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/poppy: Config GPIO for DMIC by different sku id
by build bot (Jenkins) (Code Review) 15 Mar '18

15 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25148 ) Change subject: mb/google/poppy: Config GPIO for DMIC by different sku id ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/68570/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/22970/ : SUCCESS -- To view, visit https://review.coreboot.org/25148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic6570703f6ab4a1b03cbba8370fc0f597ab6bcf2 Gerrit-Change-Number: 25148 Gerrit-PatchSet: 3 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: luke yang <luke_yang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 15 Mar 2018 09:29:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/gitconfig: support pre-v2.5.0 git
by build bot (Jenkins) (Code Review) 15 Mar '18

15 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24981 ) Change subject: util/gitconfig: support pre-v2.5.0 git ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22969/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68569/ : SUCCESS -- To view, visit https://review.coreboot.org/24981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I232499c51e30bee546994eedcd2534642cd534e6 Gerrit-Change-Number: 24981 Gerrit-PatchSet: 3 Gerrit-Owner: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Reviewer: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Thu, 15 Mar 2018 06:29:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array
by build bot (Jenkins) (Code Review) 15 Mar '18

15 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25186 ) Change subject: soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68568/ : SUCCESS -- To view, visit https://review.coreboot.org/25186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Gerrit-Change-Number: 25186 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Mar 2018 04:54:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake: Add config option for enabling hotplug
by build bot (Jenkins) (Code Review) 15 Mar '18

15 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25187 ) Change subject: soc/intel/apollolake: Add config option for enabling hotplug ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/68565/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/22968/ : SUCCESS -- To view, visit https://review.coreboot.org/25187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I572c054d31aaf5d43a79c4b1773ec9356da48d9d Gerrit-Change-Number: 25187 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Mar 2018 04:52:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake: Add config option for enabling hotplug
by build bot (Jenkins) (Code Review) 15 Mar '18

15 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25187 ) Change subject: soc/intel/apollolake: Add config option for enabling hotplug ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68567/ : SUCCESS -- To view, visit https://review.coreboot.org/25187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I572c054d31aaf5d43a79c4b1773ec9356da48d9d Gerrit-Change-Number: 25187 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Mar 2018 04:52:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array
by build bot (Jenkins) (Code Review) 15 Mar '18

15 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25186 ) Change subject: soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/22967/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/68566/ : ABORTED -- To view, visit https://review.coreboot.org/25186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Gerrit-Change-Number: 25186 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Mar 2018 04:48:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake: Add config option for enabling hotplug
by Furquan Shaikh (Code Review) 15 Mar '18

15 Mar '18

Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/25187 ) Change subject: soc/intel/apollolake: Add config option for enabling hotplug ...................................................................... soc/intel/apollolake: Add config option for enabling hotplug PcieRpHotPlug in apollolake UPD is default enabled. This change adds a config option to enable hotplug only if explicitly requested by mainboard. This changes the default behavior on all apollolake boards to have hotplug disabled. BUG=b:74633273 BRANCH=reef,coral Change-Id: I572c054d31aaf5d43a79c4b1773ec9356da48d9d Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/25187/2 -- To view, visit https://review.coreboot.org/25187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I572c054d31aaf5d43a79c4b1773ec9356da48d9d Gerrit-Change-Number: 25187 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array
by Furquan Shaikh (Code Review) 15 Mar '18

15 Mar '18

Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/25186 ) Change subject: soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array ...................................................................... soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ# from mainboards instead of defining a separate property for each root port. This allows us to use memcpy to copy the entire array into FSP params as well as new properties for PCIe root ports can be added as arrays in future CLs. BUG=b:74633273 BRANCH=reef,coral Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/reef/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/coral/devicetree.cb M src/mainboard/google/reef/variants/pyro/devicetree.cb M src/mainboard/google/reef/variants/sand/devicetree.cb M src/mainboard/google/reef/variants/snappy/devicetree.cb M src/mainboard/intel/apollolake_rvp/devicetree.cb M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/leafhill/devicetree.cb M src/mainboard/intel/minnow3/devicetree.cb M src/mainboard/siemens/mc_apl1/devicetree.cb M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 12 files changed, 64 insertions(+), 72 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/25186/2 -- To view, visit https://review.coreboot.org/25186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Gerrit-Change-Number: 25186 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/apollolake: Add config option for enabling hotplug
by Furquan Shaikh (Code Review) 15 Mar '18

15 Mar '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/25187 Change subject: soc/intel/apollolake: Add config option for enabling hotplug ...................................................................... soc/intel/apollolake: Add config option for enabling hotplug PcieRpHotPlug in apollolake UPD is default enabled. This change adds a config option to enable hotplug only if explicitly requested by mainboard. This changes the default behavior on all apollolake boards to have hotplug disabled. BUG=b:74633273 Change-Id: I572c054d31aaf5d43a79c4b1773ec9356da48d9d Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/25187/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 6006773..af145c0 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -534,6 +534,9 @@ memcpy(silconfig->PcieRpClkReqNumber, cfg->pcie_rp_clkreq_pin, sizeof(silconfig->PcieRpClkReqNumber)); + memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable, + sizeof(silconfig->PcieRpHotPlug)); + if (cfg->emmc_tx_cmd_cntl != 0) silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl; if (cfg->emmc_tx_data_cntl1 != 0) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 7a1d16a..fe845ab 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -46,6 +46,9 @@ */ uint8_t pcie_rp_clkreq_pin[MAX_PCIE_PORTS]; + /* Enable/disable hot-plug for root ports (0 = disable, 1 = enable). */ + uint8_t pcie_rp_hotplug_enable[MAX_PCIE_PORTS]; + /* [14:8] DDR mode Number of dealy elements.Each = 125pSec. * [6:0] SDR mode Number of dealy elements.Each = 125pSec. */ -- To view, visit https://review.coreboot.org/25187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I572c054d31aaf5d43a79c4b1773ec9356da48d9d Gerrit-Change-Number: 25187 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array
by Furquan Shaikh (Code Review) 15 Mar '18

15 Mar '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/25186 Change subject: soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array ...................................................................... soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ# from mainboards instead of defining a separate property for each root port. This allows us to use memcpy to copy the entire array into FSP params as well as new properties for PCIe root ports can be added as arrays in future CLs. BUG=b:74633273 Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/reef/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/coral/devicetree.cb M src/mainboard/google/reef/variants/pyro/devicetree.cb M src/mainboard/google/reef/variants/sand/devicetree.cb M src/mainboard/google/reef/variants/snappy/devicetree.cb M src/mainboard/intel/apollolake_rvp/devicetree.cb M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/leafhill/devicetree.cb M src/mainboard/intel/minnow3/devicetree.cb M src/mainboard/siemens/mc_apl1/devicetree.cb M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 12 files changed, 64 insertions(+), 72 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/25186/1 diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 0f11f63..a8e24cd 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -4,13 +4,13 @@ device lapic 0 on end end - register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports - register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" # GPIO for PERST_0 # If the Board has PERST_0 signal, assign the GPIO diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index 0a06c76..c1b7067 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -4,13 +4,13 @@ device lapic 0 on end end - register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports - register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" # GPIO for PERST_0 # If the Board has PERST_0 signal, assign the GPIO diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 5bfe2c2..cb297d9 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -4,13 +4,13 @@ device lapic 0 on end end - register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports - register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" # GPIO for PERST_0 # If the Board has PERST_0 signal, assign the GPIO diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index a6692e6..e53af88 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -4,13 +4,13 @@ device lapic 0 on end end - register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports - register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" # GPIO for PERST_0 # If the Board has PERST_0 signal, assign the GPIO diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 6adf94c..9719368 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -4,13 +4,13 @@ device lapic 0 on end end - register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports - register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" # GPIO for PERST_0 # If the Board has PERST_0 signal, assign the GPIO diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb index 746aaf3..f7e82a0 100644 --- a/src/mainboard/intel/apollolake_rvp/devicetree.cb +++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb @@ -1,11 +1,11 @@ chip soc/intel/apollolake - register "pcie_rp0_clkreq_pin" = "2" # PCIe slot 2 - register "pcie_rp1_clkreq_pin" = "3" # Wifi+BT M2 slot - register "pcie_rp2_clkreq_pin" = "0" # PCIe slot 1 - register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[0]" = "2" # PCIe slot 2 + register "pcie_rp_clkreq_pin[1]" = "3" # Wifi+BT M2 slot + register "pcie_rp_clkreq_pin[2]" = "0" # PCIe slot 1 + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 45badcd..5a54430 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -4,13 +4,13 @@ device lapic 0 on end end - register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" # Disable unused clkreq of PCIe root ports - register "pcie_rp1_clkreq_pin" = "3" # wifi/bt - register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp4_clkreq_pin" = "1" - register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "3" # wifi/bt + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "1" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" # GPIO for PERST_0 # If the Board has PERST_0 signal, assign the GPIO diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb index 2a284d2..6c872b1 100644 --- a/src/mainboard/intel/leafhill/devicetree.cb +++ b/src/mainboard/intel/leafhill/devicetree.cb @@ -1,11 +1,11 @@ chip soc/intel/apollolake - register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb index 2a284d2..6c872b1 100644 --- a/src/mainboard/intel/minnow3/devicetree.cb +++ b/src/mainboard/intel/minnow3/devicetree.cb @@ -1,11 +1,11 @@ chip soc/intel/apollolake - register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/siemens/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/devicetree.cb index e2b6cee..c1ef76b 100644 --- a/src/mainboard/siemens/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/devicetree.cb @@ -7,12 +7,12 @@ register "sci_irq" = "SCIS_IRQ10" # Disable unused clkreq of PCIe root ports - register "pcie_rp0_clkreq_pin" = "3" # PCIe-PCI-Bridge - register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp2_clkreq_pin" = "0" # MACPHY - register "pcie_rp3_clkreq_pin" = "1" # MACPHY - register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY + register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" # EMMC TX DATA Delay 1 # Refer to EDS-Vol2-22.3. diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 53ffdb9..6006773 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -531,12 +531,8 @@ /* Parse device tree and disable unused device*/ parse_devicetree(silconfig); - silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin; - silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin; - silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin; - silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin; - silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; - silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; + memcpy(silconfig->PcieRpClkReqNumber, cfg->pcie_rp_clkreq_pin, + sizeof(silconfig->PcieRpClkReqNumber)); if (cfg->emmc_tx_cmd_cntl != 0) silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 8573cf4..7a1d16a 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -28,6 +28,7 @@ #include <soc/pm.h> #include <soc/usb.h> +#define MAX_PCIE_PORTS 6 #define CLKREQ_DISABLED 0xf #define APOLLOLAKE_I2C_DEV_MAX 8 @@ -43,12 +44,7 @@ * four CLKREQ inputs, but six root ports. Root ports without an * associated CLKREQ signal must be marked with "CLKREQ_DISABLED" */ - uint8_t pcie_rp0_clkreq_pin; - uint8_t pcie_rp1_clkreq_pin; - uint8_t pcie_rp2_clkreq_pin; - uint8_t pcie_rp3_clkreq_pin; - uint8_t pcie_rp4_clkreq_pin; - uint8_t pcie_rp5_clkreq_pin; + uint8_t pcie_rp_clkreq_pin[MAX_PCIE_PORTS]; /* [14:8] DDR mode Number of dealy elements.Each = 125pSec. * [6:0] SDR mode Number of dealy elements.Each = 125pSec. -- To view, visit https://review.coreboot.org/25186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Gerrit-Change-Number: 25186 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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coreboot-gerrit March 2018