coreboot-gerrit March 2018

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Change in coreboot[master]: mb/intel/kblrvp8: Add KBLRVP8 support
by V Sowmya (Code Review) 15 Mar '18

15 Mar '18

Hello Naresh Solanki, Balaji Manigandan, Gaggery Tsai, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/25194 to look at the new patch set (#2). Change subject: mb/intel/kblrvp8: Add KBLRVP8 support ...................................................................... mb/intel/kblrvp8: Add KBLRVP8 support Add the config for setting SPD DIMM size to 512 bytes for KBLRVP8 with DDR4 memory. Configure the channel 1 DIMM0 and DIMM1 memory SPD data. Set the UserBd UPD to BOARD_TYPE_DESKTOP for kblrvp8. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I985968d331991884050c3920ec9798cd4cb371c7 --- M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kblrvp/romstage.c 2 files changed, 12 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/25194/2 -- To view, visit https://review.coreboot.org/25194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I985968d331991884050c3920ec9798cd4cb371c7 Gerrit-Change-Number: 25194 Gerrit-PatchSet: 2 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/intel/kblrvp8:[WIP] Add KBLRVP8 support
by build bot (Jenkins) (Code Review) 15 Mar '18

15 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25194 ) Change subject: mb/intel/kblrvp8:[WIP] Add KBLRVP8 support ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22988/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68590/ : SUCCESS -- To view, visit https://review.coreboot.org/25194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I985968d331991884050c3920ec9798cd4cb371c7 Gerrit-Change-Number: 25194 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Mar 2018 16:23:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge: Create a HALT_THIS_AP callout
by build bot (Jenkins) (Code Review) 15 Mar '18

15 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24999 ) Change subject: soc/amd/stoneyridge: Create a HALT_THIS_AP callout ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22987/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68589/ : SUCCESS -- To view, visit https://review.coreboot.org/24999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I05ee405812211d93dfdbdc5ee7d9978c2eb585e1 Gerrit-Change-Number: 24999 Gerrit-PatchSet: 9 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Mar 2018 16:19:08 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/intel/kblrvp8:[WIP] Add KBLRVP8 support
by V Sowmya (Code Review) 15 Mar '18

15 Mar '18

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/25194 Change subject: mb/intel/kblrvp8:[WIP] Add KBLRVP8 support ...................................................................... mb/intel/kblrvp8:[WIP] Add KBLRVP8 support Add the config for setting SPD DIMM size to 512 bytes for KBLRVP8 with DDR4 memory. Configure the channel 1 DIMM0 and DIMM1 memory SPD data. Set the UserBd UPD to BOARD_TYPE_DESKTOP. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I985968d331991884050c3920ec9798cd4cb371c7 --- M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kblrvp/romstage.c 2 files changed, 12 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/25194/1 diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 5ca46e1..bbeb129 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -98,4 +98,7 @@ hex default 0xd00 +config DIMM_SPD_SIZE + int + default 512 if BOARD_INTEL_KBLRVP8 #DDR4 endif diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index 7bfbe1c..558c0be 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -49,7 +49,7 @@ mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); /* Memory leak is ok since we have memory mapped boot media */ mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); - } else { /* for CONFIG_BOARD_INTEL_KBLRVP7 */ + } else { /* CONFIG_BOARD_INTEL_KBLRVP7 and CONFIG_BOARD_INTEL_KBLRVP8*/ struct spd_block blk = { .addr_map = { 0x50, 0x51, 0x52, 0x53, }, }; @@ -58,8 +58,14 @@ get_spd_smbus(&blk); mem_cfg->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdPtr00 = (u32)blk.spd_array[0]; - } - mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + mem_cfg->MemorySpdPtr01 = (u32)blk.spd_array[1]; + if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) { + mem_cfg->MemorySpdPtr10 = (u32)blk.spd_array[2]; + mem_cfg->MemorySpdPtr11 = (u32)blk.spd_array[3]; + } + } mupd->FspmTestConfig.DmiVc1 = 1; + if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) + mem_cfg->UserBd = BOARD_TYPE_DESKTOP; } -- To view, visit https://review.coreboot.org/25194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I985968d331991884050c3920ec9798cd4cb371c7 Gerrit-Change-Number: 25194 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com>

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Change in coreboot[master]: soc/amd/stoneyridge/southbridge.c: Upgrade UART GPIO programming
by build bot (Jenkins) (Code Review) 15 Mar '18

15 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25192 ) Change subject: soc/amd/stoneyridge/southbridge.c: Upgrade UART GPIO programming ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22986/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68588/ : SUCCESS -- To view, visit https://review.coreboot.org/25192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98 Gerrit-Change-Number: 25192 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Mar 2018 16:05:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge/southbridge.c: Upgrade UART GPIO programming
by build bot (Jenkins) (Code Review) 15 Mar '18

15 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25192 ) Change subject: soc/amd/stoneyridge/southbridge.c: Upgrade UART GPIO programming ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22985/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68587/ : SUCCESS -- To view, visit https://review.coreboot.org/25192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98 Gerrit-Change-Number: 25192 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Mar 2018 15:59:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge/southbridge.c: Upgrade UART GPIO programming
by Richard Spiegel (Code Review) 15 Mar '18

15 Mar '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25192 Change subject: soc/amd/stoneyridge/southbridge.c: Upgrade UART GPIO programming ...................................................................... soc/amd/stoneyridge/southbridge.c: Upgrade UART GPIO programming Procedure configure_stoneyridge_uart() uses direct GPIO mux programming. Replace old style direct mux GPIO programming with a GPIO table and a call to centralized GPIO programming. BUG=b:74258015 TEST=Build and boot kahlee, observing serial output does not changes from previous serial output. Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/southbridge.c 1 file changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/25192/1 diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index a41ad1b..cce87e3 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -331,13 +331,17 @@ } while (!status); } +const static struct soc_amd_stoneyridge_gpio uart_gpio[] = { + PAD_NF(GPIO_137, UART0_RTS_L, PULL_NONE), + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), + PAD_NF(GPIO_142, UART1_RTS_L, PULL_NONE), + PAD_NF(GPIO_143, UART1_TXD, PULL_NONE) +}; + void configure_stoneyridge_uart(void) { /* Set the GPIO mux to UART */ - write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0); - write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0); - write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0); - write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0); + sb_program_gpios(uart_gpio, ARRAY_SIZE(uart_gpio)); } void sb_pci_port80(void) -- To view, visit https://review.coreboot.org/25192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98 Gerrit-Change-Number: 25192 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: security/tpm: Fix TPM software stack vulnerability
by build bot (Jenkins) (Code Review) 15 Mar '18

15 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25184 ) Change subject: security/tpm: Fix TPM software stack vulnerability ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22984/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68586/ : SUCCESS -- To view, visit https://review.coreboot.org/25184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1618b2cc579d189bccca7a781e2bed0976a8b471 Gerrit-Change-Number: 25184 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Comment-Date: Thu, 15 Mar 2018 15:47:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge: Create a HALT_THIS_AP callout
by build bot (Jenkins) (Code Review) 15 Mar '18

15 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24999 ) Change subject: soc/amd/stoneyridge: Create a HALT_THIS_AP callout ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22982/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68584/ : SUCCESS -- To view, visit https://review.coreboot.org/24999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I05ee405812211d93dfdbdc5ee7d9978c2eb585e1 Gerrit-Change-Number: 24999 Gerrit-PatchSet: 8 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Mar 2018 14:47:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nami: Add gpio-keys ACPI node for PENH
by build bot (Jenkins) (Code Review) 15 Mar '18

15 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25162 ) Change subject: mb/google/poppy/variants/nami: Add gpio-keys ACPI node for PENH ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22981/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68583/ : SUCCESS -- To view, visit https://review.coreboot.org/25162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5d87d938ac3a4e52e676850b9d8b80e83726275d Gerrit-Change-Number: 25162 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Mar 2018 14:44:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit March 2018