coreboot-gerrit March 2018

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Change in coreboot[master]: soc/intel/skylake: Save/restore GMA OpRegion address
by Matt DeVillier (Code Review) 15 Mar '18

15 Mar '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/25198 Change subject: soc/intel/skylake: Save/restore GMA OpRegion address ...................................................................... soc/intel/skylake: Save/restore GMA OpRegion address Add global/ACPI nvs variables required for IGD OpRegion. Add functions necessary to save the ACPI OpRegion table address in ASLB, and restore table address upon S3 resume. Implementation modeled on existing Baytrail code. Test: boot Windows 10 on google/chell with Tianocore payload and GOP display init, observe display driver loaded and functional, display not black screen when resuming from S3 suspend. Change-Id: Icd6b514e531eec6e49dbb03eb765144f41c1e31b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/graphics.c M src/soc/intel/skylake/include/soc/nvs.h 3 files changed, 98 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/25198/1 diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index 5564f02..c4544e8 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -71,6 +71,48 @@ EMNA, 64, // 0x44 - 0x4B EPC base address ELNG, 64, // 0x4C - 0x53 EPC Length + /* IGD OpRegion */ + Offset (0xb4), + ASLB, 32, // 0xb4 - IGD OpRegion Base Address + IBTT, 8, // 0xb8 - IGD boot panel device + IPAT, 8, // 0xb9 - IGD panel type cmos option + ITVF, 8, // 0xba - IGD TV format cmos option + ITVM, 8, // 0xbb - IGD TV minor format option + IPSC, 8, // 0xbc - IGD panel scaling + IBLC, 8, // 0xbd - IGD BLC config + IBIA, 8, // 0xbe - IGD BIA config + ISSC, 8, // 0xbf - IGD SSC config + I409, 8, // 0xc0 - IGD 0409 modified settings + I509, 8, // 0xc1 - IGD 0509 modified settings + I609, 8, // 0xc2 - IGD 0609 modified settings + I709, 8, // 0xc3 - IGD 0709 modified settings + IDMM, 8, // 0xc4 - IGD Power conservation feature + IDMS, 8, // 0xc5 - IGD DVMT memory size + IF1E, 8, // 0xc6 - IGD function 1 enable + HVCO, 8, // 0xc7 - IGD HPLL VCO + NXD1, 32, // 0xc8 - IGD _DGS next DID1 + NXD2, 32, // 0xcc - IGD _DGS next DID2 + NXD3, 32, // 0xd0 - IGD _DGS next DID3 + NXD4, 32, // 0xd4 - IGD _DGS next DID4 + NXD5, 32, // 0xd8 - IGD _DGS next DID5 + NXD6, 32, // 0xdc - IGD _DGS next DID6 + NXD7, 32, // 0xe0 - IGD _DGS next DID7 + NXD8, 32, // 0xe4 - IGD _DGS next DID8 + + ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) + PAVP, 8, // 0xe9 - IGD PAVP data + Offset (0xeb), + OSCC, 8, // 0xeb - PCIe OSC control + NPCE, 8, // 0xec - native pcie support + PLFL, 8, // 0xed - platform flavor + BREV, 8, // 0xee - board revision + DPBM, 8, // 0xef - digital port b mode + DPCM, 8, // 0xf0 - digital port c mode + DPDM, 8, // 0xf1 - digital port d mode + ALFP, 8, // 0xf2 - active lfp + IMON, 8, // 0xf3 - current graphics turbo imon value + MMIO, 8, // 0xf4 - 64bit mmio support + /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 95a37d6..bda08c5 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -14,11 +14,13 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <console/console.h> #include <device/pci.h> #include <drivers/intel/gma/i915_reg.h> #include <intelblocks/graphics.h> #include <drivers/intel/gma/opregion.h> +#include <soc/nvs.h> #include <soc/ramstage.h> uintptr_t fsp_soc_get_igd_bar(void) @@ -60,6 +62,21 @@ /* Initialize PCI device, load/execute BIOS Option ROM */ pci_dev_init(dev); + + intel_gma_restore_opregion(); +} + +uintptr_t gma_get_gnvs_aslb(const void *gnvs) +{ + const global_nvs_t *gnvs_ptr = gnvs; + return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); +} + +void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) +{ + global_nvs_t *gnvs_ptr = gnvs; + if (gnvs_ptr) + gnvs_ptr->aslb = aslb; } /* Initialize IGD OpRegion, called from ACPI code */ @@ -72,6 +89,7 @@ uintptr_t current, struct acpi_rsdp *rsdp) { igd_opregion_t *opregion; + global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); /* If GOP is not used, exit here */ if (!IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE)) @@ -86,7 +104,8 @@ if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) return current; - + if (gnvs) + gnvs->aslb = (u32)(uintptr_t)opregion; update_igd_opregion(opregion); current += sizeof(igd_opregion_t); current = acpi_align_current(current); diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 8bc4d8d..bd3610e 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -62,7 +62,42 @@ u8 ecps; /* 0x43 - SGX Enabled status */ u64 emna; /* 0x44 - 0x4B EPC base address */ u64 elng; /* 0x4C - 0x53 EPC Length */ - u8 unused[172]; + u8 rsvd[96]; + + /* IGD OpRegion */ + u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ + u8 ibtt; /* 0xb8 - IGD boot type */ + u8 ipat; /* 0xb9 - IGD panel type */ + u8 itvf; /* 0xba - IGD TV format */ + u8 itvm; /* 0xbb - IGD TV minor format */ + u8 ipsc; /* 0xbc - IGD Panel Scaling */ + u8 iblc; /* 0xbd - IGD BLC configuration */ + u8 ibia; /* 0xbe - IGD BIA configuration */ + u8 issc; /* 0xbf - IGD SSC configuration */ + u8 i409; /* 0xc0 - IGD 0409 modified settings */ + u8 i509; /* 0xc1 - IGD 0509 modified settings */ + u8 i609; /* 0xc2 - IGD 0609 modified settings */ + u8 i709; /* 0xc3 - IGD 0709 modified settings */ + u8 idmm; /* 0xc4 - IGD Power Conservation */ + u8 idms; /* 0xc5 - IGD DVMT memory size */ + u8 if1e; /* 0xc6 - IGD Function 1 Enable */ + u8 hvco; /* 0xc7 - IGD HPLL VCO */ + u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ + u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ + u8 pavp; /* 0xe9 - IGD PAVP data */ + u8 rsvd12; /* 0xea - rsvd */ + u8 oscc; /* 0xeb - PCIe OSC control */ + u8 npce; /* 0xec - native pcie support */ + u8 plfl; /* 0xed - platform flavor */ + u8 brev; /* 0xee - board revision */ + u8 dpbm; /* 0xef - digital port b mode */ + u8 dpcm; /* 0xf0 - digital port c mode */ + u8 dpdm; /* 0xf1 - digital port c mode */ + u8 alfp; /* 0xf2 - active lfp */ + u8 imon; /* 0xf3 - current graphics turbo imon value */ + u8 mmio; /* 0xf4 - 64bit mmio support */ + + u8 unused[11]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; -- To view, visit https://review.coreboot.org/25198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icd6b514e531eec6e49dbb03eb765144f41c1e31b Gerrit-Change-Number: 25198 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: soc/intel/braswell: Save/restore GMA OpRegion address
by Matt DeVillier (Code Review) 15 Mar '18

15 Mar '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/25197 Change subject: soc/intel/braswell: Save/restore GMA OpRegion address ...................................................................... soc/intel/braswell: Save/restore GMA OpRegion address Add global/ACPI nvs variables required for IGD OpRegion. Add functions necessary to save the ACPI OpRegion table address in ASLB, and restore table address upon S3 resume. Implementation modeled on existing Baytrail code. Test: boot Windows 10 on google/edgar with Tianocore payload and GOP display init, observe display driver loaded and functional, display not black screen when resuming from S3 suspend. Change-Id: I7c1fbf818510949420f70e93ed4780e94e598508 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/acpi/globalnvs.asl M src/soc/intel/braswell/gfx.c M src/soc/intel/braswell/include/soc/nvs.h 4 files changed, 98 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/25197/1 diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 61ad03d..9ac5574c 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -486,6 +486,7 @@ struct acpi_rsdp *rsdp) { acpi_header_t *ssdt2; + global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); current = acpi_write_hpet(device, current, rsdp); current = acpi_align_current(current); @@ -496,6 +497,8 @@ printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); opregion = (igd_opregion_t *)current; intel_gma_init_igd_opregion(opregion); + if (gnvs) + gnvs->aslb = (u32)opregion; update_igd_opregion(opregion); current += sizeof(igd_opregion_t); current = acpi_align_current(current); diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index a53834a..c0b0b8d 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -71,6 +71,48 @@ TOLM, 32, /* 0x34 - Top of Low Memory */ CBMC, 32, /* 0x38 - coreboot mem console pointer */ + /* IGD OpRegion */ + Offset (0xb4), + ASLB, 32, // 0xb4 - IGD OpRegion Base Address + IBTT, 8, // 0xb8 - IGD boot panel device + IPAT, 8, // 0xb9 - IGD panel type cmos option + ITVF, 8, // 0xba - IGD TV format cmos option + ITVM, 8, // 0xbb - IGD TV minor format option + IPSC, 8, // 0xbc - IGD panel scaling + IBLC, 8, // 0xbd - IGD BLC config + IBIA, 8, // 0xbe - IGD BIA config + ISSC, 8, // 0xbf - IGD SSC config + I409, 8, // 0xc0 - IGD 0409 modified settings + I509, 8, // 0xc1 - IGD 0509 modified settings + I609, 8, // 0xc2 - IGD 0609 modified settings + I709, 8, // 0xc3 - IGD 0709 modified settings + IDMM, 8, // 0xc4 - IGD Power conservation feature + IDMS, 8, // 0xc5 - IGD DVMT memory size + IF1E, 8, // 0xc6 - IGD function 1 enable + HVCO, 8, // 0xc7 - IGD HPLL VCO + NXD1, 32, // 0xc8 - IGD _DGS next DID1 + NXD2, 32, // 0xcc - IGD _DGS next DID2 + NXD3, 32, // 0xd0 - IGD _DGS next DID3 + NXD4, 32, // 0xd4 - IGD _DGS next DID4 + NXD5, 32, // 0xd8 - IGD _DGS next DID5 + NXD6, 32, // 0xdc - IGD _DGS next DID6 + NXD7, 32, // 0xe0 - IGD _DGS next DID7 + NXD8, 32, // 0xe4 - IGD _DGS next DID8 + + ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) + PAVP, 8, // 0xe9 - IGD PAVP data + Offset (0xeb), + OSCC, 8, // 0xeb - PCIe OSC control + NPCE, 8, // 0xec - native pcie support + PLFL, 8, // 0xed - platform flavor + BREV, 8, // 0xee - board revision + DPBM, 8, // 0xef - digital port b mode + DPCM, 8, // 0xf0 - digital port c mode + DPDM, 8, // 0xf1 - digital port d mode + ALFP, 8, // 0xf2 - active lfp + IMON, 8, // 0xf3 - current graphics turbo imon value + MMIO, 8, // 0xf4 - 64bit mmio support + /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index 4328abb..8481446 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -20,8 +20,10 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <drivers/intel/gma/opregion.h> #include <reg_script.h> #include <soc/gfx.h> +#include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> @@ -73,6 +75,21 @@ /* Post VBIOS Init */ gfx_post_vbios_init(dev); + + intel_gma_restore_opregion(); +} + +uintptr_t gma_get_gnvs_aslb(const void *gnvs) +{ + const global_nvs_t *gnvs_ptr = gnvs; + return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); +} + +void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) +{ + global_nvs_t *gnvs_ptr = gnvs; + if (gnvs_ptr) + gnvs_ptr->aslb = aslb; } static struct device_operations gfx_device_ops = { diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 9b921c5..89a434b 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -63,7 +63,42 @@ u32 cmem; /* 0x30 - CBMEM TOC */ u32 tolm; /* 0x34 - Top of Low Memory */ u32 cbmc; /* 0x38 - coreboot memconsole */ - u8 rsvd3[196]; + u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */ + + /* IGD OpRegion */ + u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ + u8 ibtt; /* 0xb8 - IGD boot type */ + u8 ipat; /* 0xb9 - IGD panel type */ + u8 itvf; /* 0xba - IGD TV format */ + u8 itvm; /* 0xbb - IGD TV minor format */ + u8 ipsc; /* 0xbc - IGD Panel Scaling */ + u8 iblc; /* 0xbd - IGD BLC configuration */ + u8 ibia; /* 0xbe - IGD BIA configuration */ + u8 issc; /* 0xbf - IGD SSC configuration */ + u8 i409; /* 0xc0 - IGD 0409 modified settings */ + u8 i509; /* 0xc1 - IGD 0509 modified settings */ + u8 i609; /* 0xc2 - IGD 0609 modified settings */ + u8 i709; /* 0xc3 - IGD 0709 modified settings */ + u8 idmm; /* 0xc4 - IGD Power Conservation */ + u8 idms; /* 0xc5 - IGD DVMT memory size */ + u8 if1e; /* 0xc6 - IGD Function 1 Enable */ + u8 hvco; /* 0xc7 - IGD HPLL VCO */ + u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ + u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ + u8 pavp; /* 0xe9 - IGD PAVP data */ + u8 rsvd12; /* 0xea - rsvd */ + u8 oscc; /* 0xeb - PCIe OSC control */ + u8 npce; /* 0xec - native pcie support */ + u8 plfl; /* 0xed - platform flavor */ + u8 brev; /* 0xee - board revision */ + u8 dpbm; /* 0xef - digital port b mode */ + u8 dpcm; /* 0xf0 - digital port c mode */ + u8 dpdm; /* 0xf1 - digital port c mode */ + u8 alfp; /* 0xf2 - active lfp */ + u8 imon; /* 0xf3 - current graphics turbo imon value */ + u8 mmio; /* 0xf4 - 64bit mmio support */ + + u8 unused[11]; /* ChromeOS specific (0x100-0xfff) */ chromeos_acpi_t chromeos; -- To view, visit https://review.coreboot.org/25197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7c1fbf818510949420f70e93ed4780e94e598508 Gerrit-Change-Number: 25197 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: security/flash: Add SPI flash protection
by build bot (Jenkins) (Code Review) 15 Mar '18

15 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25196 ) Change subject: security/flash: Add SPI flash protection ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/68595/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22992/ : SUCCESS -- To view, visit https://review.coreboot.org/25196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I12656d7c111ed3622fab5578f6e0c462fe5d4796 Gerrit-Change-Number: 25196 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Mar 2018 16:56:55 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge/southbridge.c: Create AOAC initialization code
by build bot (Jenkins) (Code Review) 15 Mar '18

15 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25142 ) Change subject: soc/amd/stoneyridge/southbridge.c: Create AOAC initialization code ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22991/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68594/ : SUCCESS -- To view, visit https://review.coreboot.org/25142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I359791c2a332629aa991f2f17a67e94726a21eb5 Gerrit-Change-Number: 25142 Gerrit-PatchSet: 5 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshall.dawson(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Mar 2018 16:54:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/flash: Add SPI flash protection
by Philipp Deppenwiese (Code Review) 15 Mar '18

15 Mar '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/25196 Change subject: security/flash: Add SPI flash protection ...................................................................... security/flash: Add SPI flash protection * get/set write protection for SPI flash. * GPIO weak function for WP pin lookup (VBOOT). Change-Id: I12656d7c111ed3622fab5578f6e0c462fe5d4796 Signed-off-by: zaolin <zaolin(a)das-labor.org> --- M src/security/Kconfig M src/security/Makefile.inc A src/security/flash/Kconfig A src/security/flash/Makefile.inc A src/security/flash/flash.c A src/security/flash/flash.h 6 files changed, 229 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/25196/1 diff --git a/src/security/Kconfig b/src/security/Kconfig index 6a334ac..006d089 100644 --- a/src/security/Kconfig +++ b/src/security/Kconfig @@ -14,3 +14,4 @@ source "src/security/vboot/Kconfig" source "src/security/tpm/Kconfig" +source "src/security/flash/Kconfig" diff --git a/src/security/Makefile.inc b/src/security/Makefile.inc index a940b82..413f7d0 100644 --- a/src/security/Makefile.inc +++ b/src/security/Makefile.inc @@ -1,2 +1,3 @@ subdirs-y += vboot subdirs-y += tpm +subdirs-y += flash diff --git a/src/security/flash/Kconfig b/src/security/flash/Kconfig new file mode 100644 index 0000000..67e62c7 --- /dev/null +++ b/src/security/flash/Kconfig @@ -0,0 +1,102 @@ +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Philipp Deppenwiese, Facebook, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +menu "Flash write protection" + +config FLASH_SPI_PROTECTIONS + bool + default y if MAINBOARD_HAS_FLASH_SPI_PROTECTIONS || USER_FLASH_SPI_PROTECTIONS + depends on SPI_FLASH + +config FLASH_PCH_PROTECTIONS + bool + default y if MAINBOARD_HAS_FLASH_PCH_PROTECTIONS || USER_FLASH_PCH_PROTECTIONS + +config MAINBOARD_HAS_FLASH_PCH_PROTECTIONS + bool + +config MAINBOARD_HAS_FLASH_SPI_PROTECTIONS + bool + +if !MAINBOARD_HAS_FLASH_SPI_PROTECTIONS && !MAINBOARD_HAS_FLASH_PCH_PROTECTIONS + +choice + prompt "Type" + default USER_FLASH_PCH_PROTECTIONS + +config USER_FLASH_SPI_PROTECTIONS + bool "SPI flash" + help + Enable this option to enable SPI flash write protection. + +config USER_FLASH_PCH_PROTECTIONS + bool "Platform PCH" + help + Enable this option to enable PCH flash write protection. + +endchoice + +endif + +config FLASH_MODE_VBOOT + bool + default y if MAINBOARD_HAS_FLASH_MODE_VBOOT || USER_FLASH_SPI_PROTECTIONS + depends on VBOOT + +config FLASH_MODE_BIOS + bool + default y if MAINBOARD_HAS_FLASH_MODE_BIOS || USER_FLASH_PCH_PROTECTIONS + +config FLASH_MODE_EVERYTHING + bool + default y if MAINBOARD_HAS_FLASH_MODE_EVERYTHING || USER_FLASH_PCH_PROTECTIONS + +config MAINBOARD_HAS_FLASH_MODE_VBOOT + bool + +config MAINBOARD_HAS_FLASH_MODE_BIOS + bool + +config MAINBOARD_HAS_FLASH_MODE_EVERYTHING + bool + +if !MAINBOARD_HAS_FLASH_MODE_VBOOT && !MAINBOARD_HAS_FLASH_MODE_BIOS && !MAINBOARD_HAS_FLASH_MODE_EVERYTHING + +choice + prompt "Mode" + default USER_NO_FLASH_PROTECTION + +config USER_NO_FLASH_PROTECTION + bool "disabled" + +config USER_FLASH_MODE_VBOOT + bool "Verified Boot" + help + Enable this option to enable VBoot mode. + +config USER_FLASH_MODE_BIOS + bool "BIOS region" + help + Enable this option to enable BIOS region write protection. + +config USER_FLASH_MODE_EVERYTHING + bool "Entire SPI flash" + help + Enable this option to enable entire flash write protection. + +endchoice + +endif + +endmenu diff --git a/src/security/flash/Makefile.inc b/src/security/flash/Makefile.inc new file mode 100644 index 0000000..50d4a7a --- /dev/null +++ b/src/security/flash/Makefile.inc @@ -0,0 +1,5 @@ +## flash + +verstage-y += flash.c +romstage-y += flash.c +ramstage-y += flash.c diff --git a/src/security/flash/flash.c b/src/security/flash/flash.c new file mode 100644 index 0000000..b103909 --- /dev/null +++ b/src/security/flash/flash.c @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <commonlib/region.h> +#include <fmap.h> +#include <security/flash/flash.h> +#include <spi_flash.h> + +#define FMAP_VBOOT_RO_REGION "WP_RO" +#define FMAP_BIOS_REGION "BIOS" +#define FMAP_FLASH_REGION "FLASH" + +__attribute__((weak)) int gpio_get_wp_state(void) { return 0; } + +int set_write_protect_enabled(void) +{ + int result = -1; + struct region region; + + if (IS_ENABLED(CONFIG_FLASH_SPI_PROTECTIONS)) { + struct spi_flash flash; + + spi_init(); + if (spi_flash_probe(0, 0, &flash)) + return result; + + if (IS_ENABLED(CONFIG_FLASH_MODE_VBOOT)) { + if (fmap_locate_area(FMAP_VBOOT_RO_REGION, &region) == + 0) { + result = spi_flash_set_write_protected(&flash, + &region); + } + } else if (IS_ENABLED(CONFIG_FLASH_MODE_BIOS)) { + if (fmap_locate_area(FMAP_BIOS_REGION, &region) == 0) { + result = spi_flash_set_write_protected(&flash, + &region); + } + } else if (IS_ENABLED(CONFIG_FLASH_MODE_EVERYTHING)) { + if (fmap_locate_area(FMAP_FLASH_REGION, &region) == 0) { + result = spi_flash_set_write_protected(&flash, + &region); + } + } + } else if (IS_ENABLED(CONFIG_FLASH_PCH_PROTECTIONS)) { + } + + return result; +} + +int get_write_protect_state(void) +{ + int result = -1; + struct region region; + + if (IS_ENABLED(CONFIG_FLASH_SPI_PROTECTIONS)) { + struct spi_flash flash; + + spi_init(); + if (spi_flash_probe(0, 0, &flash)) + return result; + + if (IS_ENABLED(CONFIG_FLASH_MODE_VBOOT)) { + if (fmap_locate_area(FMAP_VBOOT_RO_REGION, &region) == + 0) { + result = spi_flash_is_write_protected(&flash, + &region); + result &= gpio_get_wp_state(); + } + } else if (IS_ENABLED(CONFIG_FLASH_MODE_BIOS)) { + if (fmap_locate_area(FMAP_BIOS_REGION, &region) == 0) { + result = spi_flash_is_write_protected(&flash, + &region); + } + } else if (IS_ENABLED(CONFIG_FLASH_MODE_EVERYTHING)) { + if (fmap_locate_area(FMAP_FLASH_REGION, &region) == 0) { + result = spi_flash_is_write_protected(&flash, + &region); + } + } + } else if (IS_ENABLED(CONFIG_FLASH_PCH_PROTECTIONS)) { + } + + return result; +} diff --git a/src/security/flash/flash.h b/src/security/flash/flash.h new file mode 100644 index 0000000..bbd60df --- /dev/null +++ b/src/security/flash/flash.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef FLASH_H_ +#define FLASH_H_ + +int gpio_get_wp_state(void); + +int set_write_protect_enabled(void); +int get_write_protect_state(void); + +#endif /* FLASH_H_ */ -- To view, visit https://review.coreboot.org/25196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I12656d7c111ed3622fab5578f6e0c462fe5d4796 Gerrit-Change-Number: 25196 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: mb/intel/kblrvp8: Add KBLRVP8 support
by build bot (Jenkins) (Code Review) 15 Mar '18

15 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25194 ) Change subject: mb/intel/kblrvp8: Add KBLRVP8 support ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22989/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68592/ : SUCCESS -- To view, visit https://review.coreboot.org/25194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I985968d331991884050c3920ec9798cd4cb371c7 Gerrit-Change-Number: 25194 Gerrit-PatchSet: 3 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Mar 2018 16:47:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge/southbridge.c: Create AOAC initialization code
by build bot (Jenkins) (Code Review) 15 Mar '18

15 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25142 ) Change subject: soc/amd/stoneyridge/southbridge.c: Create AOAC initialization code ...................................................................... Patch Set 4: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/22990/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/68593/ : ABORTED -- To view, visit https://review.coreboot.org/25142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I359791c2a332629aa991f2f17a67e94726a21eb5 Gerrit-Change-Number: 25142 Gerrit-PatchSet: 4 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshall.dawson(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Mar 2018 16:46:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/intel/kblrvp8: Add KBLRVP8 support
by build bot (Jenkins) (Code Review) 15 Mar '18

15 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25194 ) Change subject: mb/intel/kblrvp8: Add KBLRVP8 support ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68591/ : SUCCESS -- To view, visit https://review.coreboot.org/25194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I985968d331991884050c3920ec9798cd4cb371c7 Gerrit-Change-Number: 25194 Gerrit-PatchSet: 2 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Mar 2018 16:35:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/intel/kblrvp8: Add KBLRVP8 support
by Subrata Banik (Code Review) 15 Mar '18

15 Mar '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/25194 ) Change subject: mb/intel/kblrvp8: Add KBLRVP8 support ...................................................................... Patch Set 2: rvp7 has only 1 ch? -- To view, visit https://review.coreboot.org/25194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I985968d331991884050c3920ec9798cd4cb371c7 Gerrit-Change-Number: 25194 Gerrit-PatchSet: 2 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Mar 2018 16:33:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/intel/kblrvp8: Add KBLRVP8 support
by Subrata Banik (Code Review) 15 Mar '18

15 Mar '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/25194 ) Change subject: mb/intel/kblrvp8: Add KBLRVP8 support ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/25194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I985968d331991884050c3920ec9798cd4cb371c7 Gerrit-Change-Number: 25194 Gerrit-PatchSet: 2 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Mar 2018 16:32:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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