coreboot-gerrit March 2018

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Change in coreboot[master]: soc/intel/coffeelake: Modify PCR ID for ABASE address for Coffeelake-H
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

1 0

Change in coreboot[master]: drivers/intel/fsp2_0: Add support for FSP tempraminit
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

1 0

Change in coreboot[master]: src/soc/intel/coffeelake: Add support for FSP tempraminit for CFL
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

1 0

Change in coreboot[master]: soc/intel/coffeelake: Include Coffeelake Device Ids
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

Hello Naresh Solanki, Subrata Banik, Balaji Manigandan, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, I'd like you to do a code review. Please visit https://review.coreboot.org/25224 to review the following change. Change subject: soc/intel/coffeelake: Include Coffeelake Device Ids ...................................................................... soc/intel/coffeelake: Include Coffeelake Device Ids Add Coffeelake specific CPU, System Agent, PCH, IGD Device ID, etc. Change-Id: Ia8417199205c26b9147f7b04a2418ca22ffc188b Signed-off-by: Ng Kin Wai <kin.wai.ng(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/coffeelake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c 18 files changed, 82 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/25224/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h old mode 100644 new mode 100755 index c184383..cd534f9 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2682,6 +2682,8 @@ #define PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC 0x9d85 #define PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC 0x9d84 #define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83 +#define PCI_DEVICE_ID_INTEL_CNL_H_LPC_Q370 0xa306 +#define PCI_DEVICE_ID_INTEL_CNL_H_LPC_QM370 0xa30c /* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 @@ -2760,6 +2762,23 @@ #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15 0x9db6 #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16 0x9db7 +#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP1 0xa338 +#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP2 0xa339 +#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP3 0xa33a +#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP4 0xa33b +#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP5 0xa33c +#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP6 0xa33d +#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP7 0xa33e +#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP8 0xa33f +#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP9 0xa330 +#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP10 0xa331 +#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP11 0xa332 +#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP12 0xa333 +#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP13 0xa334 +#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP14 0xa335 +#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP15 0xa336 +#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP16 0xa337 + /* Intel SATA device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03 #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07 @@ -2769,6 +2788,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_SATA 0x9dd5 #define PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA 0x9dd7 #define PCI_DEVICE_ID_INTEL_CNL_COMPAT_SATA 0x282a +#define PCI_DEVICE_ID_INTEL_CNL_H_SATA 0xa352 /* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 @@ -2777,6 +2797,7 @@ #define PCI_DEVICE_ID_INTEL_APL_PMC 0x5a94 #define PCI_DEVICE_ID_INTEL_GLK_PMC 0x3194 #define PCI_DEVICE_ID_INTEL_CNL_PMC 0x9da1 +#define PCI_DEVICE_ID_INTEL_CNL_H_PMC 0xa321 /* Intel I2C device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 @@ -2811,6 +2832,10 @@ #define PCI_DEVICE_ID_INTEL_CNL_I2C3 0x9deb #define PCI_DEVICE_ID_INTEL_CNL_I2C4 0x9dc5 #define PCI_DEVICE_ID_INTEL_CNL_I2C5 0x9dc6 +#define PCI_DEVICE_ID_INTEL_CNL_H_I2C0 0xa368 +#define PCI_DEVICE_ID_INTEL_CNL_H_I2C1 0xa369 +#define PCI_DEVICE_ID_INTEL_CNL_H_I2C2 0xa36a +#define PCI_DEVICE_ID_INTEL_CNL_H_I2C3 0xa36b /* Intel UART device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27 @@ -2833,6 +2858,9 @@ #define PCI_DEVICE_ID_INTEL_CNL_UART0 0x9da8 #define PCI_DEVICE_ID_INTEL_CNL_UART1 0x9da9 #define PCI_DEVICE_ID_INTEL_CNL_UART2 0x9dc7 +#define PCI_DEVICE_ID_INTEL_CNL_H_UART0 0xa328 +#define PCI_DEVICE_ID_INTEL_CNL_H_UART1 0xa329 +#define PCI_DEVICE_ID_INTEL_CNL_H_UART2 0xa347 /* Intel SPI device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24 @@ -2875,6 +2903,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2 0x5A5A #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3 0x5A42 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4 0x5A4A +#define PCI_DEVICE_ID_INTEL_CFL_H 0x3e9b /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -2891,12 +2920,14 @@ #define PCI_DEVICE_ID_INTEL_KBL_ID_DT 0x591f #define PCI_DEVICE_ID_INTEL_CNL_ID_U 0x5A04 #define PCI_DEVICE_ID_INTEL_CNL_ID_Y 0x5A02 +#define PCI_DEVICE_ID_INTEL_CNL_ID_H 0x3ec4 /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 #define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS 0xa123 #define PCI_DEVICE_ID_INTEL_KBP_H_SMBUS 0xa1a3 #define PCI_DEVICE_ID_INTEL_CNL_SMBUS 0x9da3 +#define PCI_DEVICE_ID_INTEL_CNL_H_SMBUS 0xa323 /* Intel XHCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 @@ -2905,16 +2936,19 @@ #define PCI_DEVICE_ID_INTEL_SPT_H_XHCI 0xa12f #define PCI_DEVICE_ID_INTEL_KBP_H_XHCI 0xa2af #define PCI_DEVICE_ID_INTEL_CNL_LP_XHCI 0x9ded +#define PCI_DEVICE_ID_INTEL_CNP_H_XHCI 0xa36d /* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 #define PCI_DEVICE_ID_INTEL_GLK_P2SB 0x3192 #define PCI_DEVICE_ID_INTEL_CNL_P2SB 0x9da0 +#define PCI_DEVICE_ID_INTEL_CNL_H_P2SB 0xa320 /* Intel SRAM device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec #define PCI_DEVICE_ID_INTEL_GLK_SRAM 0x31ec #define PCI_DEVICE_ID_INTEL_CNL_SRAM 0x9def +#define PCI_DEVICE_ID_INTEL_CNL_H_SRAM 0xa36f /* Intel AUDIO device Ids */ #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98 @@ -2922,24 +2956,28 @@ #define PCI_DEVICE_ID_INTEL_CNL_AUDIO 0x9dc8 #define PCI_DEVICE_ID_INTEL_SKL_AUDIO 0x9d70 #define PCI_DEVICE_ID_INTEL_KBL_AUDIO 0x9d71 +#define PCI_DEVICE_ID_INTEL_CNL_H_AUDIO 0xa348 /* Intel HECI/ME device Ids */ #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a #define PCI_DEVICE_ID_INTEL_GLK_CSE0 0x319a #define PCI_DEVICE_ID_INTEL_CNL_CSE0 0x9de0 #define PCI_DEVICE_ID_INTEL_SKL_CSE0 0x9d3a +#define PCI_DEVICE_ID_INTEL_CNL_H_CSE0 0xa360 /* Intel XDCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa #define PCI_DEVICE_ID_INTEL_GLK_XDCI 0x31aa #define PCI_DEVICE_ID_INTEL_SPT_LP_XDCI 0x9d30 #define PCI_DEVICE_ID_INTEL_CNL_LP_XDCI 0x9dee +#define PCI_DEVICE_ID_INTEL_CNL_H_XDCI 0xa36e /* Intel SD device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca #define PCI_DEVICE_ID_INTEL_SKL_SD 0x9d2d #define PCI_DEVICE_ID_INTEL_CNL_SD 0x9df5 +#define PCI_DEVICE_ID_INTEL_CNL_H_SD 0xa375 /* Intel EMMC device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_EMMC 0x9d2b @@ -2952,6 +2990,8 @@ #define PCH_CNL_LP_U_PREMIUM 0x9d84 #define PCH_CNL_LP_U_BASE 0x9d85 #define PCH_CNL_H_DT_SUPER 0xa280 +#define PCH_CNL_H_MOBILE_Q370 0xa306 +#define PCH_CNL_H_MOBILE_QM370 0xa30c #define PCI_VENDOR_ID_COMPUTONE 0x8e0e #define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 diff --git a/src/soc/intel/coffeelake/bootblock/report_platform.c b/src/soc/intel/coffeelake/bootblock/report_platform.c old mode 100644 new mode 100755 index c37f475..4748004 --- a/src/soc/intel/coffeelake/bootblock/report_platform.c +++ b/src/soc/intel/coffeelake/bootblock/report_platform.c @@ -32,41 +32,29 @@ u32 cpuid; const char *name; } cpu_table[] = { - { CPUID_CANNONLAKE_A0, "Cannonlake A0" }, - { CPUID_CANNONLAKE_B0, "Cannonlake B0" }, - { CPUID_CANNONLAKE_C0, "Cannonlake C0" }, - { CPUID_CANNONLAKE_D0, "Cannonlake D0" }, + { CPUID_COFFEELAKE_A0, "Coffeelake A0" }, }; static struct { u16 mchid; const char *name; } mch_table[] = { - { PCI_DEVICE_ID_INTEL_CNL_ID_U, "Cannonlake-U" }, - { PCI_DEVICE_ID_INTEL_CNL_ID_Y, "Cannonlake-Y" }, + { PCI_DEVICE_ID_INTEL_CNL_ID_H, "CoffeeLake Halo (6+2)" }, }; static struct { u16 lpcid; const char *name; } pch_table[] = { - { PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, "Cannonlake-U Base" }, - { PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, "Cannonlake-U Premium" }, - { PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" }, + { PCI_DEVICE_ID_INTEL_CNL_H_LPC_Q370, "Coffeelake-H" }, + { PCI_DEVICE_ID_INTEL_CNL_H_LPC_QM370, "Coffeelake-H" }, }; static struct { u16 igdid; const char *name; } igd_table[] = { - { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1, "Cannonlake ULX GT2" }, - { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2, "Cannonlake ULX GT1.5" }, - { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3, "Cannonlake ULX GT1" }, - { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_4, "Cannonlake ULX GT0.5" }, - { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_1, "Cannonlake ULT GT2" }, - { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2, "Cannonlake ULT GT1.5" }, - { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3, "Cannonlake ULT GT1" }, - { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" }, + { PCI_DEVICE_ID_INTEL_CFL_H, "Coffeelake H" }, }; static uint8_t get_dev_revision(device_t dev) diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c old mode 100644 new mode 100755 index 085a340..40086e4 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -69,6 +69,7 @@ { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 }, { X86_VENDOR_INTEL, CPUID_GLK_A0 }, { X86_VENDOR_INTEL, CPUID_GLK_B0 }, + { X86_VENDOR_INTEL, CPUID_COFFEELAKE_A0 }, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c old mode 100644 new mode 100755 index 4991db6..d57cb7f --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -514,6 +514,7 @@ PCI_DEVICE_ID_INTEL_GLK_CSE0, PCI_DEVICE_ID_INTEL_CNL_CSE0, PCI_DEVICE_ID_INTEL_SKL_CSE0, + PCI_DEVICE_ID_INTEL_CNL_H_CSE0, 0, }; diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c old mode 100644 new mode 100755 index 365fab7..2b11cd8 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -31,6 +31,7 @@ PCI_DEVICE_ID_INTEL_CNL_AUDIO, PCI_DEVICE_ID_INTEL_GLK_AUDIO, PCI_DEVICE_ID_INTEL_SKL_AUDIO, + PCI_DEVICE_ID_INTEL_CNL_H_AUDIO, 0, }; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c old mode 100644 new mode 100755 index dcf8200..fa63477 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -128,6 +128,7 @@ PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM, PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM, PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM, + PCI_DEVICE_ID_INTEL_CFL_H, 0, }; diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c old mode 100644 new mode 100755 index 7dd40db..95b5bae --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -93,6 +93,10 @@ PCI_DEVICE_ID_INTEL_GLK_I2C5, PCI_DEVICE_ID_INTEL_GLK_I2C6, PCI_DEVICE_ID_INTEL_GLK_I2C7, + PCI_DEVICE_ID_INTEL_CNL_H_I2C0, + PCI_DEVICE_ID_INTEL_CNL_H_I2C1, + PCI_DEVICE_ID_INTEL_CNL_H_I2C2, + PCI_DEVICE_ID_INTEL_CNL_H_I2C3, 0, }; diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h old mode 100644 new mode 100755 index 3057209..d9336b9 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -37,6 +37,7 @@ #define CPUID_APOLLOLAKE_E0 0x506ca #define CPUID_GLK_A0 0x706a0 #define CPUID_GLK_B0 0x706a1 +#define CPUID_COFFEELAKE_A0 0x906ea /* * MP Init callback function to Find CPU Topology. This function is common diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c old mode 100644 new mode 100755 index 2efdc8d..b525ef8 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -140,6 +140,8 @@ PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, + PCI_DEVICE_ID_INTEL_CNL_H_LPC_Q370, + PCI_DEVICE_ID_INTEL_CNL_H_LPC_QM370, 0 }; diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c old mode 100644 new mode 100755 index 6a9bd34..23e279e --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -71,6 +71,7 @@ PCI_DEVICE_ID_INTEL_APL_P2SB, PCI_DEVICE_ID_INTEL_GLK_P2SB, PCI_DEVICE_ID_INTEL_CNL_P2SB, + PCI_DEVICE_ID_INTEL_CNL_H_P2SB, 0, }; diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c old mode 100644 new mode 100755 index 7d383fd..74f21e6 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -165,6 +165,22 @@ PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14, PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15, PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16, + PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP1, + PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP2, + PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP3, + PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP4, + PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP5, + PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP6, + PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP7, + PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP8, + PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP9, + PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP10, + PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP11, + PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP12, + PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP13, + PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP14, + PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP15, + PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP16, 0 }; diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c old mode 100644 new mode 100755 index cabe895..b3e0672 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -76,6 +76,7 @@ PCI_DEVICE_ID_INTEL_CNL_SATA, PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA, PCI_DEVICE_ID_INTEL_CNL_COMPAT_SATA, + PCI_DEVICE_ID_INTEL_CNL_H_SATA, 0 }; diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c old mode 100644 new mode 100755 index 66eaddf5..7d2bfb0 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -69,6 +69,7 @@ PCI_DEVICE_ID_INTEL_CNL_SD, PCI_DEVICE_ID_INTEL_GLK_SD, PCI_DEVICE_ID_INTEL_SKL_SD, + PCI_DEVICE_ID_INTEL_CNL_H_SD, 0 }; diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c old mode 100644 new mode 100755 index 3793025..f27a53b --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -91,7 +91,7 @@ PCI_DEVICE_ID_INTEL_CNL_SMBUS, PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS, PCI_DEVICE_ID_INTEL_SPT_H_SMBUS, - PCI_DEVICE_ID_INTEL_KBP_H_SMBUS, + PCI_DEVICE_ID_INTEL_CNL_H_SMBUS, 0 }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c old mode 100644 new mode 100755 index 027222b..4be9cae --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -299,6 +299,7 @@ PCI_DEVICE_ID_INTEL_KBL_ID_H, PCI_DEVICE_ID_INTEL_KBL_U_R, PCI_DEVICE_ID_INTEL_KBL_ID_DT, + PCI_DEVICE_ID_INTEL_CNL_ID_H, 0 }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c old mode 100644 new mode 100755 index 9f26ef1..582d5cf --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -168,6 +168,9 @@ PCI_DEVICE_ID_INTEL_GLK_UART1, PCI_DEVICE_ID_INTEL_GLK_UART2, PCI_DEVICE_ID_INTEL_GLK_UART3, + PCI_DEVICE_ID_INTEL_CNL_H_UART0, + PCI_DEVICE_ID_INTEL_CNL_H_UART1, + PCI_DEVICE_ID_INTEL_CNL_H_UART2, 0, }; diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c old mode 100644 new mode 100755 index 10e6f0d..6a61d5e --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -35,6 +35,7 @@ PCI_DEVICE_ID_INTEL_CNL_LP_XDCI, PCI_DEVICE_ID_INTEL_GLK_XDCI, PCI_DEVICE_ID_INTEL_SPT_LP_XDCI, + PCI_DEVICE_ID_INTEL_CNL_H_XDCI, 0 }; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c old mode 100644 new mode 100755 index e5a4f9b..dd11e83 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -37,6 +37,7 @@ PCI_DEVICE_ID_INTEL_SPT_LP_XHCI, PCI_DEVICE_ID_INTEL_SPT_H_XHCI, PCI_DEVICE_ID_INTEL_KBP_H_XHCI, + PCI_DEVICE_ID_INTEL_CNP_H_XHCI, 0 }; -- To view, visit https://review.coreboot.org/25224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia8417199205c26b9147f7b04a2418ca22ffc188b Gerrit-Change-Number: 25224 Gerrit-PatchSet: 1 Gerrit-Owner: Kin Wai Ng <kin.wai.ng(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/coffeelake: Use DRIVERS_UART_8250IO
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

1 0

Change in coreboot[master]: lib/lzma: Respect dstn argument
by build bot (Jenkins) (Code Review) 16 Mar '18

16 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25222 ) Change subject: lib/lzma: Respect dstn argument ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23066/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68670/ : SUCCESS -- To view, visit https://review.coreboot.org/25222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I336de417c7cd6f35cf84947fc4ae161c15bd93ef Gerrit-Change-Number: 25222 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Mar 2018 11:35:55 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: lib/lzma: Respect dstn argument
by Patrick Rudolph (Code Review) 16 Mar '18

16 Mar '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25222 Change subject: lib/lzma: Respect dstn argument ...................................................................... lib/lzma: Respect dstn argument Don't write more bytes than the caller requests. Based on I484b5c1e3809781033d146609a35a9e5e666c8ed. Change-Id: I336de417c7cd6f35cf84947fc4ae161c15bd93ef Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/lib/lzma.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/25222/1 diff --git a/src/lib/lzma.c b/src/lib/lzma.c index f727553..dbc464c 100644 --- a/src/lib/lzma.c +++ b/src/lib/lzma.c @@ -37,6 +37,8 @@ * byte and re-construct. */ cp = src + LZMA_PROPERTIES_SIZE; outSize = cp[3] << 24 | cp[2] << 16 | cp[1] << 8 | cp[0]; + if (outSize > dstn) + outSize = dstn; if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) { printk(BIOS_WARNING, "lzma: Incorrect stream properties.\n"); -- To view, visit https://review.coreboot.org/25222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I336de417c7cd6f35cf84947fc4ae161c15bd93ef Gerrit-Change-Number: 25222 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

1 0

Change in coreboot[master]: fsp/fsp2_0/coffeelake: Add CFL FSP UPD Headers to ver 7.0.25.34
by build bot (Jenkins) (Code Review) 16 Mar '18

16 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25219 ) Change subject: fsp/fsp2_0/coffeelake: Add CFL FSP UPD Headers to ver 7.0.25.34 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23064/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68668/ : SUCCESS -- To view, visit https://review.coreboot.org/25219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie2e9ad53afbad931c494beb9c02de1f717718a37 Gerrit-Change-Number: 25219 Gerrit-PatchSet: 1 Gerrit-Owner: Kin Wai Ng <kin.wai.ng(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Mar 2018 09:37:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: fsp/fsp2_0/coffeelake: Add CFL FSP UPD Headers to ver 7.0.25.34
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

Kin Wai Ng has uploaded this change for review. ( https://review.coreboot.org/25219 Change subject: fsp/fsp2_0/coffeelake: Add CFL FSP UPD Headers to ver 7.0.25.34 ...................................................................... fsp/fsp2_0/coffeelake: Add CFL FSP UPD Headers to ver 7.0.25.34 Header files based on FSP 7.0.25.34 Change-Id: Ie2e9ad53afbad931c494beb9c02de1f717718a37 Signed-off-by: Ng Kin Wai <kin.wai.ng(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h M src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h M src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h M src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h 5 files changed, 461 insertions(+), 454 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/25219/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h index 0dbafff..fca01e9 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h @@ -1,67 +1,67 @@ -/** @file - Header file for Firmware Version Information - - Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved. - - This program and the accompanying materials are licensed and made available under - the terms and conditions of the BSD License which accompanies this distribution. - The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ -#define _FIRMWARE_VERSION_INFO_HOB_H_ - -#include <Uefi/UefiMultiPhase.h> -#include <Pi/PiBootMode.h> -#include <Pi/PiHob.h> - -#pragma pack(1) -/// -/// Firmware Version Structure -/// -typedef struct { - UINT8 MajorVersion; - UINT8 MinorVersion; - UINT8 Revision; - UINT16 BuildNumber; -} FIRMWARE_VERSION; - -/// -/// Firmware Version Information Structure -/// -typedef struct { - UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name - UINT8 VersionStringIndex; ///< Offset 1 Index of Version String - FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version -} FIRMWARE_VERSION_INFO; - -#ifndef __SMBIOS_STANDARD_H__ -/// -/// The Smbios structure header. -/// -typedef struct { - UINT8 Type; - UINT8 Length; - UINT16 Handle; -} SMBIOS_STRUCTURE; -#endif - -/// -/// Firmware Version Information HOB Structure -/// -typedef struct { - EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB - SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB - UINT8 Count; ///< Offset 28 Number of FVI elements included. -/// -/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer -/// -} FIRMWARE_VERSION_INFO_HOB; -#pragma pack() - -#endif // _FIRMWARE_VERSION_INFO_HOB_H_ +/** @file + Header file for Firmware Version Information + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved. + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License which accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ +#define _FIRMWARE_VERSION_INFO_HOB_H_ + +#include <Uefi/UefiMultiPhase.h> +#include <Pi/PiBootMode.h> +#include <Pi/PiHob.h> + +#pragma pack(1) +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} FIRMWARE_VERSION; + +/// +/// Firmware Version Information Structure +/// +typedef struct { + UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name + UINT8 VersionStringIndex; ///< Offset 1 Index of Version String + FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version +} FIRMWARE_VERSION_INFO; + +#ifndef __SMBIOS_STANDARD_H__ +/// +/// The Smbios structure header. +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Handle; +} SMBIOS_STRUCTURE; +#endif + +/// +/// Firmware Version Information HOB Structure +/// +typedef struct { + EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB + SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB + UINT8 Count; ///< Offset 28 Number of FVI elements included. +/// +/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer +/// +} FIRMWARE_VERSION_INFO_HOB; +#pragma pack() + +#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h index feb2022..ae25814 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h @@ -37,11 +37,11 @@ #pragma pack(1) -#define FSPT_UPD_SIGNATURE 0x545F4450554C4E43 /* 'CNLUPD_T' */ +#define FSPT_UPD_SIGNATURE 0x545F4450554C4643 /* 'CFLUPD_T' */ -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4E43 /* 'CNLUPD_M' */ +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4643 /* 'CFLUPD_M' */ -#define FSPS_UPD_SIGNATURE 0x535F4450554C4E43 /* 'CNLUPD_S' */ +#define FSPS_UPD_SIGNATURE 0x535F4450554C4643 /* 'CFLUPD_S' */ #pragma pack() diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h index d014f81..a147f4f 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h @@ -37,19 +37,19 @@ #pragma pack(1) - -#include <MemInfoHob.h> - -/// -/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. -/// -typedef struct { - UINT8 Revision; ///< Chipset Init Info Revision - UINT8 Rsvd[3]; ///< Reserved - UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table - UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table -} CHIPSET_INIT_INFO; - + +#include <MemInfoHob.h> + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + /** Fsp M Configuration **/ @@ -182,9 +182,15 @@ **/ UINT8 ProbelessTrace; -/** Offset 0x00A3 +/** Offset 0x00A3 - GDXC IOT SIZE + Size of IOT and MOT is in 8 MB chunks **/ - UINT8 UnusedUpdSpace0[2]; + UINT8 GdxcIotSize; + +/** Offset 0x00A4 - GDXC MOT SIZE + Size of IOT and MOT is in 8 MB chunks +**/ + UINT8 GdxcMotSize; /** Offset 0x00A5 - Enable SMBus Enable/disable SMBus controller. @@ -244,9 +250,7 @@ /** Offset 0x00B8 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics. - 0x00:0MB, 0x01:32MB, 0x02:64MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, - 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, - 0xFD:56MB, 0xFE:60MB + 0x00:0 MB, 0x01:32 MB, 0x02:64 MB **/ UINT8 IgdDvmt50PreAlloc; @@ -272,14 +276,14 @@ /** Offset 0x00BC - SA GV System Agent dynamic frequency support and when enabled memory will be training at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, - 2=FixedMid, 3=FixedHigh, and 4=Enabled. - 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled + 2=FixedHigh, and 3=Enabled. + 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled **/ UINT8 SaGv; /** Offset 0x00BD **/ - UINT8 UnusedUpdSpace1; + UINT8 UnusedUpdSpace0; /** Offset 0x00BE - DDR Frequency Limit Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, @@ -329,7 +333,7 @@ /** Offset 0x00C8 **/ - UINT8 UnusedUpdSpace2[16]; + UINT8 UnusedUpdSpace1[16]; /** Offset 0x00D8 - SPD Profile Selected Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP @@ -488,7 +492,7 @@ /** Offset 0x00F8 **/ - UINT8 UnusedUpdSpace3[4]; + UINT8 UnusedUpdSpace2[4]; /** Offset 0x00FC - Enable Intel HD Audio (Azalia) 0: Disable, 1: Enable (Default) Azalia controller @@ -510,7 +514,7 @@ /** Offset 0x00FF **/ - UINT8 UnusedUpdSpace4; + UINT8 UnusedUpdSpace3; /** Offset 0x0100 - HECI1 BAR address BAR address of HECI1 @@ -681,7 +685,7 @@ /** Offset 0x0125 **/ - UINT8 UnusedUpdSpace5[3]; + UINT8 UnusedUpdSpace4[3]; /** Offset 0x0128 - DMI Gen3 Root port preset values per lane Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane @@ -720,7 +724,7 @@ /** Offset 0x0146 **/ - UINT8 UnusedUpdSpace6[2]; + UINT8 UnusedUpdSpace5[2]; /** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control Range: 0-15, 12 is default for each bundle, must be specified based upon platform design @@ -957,7 +961,7 @@ /** Offset 0x0207 **/ - UINT8 UnusedUpdSpace7; + UINT8 UnusedUpdSpace6; /** Offset 0x0208 - Maximum clr turbo ratio override Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the @@ -1112,7 +1116,7 @@ /** Offset 0x0227 **/ - UINT8 UnusedUpdSpace8; + UINT8 UnusedUpdSpace7; /** Offset 0x0228 - PrmrrSize 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000 @@ -2275,25 +2279,16 @@ **/ UINT8 EnBER; -/** Offset 0x050F - PEG IMR support - This option configures the IMR support for PEG.(def=Disable) - $EN_DIS +/** Offset 0x050F - Dual Dimm Per-Channel Board Type + Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used + to limit maximum frequency for some SKUs. + 0:1DPC, 1:2DPC **/ - UINT8 PegImrEnable; + UINT8 DualDimmPerChannelBoardType; -/** Offset 0x0510 - PEG IMR size - The size of IMR to be allocated for PEG EndPoint device +/** Offset 0x0510 **/ - UINT16 PegImrSize; - -/** Offset 0x0512 - PEG Root Port Selection - The Root Port for which the IMR to be allocated -**/ - UINT8 PegImrRpSelection; - -/** Offset 0x0513 -**/ - UINT8 ReservedFspmUpd[12]; + UINT8 ReservedFspmUpd[15]; } FSP_M_CONFIG; /** Fsp M Test Configuration @@ -2518,7 +2513,7 @@ /** Offset 0x0579 **/ - UINT8 UnusedUpdSpace10; + UINT8 UnusedUpdSpace9; /** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 1000. @warning Do not change from the default @@ -2793,7 +2788,7 @@ /** Offset 0x051F **/ - UINT8 UnusedUpdSpace9; + UINT8 UnusedUpdSpace8; /** Offset 0x0520 **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h index 0f3577a..5725dd3 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h @@ -37,49 +37,49 @@ #pragma pack(1) - -/// -/// Azalia Header structure -/// -typedef struct { - UINT16 VendorId; ///< Codec Vendor ID - UINT16 DeviceId; ///< Codec Device ID - UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. - UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. - UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. - UINT32 Reserved; ///< Reserved for future use. Must be set to 0. -} AZALIA_HEADER; - -/// -/// Audio Azalia Verb Table structure -/// -typedef struct { - AZALIA_HEADER Header; ///< AZALIA PCH header - UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header -} AUDIO_AZALIA_VERB_TABLE; - -/// -/// Refer to the definition of PCH_INT_PIN -/// -typedef enum { - SiPchNoInt, ///< No Interrupt Pin - SiPchIntA, - SiPchIntB, - SiPchIntC, - SiPchIntD -} SI_PCH_INT_PIN; -/// -/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. -/// -typedef struct { - UINT8 Device; ///< Device number - UINT8 Function; ///< Device function - UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) - UINT8 Irq; ///< IRQ to be set for device. -} SI_PCH_DEVICE_INTERRUPT_CONFIG; - -#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices - + +/// +/// Azalia Header structure +/// +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. + UINT32 Reserved; ///< Reserved for future use. Must be set to 0. +} AZALIA_HEADER; + +/// +/// Audio Azalia Verb Table structure +/// +typedef struct { + AZALIA_HEADER Header; ///< AZALIA PCH header + UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + /** Fsp S Configuration **/ @@ -717,8 +717,8 @@ UINT8 PavpEnable; /** Offset 0x0217 - CdClock Frequency selection - 0=168 Mhz, 1=336 Mhz, 2(Default)=528 Mhz - 0: 168 Mhz, 1: 336 Mhz, 2: 528 Mhz + 0=168 Mhz, 1=336 Mhz, 2=528 Mhz, 3(Default)=675 Mhz + 0: 168 Mhz, 1: 336 Mhz, 2: 528 Mhz, 3: 675 Mhz **/ UINT8 CdClock; @@ -2335,7 +2335,7 @@ UINT8 PmSupport; /** Offset 0x07BC - Enable/Disable CdynmaxClamp - Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp + Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp $EN_DIS **/ UINT8 CdynmaxClampEnable; @@ -2784,8 +2784,8 @@ UINT8 CstateLatencyControl5TimeUnit; /** Offset 0x0819 - Interrupt Redirection Mode Select - Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7: - No change. + Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: + PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change. **/ UINT8 PpmIrmSetting; @@ -3032,11 +3032,23 @@ **/ UINT8 MaxRingRatioLimit; -/** Offset 0x08A5 - ReservedCpuPostMemTest +/** Offset 0x08A5 - Enable or Disable C3 Cstate Demotion + Enable or Disable C3 Cstate Demotion. Disable; 1: Enable + $EN_DIS +**/ + UINT8 C3StateAutoDemotion; + +/** Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion + Enable or Disable C3 Cstate UnDemotion. Disable; 1: Enable + $EN_DIS +**/ + UINT8 C3StateUnDemotion; + +/** Offset 0x08A7 - ReservedCpuPostMemTest Reserved for CPU Post-Mem Test $EN_DIS **/ - UINT8 ReservedCpuPostMemTest[21]; + UINT8 ReservedCpuPostMemTest[19]; /** Offset 0x08BA - SgxSinitDataFromTpm SgxSinitDataFromTpm default values diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h index 941a891..e2a3e09 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h @@ -1,288 +1,288 @@ -/** @file - This file contains definitions required for creation of - Memory S3 Save data, Memory Info data and Memory Platform - data hobs. - -@copyright - INTEL CONFIDENTIAL - Copyright 1999 - 2018 Intel Corporation. - - The source code contained or described herein and all documents related to the - source code ("Material") are owned by Intel Corporation or its suppliers or - licensors. Title to the Material remains with Intel Corporation or its suppliers - and licensors. The Material may contain trade secrets and proprietary and - confidential information of Intel Corporation and its suppliers and licensors, - and is protected by worldwide copyright and trade secret laws and treaty - provisions. No part of the Material may be used, copied, reproduced, modified, - published, uploaded, posted, transmitted, distributed, or disclosed in any way - without Intel's prior express written permission. - - No license under any patent, copyright, trade secret or other intellectual - property right is granted to or conferred upon you by disclosure or delivery - of the Materials, either expressly, by implication, inducement, estoppel or - otherwise. Any license under such intellectual property rights must be - express and approved by Intel in writing. - - Unless otherwise agreed by Intel in writing, you may not remove or alter - this notice or any other notice embedded in Materials by Intel or - Intel's suppliers or licensors in any way. - - This file contains an 'Intel Peripheral Driver' and is uniquely identified as - "Intel Reference Module" and is licensed for Intel CPUs and chipsets under - the terms of your license agreement with Intel or your vendor. This file may - be modified by the user, subject to additional terms of the license agreement. - -@par Specification Reference: -**/ -#ifndef _MEM_INFO_HOB_H_ -#define _MEM_INFO_HOB_H_ - -#include <Uefi/UefiMultiPhase.h> -#include <Pi/PiBootMode.h> -#include <Pi/PiHob.h> - -#pragma pack (push, 1) - -extern EFI_GUID gSiMemoryS3DataGuid; -extern EFI_GUID gSiMemoryInfoDataGuid; -extern EFI_GUID gSiMemoryPlatformDataGuid; - -#define MAX_NODE 1 -#define MAX_CH 2 -#define MAX_DIMM 2 - -/// -/// Host reset states from MRC. -/// -#define WARM_BOOT 2 - -#define R_MC_CHNL_RANK_PRESENT 0x7C -#define B_RANK0_PRS BIT0 -#define B_RANK1_PRS BIT1 -#define B_RANK2_PRS BIT4 -#define B_RANK3_PRS BIT5 - -/// -/// Defines taken from MRC so avoid having to include MrcInterface.h -/// - -// -// Matches MAX_SPD_SAVE define in MRC -// -#ifndef MAX_SPD_SAVE -#define MAX_SPD_SAVE 29 -#endif - -// -// MRC version description. -// -typedef struct { - UINT8 Major; ///< Major version number - UINT8 Minor; ///< Minor version number - UINT8 Rev; ///< Revision number - UINT8 Build; ///< Build number -} SiMrcVersion; - -// -// Matches MrcChannelSts enum in MRC -// -#ifndef CHANNEL_NOT_PRESENT -#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. -#endif -#ifndef CHANNEL_DISABLED -#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. -#endif -#ifndef CHANNEL_PRESENT -#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. -#endif - -// -// Matches MrcDimmSts enum in MRC -// -#ifndef DIMM_ENABLED -#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. -#endif -#ifndef DIMM_DISABLED -#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. -#endif -#ifndef DIMM_PRESENT -#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. -#endif -#ifndef DIMM_NOT_PRESENT -#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. -#endif - -// -// Matches MrcBootMode enum in MRC -// -#ifndef bmCold -#define bmCold 0 // Cold boot -#endif -#ifndef bmWarm -#define bmWarm 1 // Warm boot -#endif -#ifndef bmS3 -#define bmS3 2 // S3 resume -#endif -#ifndef bmFast -#define bmFast 3 // Fast boot -#endif - -// -// Matches MrcDdrType enum in MRC -// -#ifndef MRC_DDR_TYPE_DDR4 -#define MRC_DDR_TYPE_DDR4 0 -#endif -#ifndef MRC_DDR_TYPE_DDR3 -#define MRC_DDR_TYPE_DDR3 1 -#endif -#ifndef MRC_DDR_TYPE_LPDDR3 -#define MRC_DDR_TYPE_LPDDR3 2 -#endif -#ifndef CPU_CFL//CNL -#ifndef MRC_DDR_TYPE_LPDDR4 -#define MRC_DDR_TYPE_LPDDR4 3 -#endif -#else//CFL -#ifndef MRC_DDR_TYPE_UNKNOWN -#define MRC_DDR_TYPE_UNKNOWN 3 -#endif -#endif//CPU_CFL-endif - -#define MAX_PROFILE_NUM 4 // number of memory profiles supported -#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported - -// -// DIMM timings -// -typedef struct { - UINT32 tCK; ///< Memory cycle time, in femtoseconds. - UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. - UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. - UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. - UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. - UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. - UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. - UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. - UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. - UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. - UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. - UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. - UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. - UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. - UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. - UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. - UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. - UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. - UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. -} MRC_CH_TIMING; - -typedef struct { - UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group. - UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups. - UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM). - UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs. -} MRC_TA_TIMING; - -/// -/// Memory SMBIOS & OC Memory Data Hob -/// -typedef struct { - UINT8 Status; ///< See MrcDimmStatus for the definition of this field. - UINT8 DimmId; - UINT32 DimmCapacity; ///< DIMM size in MBytes. - UINT16 MfgId; - UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes - UINT8 RankInDimm; ///< The number of ranks in this DIMM. - UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. - UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. - UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. - UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. -} DIMM_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this channel should be used. - UINT8 ChannelId; - UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. - MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. - DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. -} CHANNEL_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this controller should be used. - UINT16 DeviceId; ///< The PCI device id of this memory controller. - UINT8 RevisionId; ///< The PCI revision id of this memory controller. - UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. - CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. - MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings - MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings - MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings - MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings -} CONTROLLER_INFO; - -typedef struct { - UINT8 Revision; - UINT16 DataWidth; ///< Data width, in bits, of this memory device - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 - UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) - UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - - SiMrcVersion Version; - BOOLEAN EccSupport; - UINT8 MemoryProfile; - UINT32 TotalPhysicalMemorySize; - UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. - UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. - UINT8 Ratio; - UINT8 RefClk; - UINT32 VddVoltage[MAX_PROFILE_NUM]; - CONTROLLER_INFO Controller[MAX_NODE]; -} MEMORY_INFO_DATA_HOB; - -/** - Memory Platform Data Hob - - Revision 1: - - Initial version. - Revision 2: - - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields -**/ -typedef struct { - UINT8 Revision; - UINT8 Reserved[3]; - UINT32 BootMode; - UINT32 TsegSize; - UINT32 TsegBase; - UINT32 PrmrrSize; - UINT32 PrmrrBase; - UINT32 GttBase; - UINT32 MmioSize; - UINT32 PciEBaseAddress; -#ifdef CPU_CFL - UINT32 GdxcIotBase; - UINT32 GdxcIotSize; - UINT32 GdxcMotBase; - UINT32 GdxcMotSize; -#endif //CPU_CFL -} MEMORY_PLATFORM_DATA; - -typedef struct { - EFI_HOB_GUID_TYPE EfiHobGuidType; - MEMORY_PLATFORM_DATA Data; - UINT8 *Buffer; -} MEMORY_PLATFORM_DATA_HOB; - -#pragma pack (pop) - -#endif // _MEM_INFO_HOB_H_ +/** @file + This file contains definitions required for creation of + Memory S3 Save data, Memory Info data and Memory Platform + data hobs. + +@copyright + INTEL CONFIDENTIAL + Copyright 1999 - 2018 Intel Corporation. + + The source code contained or described herein and all documents related to the + source code ("Material") are owned by Intel Corporation or its suppliers or + licensors. Title to the Material remains with Intel Corporation or its suppliers + and licensors. The Material may contain trade secrets and proprietary and + confidential information of Intel Corporation and its suppliers and licensors, + and is protected by worldwide copyright and trade secret laws and treaty + provisions. No part of the Material may be used, copied, reproduced, modified, + published, uploaded, posted, transmitted, distributed, or disclosed in any way + without Intel's prior express written permission. + + No license under any patent, copyright, trade secret or other intellectual + property right is granted to or conferred upon you by disclosure or delivery + of the Materials, either expressly, by implication, inducement, estoppel or + otherwise. Any license under such intellectual property rights must be + express and approved by Intel in writing. + + Unless otherwise agreed by Intel in writing, you may not remove or alter + this notice or any other notice embedded in Materials by Intel or + Intel's suppliers or licensors in any way. + + This file contains an 'Intel Peripheral Driver' and is uniquely identified as + "Intel Reference Module" and is licensed for Intel CPUs and chipsets under + the terms of your license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the license agreement. + +@par Specification Reference: +**/ +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + +#include <Uefi/UefiMultiPhase.h> +#include <Pi/PiBootMode.h> +#include <Pi/PiHob.h> + +#pragma pack (push, 1) + +extern EFI_GUID gSiMemoryS3DataGuid; +extern EFI_GUID gSiMemoryInfoDataGuid; +extern EFI_GUID gSiMemoryPlatformDataGuid; + +#define MAX_NODE 1 +#define MAX_CH 2 +#define MAX_DIMM 2 + +/// +/// Host reset states from MRC. +/// +#define WARM_BOOT 2 + +#define R_MC_CHNL_RANK_PRESENT 0x7C +#define B_RANK0_PRS BIT0 +#define B_RANK1_PRS BIT1 +#define B_RANK2_PRS BIT4 +#define B_RANK3_PRS BIT5 + +/// +/// Defines taken from MRC so avoid having to include MrcInterface.h +/// + +// +// Matches MAX_SPD_SAVE define in MRC +// +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE 29 +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; + +// +// Matches MrcChannelSts enum in MRC +// +#ifndef CHANNEL_NOT_PRESENT +#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. +#endif +#ifndef CHANNEL_DISABLED +#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. +#endif +#ifndef CHANNEL_PRESENT +#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. +#endif + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. +#endif + +// +// Matches MrcBootMode enum in MRC +// +#ifndef bmCold +#define bmCold 0 // Cold boot +#endif +#ifndef bmWarm +#define bmWarm 1 // Warm boot +#endif +#ifndef bmS3 +#define bmS3 2 // S3 resume +#endif +#ifndef bmFast +#define bmFast 3 // Fast boot +#endif + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_DDR4 +#define MRC_DDR_TYPE_DDR4 0 +#endif +#ifndef MRC_DDR_TYPE_DDR3 +#define MRC_DDR_TYPE_DDR3 1 +#endif +#ifndef MRC_DDR_TYPE_LPDDR3 +#define MRC_DDR_TYPE_LPDDR3 2 +#endif +#ifndef CPU_CFL//CNL +#ifndef MRC_DDR_TYPE_LPDDR4 +#define MRC_DDR_TYPE_LPDDR4 3 +#endif +#else//CFL +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 3 +#endif +#endif//CPU_CFL-endif + +#define MAX_PROFILE_NUM 4 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported + +// +// DIMM timings +// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. + UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. +} MRC_CH_TIMING; + +typedef struct { + UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group. + UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups. + UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM). + UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs. +} MRC_TA_TIMING; + +/// +/// Memory SMBIOS & OC Memory Data Hob +/// +typedef struct { + UINT8 Status; ///< See MrcDimmStatus for the definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT16 MfgId; + UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + UINT8 RankInDimm; ///< The number of ranks in this DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. +} DIMM_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this channel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. +} CHANNEL_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this controller should be used. + UINT16 DeviceId; ///< The PCI device id of this memory controller. + UINT8 RevisionId; ///< The PCI revision id of this memory controller. + UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. + MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings + MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings + MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings + MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings +} CONTROLLER_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; ///< Data width, in bits, of this memory device + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 + UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + + SiMrcVersion Version; + BOOLEAN EccSupport; + UINT8 MemoryProfile; + UINT32 TotalPhysicalMemorySize; + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + UINT8 Ratio; + UINT8 RefClk; + UINT32 VddVoltage[MAX_PROFILE_NUM]; + CONTROLLER_INFO Controller[MAX_NODE]; +} MEMORY_INFO_DATA_HOB; + +/** + Memory Platform Data Hob + + Revision 1: + - Initial version. + Revision 2: + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields +**/ +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; + UINT32 TsegBase; + UINT32 PrmrrSize; + UINT32 PrmrrBase; + UINT32 GttBase; + UINT32 MmioSize; + UINT32 PciEBaseAddress; +#ifdef CPU_CFL + UINT32 GdxcIotBase; + UINT32 GdxcIotSize; + UINT32 GdxcMotBase; + UINT32 GdxcMotSize; +#endif //CPU_CFL +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; + +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_ -- To view, visit https://review.coreboot.org/25219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie2e9ad53afbad931c494beb9c02de1f717718a37 Gerrit-Change-Number: 25219 Gerrit-PatchSet: 1 Gerrit-Owner: Kin Wai Ng <kin.wai.ng(a)intel.com>

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Change in coreboot[master]: mainboard/hp: Add Elitebook Folio 9470m
by build bot (Jenkins) (Code Review) 16 Mar '18

16 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25218 ) Change subject: mainboard/hp: Add Elitebook Folio 9470m ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23063/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68667/ : SUCCESS -- To view, visit https://review.coreboot.org/25218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I52e549ec18e8aa661a506a16dbc7f83417c0da78 Gerrit-Change-Number: 25218 Gerrit-PatchSet: 2 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Mar 2018 09:17:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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