coreboot-gerrit March 2018

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Change in coreboot[master]: soc/intel/coffeelake: Include Coffeelake Device Ids
by build bot (Jenkins) (Code Review) 16 Mar '18

16 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25224 ) Change subject: soc/intel/coffeelake: Include Coffeelake Device Ids ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/68672/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23069/ : SUCCESS -- To view, visit https://review.coreboot.org/25224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia8417199205c26b9147f7b04a2418ca22ffc188b Gerrit-Change-Number: 25224 Gerrit-PatchSet: 1 Gerrit-Owner: Kin Wai Ng <kin.wai.ng(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Mar 2018 13:39:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: fsp/fsp2_0/coffeelake: Add CFL FSP UPD Headers to ver 7.0.25.34
by build bot (Jenkins) (Code Review) 16 Mar '18

16 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25219 ) Change subject: fsp/fsp2_0/coffeelake: Add CFL FSP UPD Headers to ver 7.0.25.34 ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23067/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68671/ : SUCCESS -- To view, visit https://review.coreboot.org/25219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie2e9ad53afbad931c494beb9c02de1f717718a37 Gerrit-Change-Number: 25219 Gerrit-PatchSet: 3 Gerrit-Owner: Kin Wai Ng <kin.wai.ng(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Mar 2018 13:37:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Remove unused Maxim Audio Device
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

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Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Remove unused i2c devices
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

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Change in coreboot[master]: soc/intel/coffeelake: Add Intel Bootsplash Logo
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

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Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Enable USB2_P7 and USB2_P8
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

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Change in coreboot[master]: intel/coffeelake: Fix up GPIO pad mappings to Coffee Lake H RVP11
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

Hello Naresh Solanki, Subrata Banik, Balaji Manigandan, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, I'd like you to do a code review. Please visit https://review.coreboot.org/25241 to review the following change. Change subject: intel/coffeelake: Fix up GPIO pad mappings to Coffee Lake H RVP11 ...................................................................... intel/coffeelake: Fix up GPIO pad mappings to Coffee Lake H RVP11 1. Fixing GPIO pad mappings also resolves reboot issues in UEFI shell and Yocto. 2. Fix up ACPI GPIO device for CFL-H Change-Id: I3acf0a0e3101eadb3464baf8e1a7ba5b32804777 Signed-off-by: Ng Kin Wai <kin.wai.ng(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c M src/soc/intel/coffeelake/acpi/gpio.asl M src/soc/intel/coffeelake/gpio.c M src/soc/intel/coffeelake/include/soc/gpio.h M src/soc/intel/coffeelake/include/soc/gpio_defs.h M src/soc/intel/coffeelake/include/soc/gpio_soc_defs.h 6 files changed, 547 insertions(+), 604 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/25241/1 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c old mode 100644 new mode 100755 index 44632e9..f62a891 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -19,276 +19,194 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { - /* GPPC */ - /* A0 : RCINB_TIME_SYNC_1 */ - /* A1 : ESPI_IO_0 */ - /* A2 : ESPI_IO_1 */ - /* A3 : ESPI_IO_2 */ - /* A4 : ESPI_IO_3 */ - /* A5 : ESPI_CSB */ - /* A6 : SERIRQ */ - /* A7 : PRIQAB_GSP10_CS1B */ - PAD_CFG_GPI_SCI_HIGH(GPP_A7, UP_20K, DEEP, EDGE_SINGLE), - /* A8 : CLKRUNB */ - PAD_CFG_GPO(GPP_A8, 1, PLTRST), - /* A9 : CLKOUT_LPC_0_ESPI_CLK */ - /* A10 : CLKOUT_LPC_1 */ - /* A11 : PMEB_GSP11_CS1B */ - PAD_CFG_GPI_SCI_LOW(GPP_A11, UP_20K, DEEP, LEVEL), - /* A12 : BM_BUSYB_ISH__GP_6 */ - /* A13 : SUSWARNB_SUSPWRDNACK */ - PAD_CFG_GPO(GPP_A13, 1, PLTRST), - /* A14 : SUS_STATB_ESPI_RESETB */ - /* A15 : SUSACKB */ - PAD_CFG_GPO(GPP_A15, 1, PLTRST), - /* A16 : SD_1P8_SEL */ - PAD_CFG_GPO(GPP_A16, 0, PLTRST), - /* A17 : SD_VDD1_PWR_EN_B_ISH_GP_7 */ - /* A18 : ISH_GP_0 */ - PAD_CFG_NF(GPP_A18, UP_20K, DEEP, NF1), - /* A19 : ISH_GP_1 */ - PAD_CFG_NF(GPP_A19, UP_20K, DEEP, NF1), - /* A20 : aduio codec irq */ - PAD_CFG_GPI_APIC_LOW(GPP_A20, NONE, DEEP), - /* A21 : ISH_GP_3 */ - PAD_CFG_NF(GPP_A21, UP_20K, DEEP, NF1), - /* A22 : ISH_GP_4 */ - PAD_CFG_NF(GPP_A22, UP_20K, DEEP, NF1), - /* A23 : ISH_GP_5 */ - PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1), - /* B0 : CORE_VID_0 */ - /* B1 : CORE_VID_1 */ - /* B2 : VRALERTB */ - PAD_CFG_GPI_APIC(GPP_B2, NONE, DEEP, LEVEL, NONE), - /* B3 : CPU_GP_2 */ - PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, LEVEL, NONE), - /* B4 : CPU_GP_3 */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), - /* B5 : SRCCLKREQB_0 */ - /* B6 : SRCCLKREQB_1 */ - /* B7 : SRCCLKREQB_2 */ - /* B8 : SRCCLKREQB_3 */ - /* B9 : SRCCLKREQB_4 */ - /* B10 : SRCCLKREQB_5 */ - /* B11 : EXT_PWR_GATEB */ - PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), - /* B12 : SLP_S0B */ - /* B13 : PLTRSTB */ - /* B14 : SPKR */ - PAD_CFG_GPO(GPP_B14, 1, PLTRST), - /* B15 : GSPI0_CS0B */ - PAD_CFG_GPO(GPP_B15, 0, DEEP), - /* B16 : GSPI0_CLK */ - PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST, LEVEL, NONE), - /* B17 : GSPI0_MISO */ - PAD_CFG_GPO(GPP_B17, 1, PLTRST), - /* B18 : GSPI0_MOSI */ - PAD_CFG_GPO(GPP_B18, 1, PLTRST), - /* B19 : GSPI1_CS0B */ - /* B20 : GSPI1_CLK_NFC_CLK */ - /* B21 : GSPI1_MISO_NFC_CLKREQ */ - /* B22 : GSP1_MOSI */ - /* B23 : SML1ALERTB_PCHHOTB */ - PAD_CFG_GPO(GPP_B23, 1, DEEP), + // Gpio's for Audio + PAD_CFG_GPI_APIC_LOW(GPP_A11, UP_20K, PLTRST), // I2S_CODEC_INT + //GPP_B11 // SSP_MCLK + //GPP_D17 // DMIC_CLK_1 + //GPP_D18 // DMIC_DATA_1 + //GPP_D19 // DMIC_CLK_0 + //GPP_D20 // DMIC_DATA_0 + PAD_CFG_GPO(GPP_H10, 1, PLTRST), // Audio Power Enable + PAD_CFG_GPO(GPP_J11, 1, PLTRST), // SPEAKER PD - /* C0 : SMBCLK */ - /* C1 : SMBDATA */ - /* C2 : SMBALERTB */ - PAD_CFG_GPO(GPP_C2, 1, DEEP), - /* C3 : SML0CLK */ - /* C4 : SML0DATA */ - /* C5 : SML0ALERTB */ - PAD_CFG_GPI_SCI_LOW(GPP_C5, NONE, DEEP, LEVEL), - /* C6 : SML1CLK */ - /* C7 : SML1DATA */ - /* C8 : UART0_RXD */ - PAD_CFG_GPI_APIC(GPP_C8, UP_20K, DEEP, LEVEL, INVERT), - /* C9 : UART0_TXD */ - PAD_CFG_GPI_SCI_LOW(GPP_C9, UP_20K, PLTRST, EDGE_SINGLE), - /* C10 : UART0_RTSB */ - PAD_CFG_GPO(GPP_C10, 0, PLTRST), - /* C11 : UART0_CTSB */ - PAD_CFG_GPI_SCI_LOW(GPP_C11, UP_20K, DEEP, LEVEL), - /* C12 : UART1_RXD_ISH_UART1_RXD */ - PAD_CFG_GPO(GPP_C12, 1, PLTRST), - /* C13 : UART1_RXD_ISH_UART1_TXD */ - /* C14 : UART1_RXD_ISH_UART1_RTSB */ - /* C15 : UART1_RXD_ISH_UART1_CTSB */ - PAD_CFG_GPO(GPP_C15, 1, PLTRST), - /* C16 : I2C0_SDA */ - /* C17 : I2C0_SCL */ - /* C18 : I2C1_SDA */ - /* C19 : I2C1_SCL */ - /* C20 : UART2_RXD */ - /* C21 : UART2_TXD */ - /* C22 : UART2_RTSB */ - /* C23 : UART2_CTSB */ + //Bios Recovery + PAD_CFG_GPI_INT(GPP_F10, NONE, PLTRST, LEVEL), // BIOS_RECOVERY - /* D0 : SPI1_CSB_BK_0 */ - /* D1 : SPI1_CLK_BK_1 */ - /* D2 : SPI1_MISO_IO_1_BK_2 */ - /* D3 : SPI1_MOSI_IO_0_BK_3 */ - /* D4 : IMGCLKOUT_0_BK_4 */ - /* D5 : ISH_I2C0_SDA */ - /* D6 : ISH_I2C0_SCL */ - /* D7 : ISH_I2C1_SDA */ - /* D8 : ISH_I2C1_SCL */ - /* D9 : ISH_SPI_CSB */ - PAD_CFG_GPO(GPP_D9, 1, PLTRST), - /* D10 : ISH_SPI_CLK */ - PAD_CFG_GPI_APIC(GPP_D10, NONE, PLTRST, EDGE_SINGLE, NONE), - /* D11 : ISH_SPI_MISO_GP_BSSB_CLK */ - PAD_CFG_GPI_SCI_LOW(GPP_D11, NONE, DEEP, LEVEL), - /* D12 : ISH_SPI_MOSI_GP_BSSB_DI */ - /* D13 : ISH_UART0_RXD_SML0BDATA */ - PAD_CFG_GPO(GPP_D13, 1, DEEP), - /* D14 : ISH_UART0_TXD_SML0BCLK */ - PAD_CFG_GPO(GPP_D14, 1, PLTRST), - /* D15 : ISH_UART0_RTSB_GPSPI2_CS1B */ - /* D16 : ISH_UART0_CTSB_SML0BALERTB */ - PAD_CFG_GPI_SCI_HIGH(GPP_D16, NONE, DEEP, LEVEL), - /* D17 : DMIC_CLK_1_SNDW3_CLK */ - PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1), - /* D18 : DMIC_DATA_1_SNDW3_DATA */ - PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1), - /* D19 : DMIC_CLK_0_SNDW4_CLK */ - PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1), - /* D20 : DMIC_DATA_0_SNDW4_DATA */ - PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1), - /* D21 : SPI1_IO_2 */ - PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1), - /* D22 : SPI1_IO_3 */ - PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1), - /* D23 : SPP_MCLK */ - PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), - /* E0 : SATAXPCIE_0_SATAGP_0 */ -#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) - PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1), -#endif - /* E1 : SATAXPCIE_1_SATAGP_1 */ - /* E2 : SATAXPCIE_2_SATAGP_2 */ - PAD_CFG_GPI(GPP_E2, UP_20K, PLTRST), - /* E3 : CPU_GP_0 */ - PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE), - /* E4 : SATA_DEVSLP_0 */ - PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP_1 */ - /* E6 : SATA_DEVSLP_2 */ - PAD_CFG_GPI_SCI(GPP_E6, NONE, DEEP, OFF, NONE), - /* E7 : CPU_GP_1 */ - PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, EDGE_SINGLE), - /* E8 : SATA_LEDB */ - /* E9 : USB2_OCB_0_GP_BSSB_CLK */ - /* E10 : USB2_OCB_1_GP_BSSB_DI */ - /* E11 : USB2_OCB_2 */ - /* E12 : USB2_OCB_3 */ - /* E13 : DDSP_HPD_0_DISP_MISC_0 */ - /* E14 : DDSP_HPD_0_DISP_MISC_1 */ - /* E15 : DDSP_HPD_0_DISP_MISC_2 */ - /* E16 : EMMC_EN */ - PAD_CFG_GPO(GPP_E16, 1, PLTRST), - /* E17 : EDP_HPD_DISP_MISC_4 */ - /* E18 : DDPB_CTRLCLK */ - /* E19 : DDPB_CTRLDATA */ - /* E20 : DDPC_CTRLCLK */ - /* E21 : DDPC_CTRLDATA */ - /* E22 : DDPD_CTRLCLK */ - /* E23 : DDPD_CTRLDATA */ + //CSME + PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, LEVEL), // ME_PG_LED - /* F0 : CNV_GNSS_PA_BLANKING */ - PAD_CFG_GPI(GPP_F0, NONE, PLTRST), - /* F1 : CNV_GNSS_FAT */ - PAD_CFG_TERM_GPO(GPP_F1, 1, UP_20K, DEEP), - /* F2 : CNV_GNSS_SYSCK */ - PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST), - /* F3 : GPP_F_3 */ - PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST), - /* F4 : CNV_BRI_DT_UART0_RTSB */ - /* F5 : CNV_BRI_RSP_UART0_RXD */ - /* F6 : CNV_RGI_DT_UART0_TXD */ - /* F7 : CNV_RGI_DT_RSP_UART9_CTSB */ - /* F8 : CNV_MFUART2_RXD */ - PAD_CFG_NF(GPP_F8, UP_20K, DEEP, NF1), - /* F9 : CNV_MFUART2_TXD */ - PAD_CFG_NF(GPP_F9, UP_20K, DEEP, NF1), - /* F10 : GPP_F_10 */ - PAD_CFG_GPO(GPP_F10, 1, PLTRST), - /* F11 : EMMC_CMD */ - /* F12 : EMMC_DATA0 */ - /* F13 : EMMC_DATA1 */ - /* F14 : EMMC_DATA2 */ - /* F15 : EMMC_DATA3 */ - /* F16 : EMMC_DATA4 */ - /* F17 : EMMC_DATA5 */ - /* F18 : EMMC_DATA6 */ - /* F19 : EMMC_DATA9 */ - /* F20 : EMMC_RCLK */ - /* F21 : EMMC_CLK */ - /* F22 : EMMC_RESETB */ - /* F23 : BIOS_REC */ - PAD_CFG_GPI(GPP_F23, UP_20K, DEEP), - /* G0 : SD3_D2 */ - /* G1 : SD3_D0_SD4_RCLK_P */ - /* G2 : SD3_D1_SD4_RCLK_N */ - /* G3 : SD3_D2 */ - /* G4 : SD3_D3 */ - /* G5 : SD3_CDB */ - PAD_CFG_NF(GPP_G5, UP_20K, DEEP, NF1), - /* G6 : SD3_CLK */ - /* G7 : SD3_WP */ - PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), + //Display + //GPP_I0 // DDSP_HPD_0 + //GPP_I1 // DDSP_HPD_1 + //GPP_I2 // DDSP_HPD_2 + //GPP_I5 // DDI1_CTRL_CLK + //GPP_I6 // DDI1_CTRL_DATA + //GPP_I7 // DDI2_CTRL_CLK + //GPP_I8 // DDI2_CTRL_DATA - /* H0 : SSP2_SCLK */ - /* H1 : SSP2_SFRM */ - /* H2 : SSP2_TXD */ - /* H3 : SSP2_RXD */ - /* H4 : I2C2_SDA */ - /* H5 : I2C2_SCL */ - /* H6 : I2C3_SDA */ - PAD_CFG_NF(GPP_H6, UP_2K, DEEP, NF1), - /* H7 : I2C3_SCL */ - PAD_CFG_NF(GPP_H7, UP_2K, DEEP, NF1), - /* H8 : I2C4_SDA */ - /* H9 : I2C4_SCL */ - /* H10 : I2C5_SDA_ISH_I2C2_SDA */ - PAD_CFG_GPO(GPP_H10, 1, PLTRST), - /* H11 : I2C5_SCL_ISH_I2C2_SCL */ - PAD_CFG_GPO(GPP_H11, 1, PLTRST), - /* H12 : M2_SKT2_CFG_0_DFLEXIO_0 */ - PAD_CFG_GPO(GPP_H12, 1, PLTRST), - /* H13 : M2_SKT2_CFG_1_DFLEXIO_1 */ - PAD_CFG_GPO(GPP_H13, 1, PLTRST), - /* H14 : M2_SKT2_CFG_2 */ - PAD_CFG_GPO(GPP_H14, 0, PLTRST), - /* H15 : M2_SKT2_CFG_3 */ - PAD_CFG_GPO(GPP_H15, 1, PLTRST), - /* H16 : CAM5_PWR_EN */ - PAD_CFG_GPO(GPP_H16, 1, PLTRST), - /* H17 : CAM5_FLASH_STROBE */ - PAD_CFG_GPO(GPP_H17, 1, PLTRST), - /* H18 : BOOTMPC */ - /* H19 : TIMESYNC_0 */ - PAD_CFG_GPO(GPP_H19, 1, PLTRST), - /* H20 : IMGCLKOUT_1 */ - /* H21 : GPPC_H_21 */ - /* H22 : GPPC_H_22 */ - PAD_CFG_GPO(GPP_H22, 1, PLTRST), - /* H23 : GPPC_H_23 */ + //EC + PAD_CFG_GPO(GPP_B23, 1, PLTRST), // EC_SLP_S0_CS_N + //GPP_C6 // SML1_CLK + //GPP_C7 // SML1_DATA + PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE), // EC_SMI_N + PAD_CFG_GPI_SCI_LOW(GPP_K11, UP_20K, PLTRST, LEVEL), // RUNTIME_SCI - /* GPD */ - /* GPD_0 : BATLOWB */ - /* GPD_1 : ACPRESENT */ - /* GPD_2 : LAN_WAKEB */ - /* GPD_3 : PWRBTNB */ - /* GPD_4 : SLP_S3B */ - /* GPD_5 : SLP_S4B */ - /* GPD_6 : SLP_AB */ - /* GPD_7 : GPD_7 */ - /* GPD-8 : SUSCLK */ - /* GPD-9 : SLP_WLANB */ - /* GPD-10 : SLP_5B */ - /* GPD_11 : LANPHYPC */ + //eDP + //GPP_F19 // L_VDDEN + //GPP_F20 // L_BKLTEN + //GPP_F21 // L_BKLTCTL + //GPP_I4 // EDP_HPD + + //FPS + //GPP_D9 // GSPI2_CS_FPS + //GPP_D10 // GSPI2_CLK_FPS + //GPP_D11 // GSPI2_MISO_FPS + //GPP_D12 // GSPI2_MOSI_FPS + PAD_CFG_GPI_APIC(GPP_J2, NONE, PLTRST, EDGE_SINGLE, NONE), // FPS_INT_N + PAD_CFG_GPO(GPP_J3, 1, PLTRST), // FPS_RST_N + + //I2C + //GPP_C16 // I2C0_SDA + //GPP_C17 // I2C0_SCL + // Touch panel + PAD_CFG_GPO(GPP_B18, 1, PLTRST), // I2C_TCH_PNL_PWREN + PAD_CFG_GPI_APIC(GPP_J0, UP_20K, PLTRST, EDGE_SINGLE, INVERT), // I2C_TCH_PNL_INT + PAD_CFG_GPO(GPP_J10, 1, PLTRST), // I2C_TCH_PNL_RST_N + //GPP_D4 // I2C3_SDA + //GPP_D23 // I2C3_SCL + + //LAN + //GPP_C3 // SML0_CLK + //GPP_C4 // SML0_DATA + //GPP_H3 // LAN_CLKREQ + //GPP_D2 // LAN_WAKE + //GPP_D9 // PM_SLP_WLAN_N + //GPP_D11 // LANPHY_EN + + // M.2 BT + PAD_CFG_GPO(GPP_B3, 1, DEEP), // BT_RF_KILL + PAD_CFG_GPI_APIC(GPP_C2, NONE, PLTRST, LEVEL, INVERT), // BT_UART_WAKE + //GPP_D5 // SSP2_SFRM_CNV_RF_RST + //GPP_D6 // SSP2_TXD_MODEM_CKREC + PAD_CFG_GPI_INT(GPP_D7, NONE, PLTRST, LEVEL), // SSP2_RXD + PAD_CFG_GPI_INT(GPP_D8, NONE, PLTRST, LEVEL), // SSP2_SCLK + + // M.2 SSD1 + // De-assert RESET pin + PAD_CFG_GPO(GPP_C14, 1, PLTRST), // SSD1_RESET + //GPP_E1 // SSD1_DET + //GPP_E5 // SSD1_SATA_Devsleep + //GPP_H1 // SSD1_CLKREQ + //GPP_K8 // SSD1_PWREN + + // M.2 SSD2 + // De-assert RESET pin + PAD_CFG_GPO(GPP_C15, 1, PLTRST), // SSD2_RESET + //GPP_F1 // SSD2_PEDET_R + //GPP_H6 // SSD2_CLKREQ + //GPP_K9 // SSD2_PWREN + + // M.2 WiFi + PAD_CFG_GPO(GPP_B4, 1, DEEP), // WIFI_RF_KILL + PAD_CFG_GPI_SCI_LOW(GPP_C5, NONE, DEEP, LEVEL), // WIFI_WAKE_N + //GPP_H0 // WIFI_CLREQ + + // PCIE Flex, X1, X4 + //GPP_B10 // PCIe FLEX + //GPP_B8 // PCIE X1 CLKREQ + // De-assert RESET pin + PAD_CFG_GPO(GPP_F4, 1, PLTRST), // SLOT2_RST_N + //GPP_H5 // PCIE X4 CLKREQ + //GPP_H18 // SLOT2_PWREN + PAD_CFG_GPI_SCI_LOW(GPP_K18, NONE, PLTRST, LEVEL), // SLOT2_WAKE_N + + // PEG Slot + //GPP_F8 // PEG_SLOT_PWREN + // De-assert RESET pin + PAD_CFG_GPO(GPP_F9, 1, PLTRST), // PEG_SLOT_RST + //GPP_F12 // SLOT2_WAKE_N + //GPP_H2 // PCIE X4 CLKREQ + + // PM + //GPP_B12 // PM_SLP_S0_N + //GPP_B13 // PLT_RST_N + + // Power management + //GPD0 // PM_BATLOW_N + //GPD1 // BC_ACOK + //GPD3 // PM_PWRBTN_N + //GPD4 // PM_SLP_S3_N + //GPD5 // PM_SLP_S4_N + //GPD6 // SLP_A_N + //GPD8 // SUS_CLK + //GPD10 // PM_SLP_S5_N + + // SATA + //GPP_E8 // SATA_LED_N + //GPP_F6 // M.2_SSD2_HDD_DEVSLP + //GPP_F2 // SATA_ODD_PRSNT + PAD_CFG_GPO(GPP_K1, 1, PLTRST), // SATA_ODD_PWRGT_R + PAD_CFG_GPI_SCI_HIGH(GPP_K2, NONE, PLTRST, EDGE_SINGLE), // SATA_ODD_DA_N + + // SD Card + PAD_CFG_NF(GPP_G5, UP_20K, DEEP, GPIO), // GPP_G_5_SD3_CDB + PAD_CFG_NF(GPP_G7, UP_20K, DEEP, GPIO), // GPP_G_7_SD3_WP + + // Sensor + //GPP_A12 // Sensor Header + //GPP_A18 // Sensor Header + //GPP_A19 // Sensor Header + //GPP_A20 // Sensor Header + //GPP_A21 // Sensor Header + //GPP_A22 // Sensor Header + //GPP_A23 // Sensor Header + //GPP_H19 // ISH_I2C0_SDA + //GPP_H20 // ISH_I2C0_SCL + //GPP_H21 // ISH_I2C1_SDA + //GPP_H22 // ISH_I2C1_SCL + + // Serial + //GPP_C20 // UART2_RXD + //GPP_C21 // UART2_TXD + //GPP_C22 // UART2_RTS + //GPP_C23 // UART2_CTS + + // SMBUS + //GPP_C0 // SMB_CLK + //GPP_C1 // SMB_DATA + PAD_CFG_GPI_SCI_LOW(GPP_B0, UP_20K, DEEP, EDGE_SINGLE), // SPI_TPM_INIT + + // SPI Touch Panel + //GPP_B14 // SPI1_TCH_PNL_PWREN + //GPP_D0 // SPI1_TCH_PNL_CS0_N + //GPP_D1 // SPI1_TCH_PNL_CLK_N + //GPP_D2 // SPI1_TCH_PNL_MISO + //GPP_D3 // SPI1_TCH_PNL_MOSI + //GPP_D15 // SPI1_TCH_PNL_INT_N + //GPP_D16 // SPI1_TCH_PNL_RST_N + //GPP_D21 // SPI1_TCH_PNL_IO2 + //GPP_D22 // SPI1_TCH_PNL_IO3 + + // TBT + PAD_CFG_GPO(GPP_H16, 1, PLTRST), // TBT_CIO_PWREN + PAD_CFG_GPO(GPP_H17, 0, PLTRST), // TBT_FORCE_PWR + PAD_CFG_GPI_SCI_LOW(GPP_H23, NONE, PLTRST, EDGE_SINGLE), // TBT_CIO_PLUG_EVENT_N + + // Touch pad + PAD_CFG_GPI_APIC(GPP_A16, NONE, PLTRST, LEVEL, INVERT), // TCH_PAD_INT_N + //GPP_D13 // I2C2_SDA + //GPP_D14 // I2C2_SCL + + // USB + //GPP_E9 // USB_OC0 + //GPP_E10 // USB_OC1 + //GPP_E11 // USB_OC2 + //GPP_E12 // USB_OC3 + //GPP_F15 // USB_OC4 + //GPP_F16 // USB_OC5 + //GPP_F17 // USB_OC6 + //GPP_F18 // USB_OC7 }; /* Early pad configuration in bootblock */ diff --git a/src/soc/intel/coffeelake/acpi/gpio.asl b/src/soc/intel/coffeelake/acpi/gpio.asl old mode 100644 new mode 100755 index e20a47d..17c5487 --- a/src/soc/intel/coffeelake/acpi/gpio.asl +++ b/src/soc/intel/coffeelake/acpi/gpio.asl @@ -20,7 +20,7 @@ Device (GPIO) { - Name (_HID, "INT34BB") + Name (_HID, "INT3450") Name (_UID, 0) Name (_DDN, "GPIO Controller") @@ -84,16 +84,16 @@ Method (GADD, 1, NotSerialized) { /* GPIO Community 0 */ - If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPIO_RSVD_11))) + If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23))) { Store (PID_GPIOCOM0, Local0) Subtract (Arg0, GPP_A0, Local1) } /* GPIO Community 1 */ - If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, GPIO_RSVD_52))) + If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_G7))) { Store (PID_GPIOCOM1, Local0) - Subtract (Arg0, GPP_D0, Local1) + Subtract (Arg0, GPP_C0, Local1) } /* GPIO Community 2 */ If (LAnd (LGreaterEqual (Arg0, GPD0), LLessEqual (Arg0, GPD11))) @@ -102,16 +102,16 @@ Subtract (Arg0, GPD0, Local1) } /* GPIO Community 3 */ - If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, GPIO_RSVD_78))) + If (LAnd (LGreaterEqual (Arg0, GPP_K0), LLessEqual (Arg0, GPP_F23))) { - Store (PID_GPIOCOM1, Local0) - Subtract (Arg0, HDA_BCLK, Local1) + Store (PID_GPIOCOM3, Local0) + Subtract (Arg0, GPP_K0, Local1) } - /* GPIO Community 04*/ - If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPIO_RSVD_67))) + /* GPIO Community 4*/ + If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_J11))) { Store (PID_GPIOCOM4, Local0) - Subtract (Arg0, GPP_C0, Local1) + Subtract (Arg0, GPP_I0, Local1) } Store (PCRB (Local0), Local2) Add (Local2, PAD_CFG_BASE, Local2) diff --git a/src/soc/intel/coffeelake/gpio.c b/src/soc/intel/coffeelake/gpio.c old mode 100644 new mode 100755 index ff33cf8..cbb93d8 --- a/src/soc/intel/coffeelake/gpio.c +++ b/src/soc/intel/coffeelake/gpio.c @@ -16,7 +16,6 @@ #include <intelblocks/gpio.h> #include <intelblocks/pcr.h> #include <soc/pcr_ids.h> -#include <soc/pmc.h> static const struct reset_mapping rst_map[] = { { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 }, @@ -32,17 +31,14 @@ }; static const struct pad_group cfl_community0_groups[] = { - INTEL_GPP(GPP_A0, GPP_A0, GPIO_RSVD_0), /* GPP_A */ - INTEL_GPP(GPP_A0, GPP_B0, GPIO_RSVD_2), /* GPP_B */ - INTEL_GPP(GPP_A0, GPP_G0, GPP_G7), /* GPP_G */ - INTEL_GPP(GPP_A0, GPIO_RSVD_3, GPIO_RSVD_11), /* SPI */ + INTEL_GPP(GPP_A0, GPP_A0, GPP_A23), /* GPP_A */ + INTEL_GPP(GPP_A0, GPP_B0, GPP_B23), /* GPP_B */ }; static const struct pad_group cfl_community1_groups[] = { - INTEL_GPP(GPP_D0, GPP_D0, GPIO_RSVD_12), /* GPP_D */ - INTEL_GPP(GPP_D0, GPP_F0, GPP_F23), /* GPP_F */ - INTEL_GPP(GPP_D0, GPP_H0, GPP_H23), /* GPP_H */ - INTEL_GPP(GPP_D0, GPIO_RSVD_12, GPIO_RSVD_52), /* VGPIO */ + INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */ + INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP_D */ + INTEL_GPP(GPP_C0, GPP_G0, GPP_G7), /* GPP_G */ }; static const struct pad_group cfl_community2_groups[] = { @@ -50,45 +46,45 @@ }; static const struct pad_group cfl_community3_groups[] = { - INTEL_GPP(HDA_BCLK, HDA_BCLK, SSP1_TXD), /* AZA */ - INTEL_GPP(HDA_BCLK, GPIO_RSVD_68, GPIO_RSVD_78), /* CPU */ + INTEL_GPP(GPP_K0, GPP_K0, GPP_K23), /* GPP_K */ + INTEL_GPP(GPP_K0, GPP_H0, GPP_H23), /* GPP_H */ + INTEL_GPP(GPP_K0, GPP_E0, GPP_E12), /* GPP_E */ + INTEL_GPP(GPP_K0, GPP_F0, GPP_F23), /* GPP_F */ }; static const struct pad_group cfl_community4_groups[] = { - INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */ - INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP_E */ - INTEL_GPP(GPP_C0, GPIO_RSVD_53, GPIO_RSVD_61), /* JTAG */ - INTEL_GPP(GPP_C0, GPIO_RSVD_62, GPIO_RSVD_67), /* HVMOS */ + INTEL_GPP(GPP_I0, GPP_I0, GPP_I14), /* GPP_I */ + INTEL_GPP(GPP_I0, GPP_J0, GPP_J11), /* GPP_J */ }; static const struct pad_community cfl_communities[] = { - { /* GPP A, B, G, SPI */ + { /* GPP A, B */ .port = PID_GPIOCOM0, .first_pad = GPP_A0, - .last_pad = GPIO_RSVD_11, + .last_pad = GPP_B23, .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_ABG", + .name = "GPP_AB", .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map_com0, .num_reset_vals = ARRAY_SIZE(rst_map_com0), .groups = cfl_community0_groups, .num_groups = ARRAY_SIZE(cfl_community0_groups), - }, { /* GPP D, F, H, VGPIO */ + }, { /* GPP C, D, G */ .port = PID_GPIOCOM1, - .first_pad = GPP_D0, - .last_pad = GPIO_RSVD_52, + .first_pad = GPP_C0, + .last_pad = GPP_G7, .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_DFH", + .name = "GPP_CDG", .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), @@ -110,33 +106,33 @@ .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cfl_community2_groups, .num_groups = ARRAY_SIZE(cfl_community2_groups), - }, { /* AZA, CPU */ + }, { /* GPP K, H, E, F */ .port = PID_GPIOCOM3, - .first_pad = HDA_BCLK, - .last_pad = GPIO_RSVD_78, + .first_pad = GPP_K0, + .last_pad = GPP_F23, .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GP_AC", + .name = "GPP_KHEF", .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cfl_community3_groups, .num_groups = ARRAY_SIZE(cfl_community3_groups), - }, { /* GPP C, E, JTAG, HVMOS */ + }, { /* GPP I, J */ .port = PID_GPIOCOM4, - .first_pad = GPP_C0, - .last_pad = GPIO_RSVD_67, + .first_pad = GPP_I0, + .last_pad = GPP_J11, .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_CEJ", + .name = "GPP_IJ", .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), @@ -154,15 +150,18 @@ const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) { static const struct pmc_to_gpio_route routes[] = { - { PMC_GPP_A, GPP_A }, - { PMC_GPP_B, GPP_B }, - { PMC_GPP_C, GPP_C }, - { PMC_GPP_D, GPP_D }, - { PMC_GPP_E, GPP_E }, - { PMC_GPP_F, GPP_F }, - { PMC_GPP_G, GPP_G }, - { PMC_GPP_H, GPP_H }, - { PMC_GPD, GPD }, + { GPP_A, GPP_A }, + { GPP_B, GPP_B }, + { GPP_C, GPP_C }, + { GPP_D, GPP_D }, + { GPP_E, GPP_E }, + { GPP_F, GPP_F }, + { GPP_G, GPP_G }, + { GPP_H, GPP_H }, + { GPP_I, GPP_I }, + { GPP_J, GPP_J }, + { GPP_K, GPP_K }, + { GPD, GPD }, }; *num = ARRAY_SIZE(routes); return routes; diff --git a/src/soc/intel/coffeelake/include/soc/gpio.h b/src/soc/intel/coffeelake/include/soc/gpio.h old mode 100644 new mode 100755 index 3c10d08..c56b1d3 --- a/src/soc/intel/coffeelake/include/soc/gpio.h +++ b/src/soc/intel/coffeelake/include/soc/gpio.h @@ -19,6 +19,6 @@ #include <soc/gpio_defs.h> #include <intelblocks/gpio.h> -#define CROS_GPIO_DEVICE_NAME "INT34BB:00" +#define CROS_GPIO_DEVICE_NAME "INT3450:00" #endif diff --git a/src/soc/intel/coffeelake/include/soc/gpio_defs.h b/src/soc/intel/coffeelake/include/soc/gpio_defs.h old mode 100644 new mode 100755 index d5731e5..ab35f8e --- a/src/soc/intel/coffeelake/include/soc/gpio_defs.h +++ b/src/soc/intel/coffeelake/include/soc/gpio_defs.h @@ -240,12 +240,86 @@ #define GPP_H21_IRQ 0x5d #define GPP_H22_IRQ 0x5e #define GPP_H23_IRQ 0x5f - +/* Group I */ +#define GPP_I0_IRQ 0x18 +#define GPP_I1_IRQ 0x19 +#define GPP_I2_IRQ 0x1a +#define GPP_I3_IRQ 0x1b +#define GPP_I4_IRQ 0x1c +#define GPP_I5_IRQ 0x1d +#define GPP_I6_IRQ 0x1e +#define GPP_I7_IRQ 0x1f +#define GPP_I8_IRQ 0x20 +#define GPP_I9_IRQ 0x21 +#define GPP_I10_IRQ 0x22 +#define GPP_I11_IRQ 0x23 +#define GPP_I12_IRQ 0x24 +#define GPP_I13_IRQ 0x25 +#define GPP_I14_IRQ 0x26 +#define GPP_I15_IRQ 0x27 +#define GPP_I16_IRQ 0x28 +#define GPP_I17_IRQ 0x29 +#define GPP_I18_IRQ 0x2a +#define GPP_I19_IRQ 0x2b +#define GPP_I20_IRQ 0x2c +#define GPP_I21_IRQ 0x2d +#define GPP_I22_IRQ 0x2e +#define GPP_I23_IRQ 0x2f +/* Group J */ +#define GPP_J0_IRQ 0x30 +#define GPP_J1_IRQ 0x31 +#define GPP_J2_IRQ 0x32 +#define GPP_J3_IRQ 0x33 +#define GPP_J4_IRQ 0x34 +#define GPP_J5_IRQ 0x35 +#define GPP_J6_IRQ 0x36 +#define GPP_J7_IRQ 0x37 +#define GPP_J8_IRQ 0x38 +#define GPP_J9_IRQ 0x39 +#define GPP_J10_IRQ 0x3a +#define GPP_J11_IRQ 0x3b +#define GPP_J12_IRQ 0x3c +#define GPP_J13_IRQ 0x3d +#define GPP_J14_IRQ 0x3e +#define GPP_J15_IRQ 0x3f +#define GPP_J16_IRQ 0x40 +#define GPP_J17_IRQ 0x41 +#define GPP_J18_IRQ 0x42 +#define GPP_J19_IRQ 0x43 +#define GPP_J20_IRQ 0x44 +#define GPP_J21_IRQ 0x45 +#define GPP_J22_IRQ 0x46 +#define GPP_J23_IRQ 0x47 +/* Group K */ +#define GPP_K0_IRQ 0x48 +#define GPP_K1_IRQ 0x49 +#define GPP_K2_IRQ 0x4a +#define GPP_K3_IRQ 0x4b +#define GPP_K4_IRQ 0x4c +#define GPP_K5_IRQ 0x4d +#define GPP_K6_IRQ 0x4e +#define GPP_K7_IRQ 0x4f +#define GPP_K8_IRQ 0x50 +#define GPP_K9_IRQ 0x51 +#define GPP_K10_IRQ 0x52 +#define GPP_K11_IRQ 0x53 +#define GPP_K12_IRQ 0x54 +#define GPP_K13_IRQ 0x55 +#define GPP_K14_IRQ 0x56 +#define GPP_K15_IRQ 0x57 +#define GPP_K16_IRQ 0x58 +#define GPP_K17_IRQ 0x59 +#define GPP_K18_IRQ 0x5a +#define GPP_K19_IRQ 0x5b +#define GPP_K20_IRQ 0x5c +#define GPP_K21_IRQ 0x5d +#define GPP_K22_IRQ 0x5e +#define GPP_K23_IRQ 0x5f /* Register defines. */ #define GPIO_MISCCFG 0x10 -#define GPE_DW_SHIFT 8 -#define GPE_DW_MASK 0xfff00 -#define HOSTSW_OWN_REG_0 0xb0 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define HOSTSW_OWN_REG_0 0xc0 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 #define PAD_CFG_BASE 0x600 diff --git a/src/soc/intel/coffeelake/include/soc/gpio_soc_defs.h b/src/soc/intel/coffeelake/include/soc/gpio_soc_defs.h old mode 100644 new mode 100755 index 67b34dc..37db625 --- a/src/soc/intel/coffeelake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/coffeelake/include/soc/gpio_soc_defs.h @@ -24,21 +24,17 @@ */ #define GPP_A 0 #define GPP_B 1 -#define GPP_G 2 -#define GROUP_SPI 3 -#define GPP_D 4 -#define GPP_F 5 +#define GPP_C 2 +#define GPP_D 3 +#define GPP_G 4 +#define GPP_K 5 #define GPP_H 6 -#define GROUP_VGPIO 7 -#define GPD 9 -#define GROUP_AZA 0xA -#define GROUP_CPU 0xB -#define GPP_C 0xC -#define GPP_E 0xD -#define GROUP_JTAG 0xE -#define GROUP_HVMOS 0xF - -#define GPIO_NUM_GROUPS 15 +#define GPP_E 7 +#define GPP_F 8 +#define GPP_I 9 +#define GPP_J 10 +#define GPD 12 +#define GPIO_NUM_GROUPS 11 #define GPIO_MAX_NUM_PER_GROUP 24 /* @@ -70,286 +66,242 @@ #define GPP_A21 21 #define GPP_A22 22 #define GPP_A23 23 -#define GPIO_RSVD_0 24 + /* Group B */ -#define GPP_B0 25 -#define GPP_B1 26 -#define GPP_B2 27 -#define GPP_B3 28 -#define GPP_B4 29 -#define GPP_B5 30 -#define GPP_B6 31 -#define GPP_B7 32 -#define GPP_B8 33 -#define GPP_B9 34 -#define GPP_B10 35 -#define GPP_B11 36 -#define GPP_B12 37 -#define GPP_B13 38 -#define GPP_B14 39 -#define GPP_B15 40 -#define GPP_B16 41 -#define GPP_B17 42 -#define GPP_B18 43 -#define GPP_B19 44 -#define GPP_B20 45 -#define GPP_B21 46 -#define GPP_B22 47 -#define GPP_B23 48 -#define GPIO_RSVD_1 49 -#define GPIO_RSVD_2 50 -/* Group G */ -#define GPP_G0 51 -#define GPP_G1 52 -#define GPP_G2 53 -#define GPP_G3 54 -#define GPP_G4 55 -#define GPP_G5 56 -#define GPP_G6 57 -#define GPP_G7 58 -/* Group SPI */ -#define GPIO_RSVD_3 59 -#define GPIO_RSVD_4 60 -#define GPIO_RSVD_5 61 -#define GPIO_RSVD_6 62 -#define GPIO_RSVD_7 63 -#define GPIO_RSVD_8 64 -#define GPIO_RSVD_9 65 -#define GPIO_RSVD_10 66 -#define GPIO_RSVD_11 67 +#define GPP_B0 24 +#define GPP_B1 25 +#define GPP_B2 26 +#define GPP_B3 27 +#define GPP_B4 28 +#define GPP_B5 29 +#define GPP_B6 30 +#define GPP_B7 31 +#define GPP_B8 32 +#define GPP_B9 33 +#define GPP_B10 34 +#define GPP_B11 35 +#define GPP_B12 36 +#define GPP_B13 37 +#define GPP_B14 38 +#define GPP_B15 39 +#define GPP_B16 40 +#define GPP_B17 41 +#define GPP_B18 42 +#define GPP_B19 43 +#define GPP_B20 44 +#define GPP_B21 45 +#define GPP_B22 46 +#define GPP_B23 47 -#define NUM_GPIO_COM0_PADS (GPIO_RSVD_11 - GPP_A0 + 1) - -/* Group D */ -#define GPP_D0 68 -#define GPP_D1 69 -#define GPP_D2 70 -#define GPP_D3 71 -#define GPP_D4 72 -#define GPP_D5 73 -#define GPP_D6 74 -#define GPP_D7 75 -#define GPP_D8 76 -#define GPP_D9 77 -#define GPP_D10 78 -#define GPP_D11 79 -#define GPP_D12 80 -#define GPP_D13 81 -#define GPP_D14 82 -#define GPP_D15 83 -#define GPP_D16 84 -#define GPP_D17 85 -#define GPP_D18 86 -#define GPP_D19 87 -#define GPP_D20 88 -#define GPP_D21 89 -#define GPP_D22 90 -#define GPP_D23 91 -#define GPIO_RSVD_12 92 -/* Group F */ -#define GPP_F0 93 -#define GPP_F1 94 -#define GPP_F2 95 -#define GPP_F3 96 -#define GPP_F4 97 -#define GPP_F5 98 -#define GPP_F6 99 -#define GPP_F7 100 -#define GPP_F8 101 -#define GPP_F9 102 -#define GPP_F10 103 -#define GPP_F11 104 -#define GPP_F12 105 -#define GPP_F13 106 -#define GPP_F14 107 -#define GPP_F15 108 -#define GPP_F16 109 -#define GPP_F17 110 -#define GPP_F18 111 -#define GPP_F19 112 -#define GPP_F20 113 -#define GPP_F21 114 -#define GPP_F22 115 -#define GPP_F23 116 -/* Group H */ -#define GPP_H0 117 -#define GPP_H1 118 -#define GPP_H2 119 -#define GPP_H3 120 -#define GPP_H4 121 -#define GPP_H5 122 -#define GPP_H6 123 -#define GPP_H7 124 -#define GPP_H8 125 -#define GPP_H9 126 -#define GPP_H10 127 -#define GPP_H11 128 -#define GPP_H12 129 -#define GPP_H13 130 -#define GPP_H14 131 -#define GPP_H15 132 -#define GPP_H16 133 -#define GPP_H17 134 -#define GPP_H18 135 -#define GPP_H19 136 -#define GPP_H20 137 -#define GPP_H21 138 -#define GPP_H22 139 -#define GPP_H23 140 -/* Group VGOIO */ -#define GPIO_RSVD_13 141 -#define GPIO_RSVD_14 142 -#define GPIO_RSVD_15 143 -#define GPIO_RSVD_16 144 -#define GPIO_RSVD_17 145 -#define GPIO_RSVD_18 146 -#define GPIO_RSVD_19 147 -#define GPIO_RSVD_20 148 -#define GPIO_RSVD_21 149 -#define GPIO_RSVD_22 150 -#define GPIO_RSVD_23 151 -#define GPIO_RSVD_24 152 -#define GPIO_RSVD_25 153 -#define GPIO_RSVD_26 154 -#define GPIO_RSVD_27 155 -#define GPIO_RSVD_28 156 -#define GPIO_RSVD_29 157 -#define GPIO_RSVD_30 158 -#define GPIO_RSVD_31 159 -#define GPIO_RSVD_32 160 -#define GPIO_RSVD_33 161 -#define GPIO_RSVD_34 162 -#define GPIO_RSVD_35 163 -#define GPIO_RSVD_36 164 -#define GPIO_RSVD_37 165 -#define GPIO_RSVD_38 166 -#define GPIO_RSVD_39 167 -#define GPIO_RSVD_40 168 -#define GPIO_RSVD_41 169 -#define GPIO_RSVD_42 170 -#define GPIO_RSVD_43 171 -#define GPIO_RSVD_44 172 -#define GPIO_RSVD_45 173 -#define GPIO_RSVD_46 174 -#define GPIO_RSVD_47 175 -#define GPIO_RSVD_48 176 -#define GPIO_RSVD_49 177 -#define GPIO_RSVD_50 178 -#define GPIO_RSVD_51 179 -#define GPIO_RSVD_52 180 - -#define NUM_GPIO_COM1_PADS (GPIO_RSVD_52 - GPP_D0 + 1) +#define NUM_GPIO_COM0_PADS (GPP_B23 - GPP_A0 + 1) /* Group C */ -#define GPP_C0 181 -#define GPP_C1 182 -#define GPP_C2 183 -#define GPP_C3 184 -#define GPP_C4 185 -#define GPP_C5 186 -#define GPP_C6 187 -#define GPP_C7 188 -#define GPP_C8 189 -#define GPP_C9 190 -#define GPP_C10 191 -#define GPP_C11 192 -#define GPP_C12 193 -#define GPP_C13 194 -#define GPP_C14 195 -#define GPP_C15 196 -#define GPP_C16 197 -#define GPP_C17 198 -#define GPP_C18 199 -#define GPP_C19 200 -#define GPP_C20 201 -#define GPP_C21 202 -#define GPP_C22 203 -#define GPP_C23 204 -/* Group E */ -#define GPP_E0 205 -#define GPP_E1 206 -#define GPP_E2 207 -#define GPP_E3 208 -#define GPP_E4 209 -#define GPP_E5 210 -#define GPP_E6 211 -#define GPP_E7 212 -#define GPP_E8 213 -#define GPP_E9 214 -#define GPP_E10 215 -#define GPP_E11 216 -#define GPP_E12 217 -#define GPP_E13 218 -#define GPP_E14 219 -#define GPP_E15 220 -#define GPP_E16 221 -#define GPP_E17 222 -#define GPP_E18 223 -#define GPP_E19 224 -#define GPP_E20 225 -#define GPP_E21 226 -#define GPP_E22 227 -#define GPP_E23 228 -/* Group Jtag */ -#define GPIO_RSVD_53 229 -#define GPIO_RSVD_54 230 -#define GPIO_RSVD_55 231 -#define GPIO_RSVD_56 232 -#define GPIO_RSVD_57 233 -#define GPIO_RSVD_58 234 -#define GPIO_RSVD_59 235 -#define GPIO_RSVD_60 236 -#define GPIO_RSVD_61 237 -/* Group HVMOS */ -#define GPIO_RSVD_62 238 -#define GPIO_RSVD_63 239 -#define GPIO_RSVD_64 240 -#define GPIO_RSVD_65 241 -#define GPIO_RSVD_66 242 -#define GPIO_RSVD_67 243 +#define GPP_C0 48 +#define GPP_C1 49 +#define GPP_C2 50 +#define GPP_C3 51 +#define GPP_C4 52 +#define GPP_C5 53 +#define GPP_C6 54 +#define GPP_C7 55 +#define GPP_C8 56 +#define GPP_C9 57 +#define GPP_C10 58 +#define GPP_C11 59 +#define GPP_C12 60 +#define GPP_C13 61 +#define GPP_C14 62 +#define GPP_C15 63 +#define GPP_C16 64 +#define GPP_C17 65 +#define GPP_C18 66 +#define GPP_C19 67 +#define GPP_C20 68 +#define GPP_C21 69 +#define GPP_C22 70 +#define GPP_C23 71 -#define NUM_GPIO_COM4_PADS (GPIO_RSVD_67 - GPP_C0 + 1) +/* Group D */ +#define GPP_D0 72 +#define GPP_D1 73 +#define GPP_D2 74 +#define GPP_D3 75 +#define GPP_D4 76 +#define GPP_D5 77 +#define GPP_D6 78 +#define GPP_D7 79 +#define GPP_D8 80 +#define GPP_D9 81 +#define GPP_D10 82 +#define GPP_D11 83 +#define GPP_D12 84 +#define GPP_D13 85 +#define GPP_D14 86 +#define GPP_D15 87 +#define GPP_D16 88 +#define GPP_D17 89 +#define GPP_D18 90 +#define GPP_D19 91 +#define GPP_D20 92 +#define GPP_D21 93 +#define GPP_D22 94 +#define GPP_D23 95 + +/* Group G */ +#define GPP_G0 96 +#define GPP_G1 97 +#define GPP_G2 98 +#define GPP_G3 99 +#define GPP_G4 100 +#define GPP_G5 101 +#define GPP_G6 102 +#define GPP_G7 103 + +#define NUM_GPIO_COM1_PADS (GPP_G7 - GPP_C0 + 1) + +/* Group K */ +#define GPP_K0 104 +#define GPP_K1 105 +#define GPP_K2 106 +#define GPP_K3 107 +#define GPP_K4 108 +#define GPP_K5 109 +#define GPP_K6 110 +#define GPP_K7 111 +#define GPP_K8 112 +#define GPP_K9 113 +#define GPP_K10 114 +#define GPP_K11 115 +#define GPP_K12 116 +#define GPP_K13 117 +#define GPP_K14 118 +#define GPP_K15 119 +#define GPP_K16 120 +#define GPP_K17 121 +#define GPP_K18 122 +#define GPP_K19 123 +#define GPP_K20 124 +#define GPP_K21 125 +#define GPP_K22 126 +#define GPP_K23 127 + +/* Group H */ +#define GPP_H0 128 +#define GPP_H1 129 +#define GPP_H2 130 +#define GPP_H3 131 +#define GPP_H4 132 +#define GPP_H5 133 +#define GPP_H6 134 +#define GPP_H7 135 +#define GPP_H8 136 +#define GPP_H9 137 +#define GPP_H10 138 +#define GPP_H11 139 +#define GPP_H12 140 +#define GPP_H13 141 +#define GPP_H14 142 +#define GPP_H15 143 +#define GPP_H16 144 +#define GPP_H17 145 +#define GPP_H18 146 +#define GPP_H19 147 +#define GPP_H20 148 +#define GPP_H21 149 +#define GPP_H22 150 +#define GPP_H23 151 + +/* Group E */ +#define GPP_E0 152 +#define GPP_E1 153 +#define GPP_E2 154 +#define GPP_E3 155 +#define GPP_E4 156 +#define GPP_E5 157 +#define GPP_E6 158 +#define GPP_E7 159 +#define GPP_E8 160 +#define GPP_E9 161 +#define GPP_E10 162 +#define GPP_E11 163 +#define GPP_E12 164 + +/* Group F */ +#define GPP_F0 165 +#define GPP_F1 166 +#define GPP_F2 167 +#define GPP_F3 168 +#define GPP_F4 169 +#define GPP_F5 170 +#define GPP_F6 171 +#define GPP_F7 172 +#define GPP_F8 173 +#define GPP_F9 174 +#define GPP_F10 175 +#define GPP_F11 176 +#define GPP_F12 177 +#define GPP_F13 178 +#define GPP_F14 179 +#define GPP_F15 180 +#define GPP_F16 181 +#define GPP_F17 182 +#define GPP_F18 183 +#define GPP_F19 184 +#define GPP_F20 185 +#define GPP_F21 186 +#define GPP_F22 187 +#define GPP_F23 188 + +#define NUM_GPIO_COM3_PADS (GPP_F23 - GPP_K0 + 1) + +/* Group I */ +#define GPP_I0 189 +#define GPP_I1 190 +#define GPP_I2 191 +#define GPP_I3 192 +#define GPP_I4 193 +#define GPP_I5 194 +#define GPP_I6 195 +#define GPP_I7 196 +#define GPP_I8 197 +#define GPP_I9 198 +#define GPP_I10 199 +#define GPP_I11 200 +#define GPP_I12 201 +#define GPP_I13 202 +#define GPP_I14 203 + +/* Group J */ +#define GPP_J0 204 +#define GPP_J1 205 +#define GPP_J2 206 +#define GPP_J3 207 +#define GPP_J4 208 +#define GPP_J5 209 +#define GPP_J6 210 +#define GPP_J7 211 +#define GPP_J8 212 +#define GPP_J9 213 +#define GPP_J10 214 +#define GPP_J11 215 + +#define NUM_GPIO_COM4_PADS (GPP_J11 - GPP_I0 + 1) /* Group GPD */ -#define GPD0 244 -#define GPD1 245 -#define GPD2 246 -#define GPD3 247 -#define GPD4 248 -#define GPD5 249 -#define GPD6 250 -#define GPD7 251 -#define GPD8 252 -#define GPD9 253 -#define GPD10 254 -#define GPD11 255 +#define GPD0 216 +#define GPD1 217 +#define GPD2 218 +#define GPD3 219 +#define GPD4 220 +#define GPD5 221 +#define GPD6 222 +#define GPD7 223 +#define GPD8 224 +#define GPD9 225 +#define GPD10 226 +#define GPD11 227 #define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1) - -/* Group AZA */ -#define HDA_BCLK 256 -#define HDA_RSTB 257 -#define HDA_SYNC 258 -#define HDA_SDO 259 -#define HDA_SDI_0 260 -#define HDA_SDI_1 261 -#define SSP1_SFRM 262 -#define SSP1_TXD 263 -/* Group CPU */ -#define GPIO_RSVD_68 264 -#define GPIO_RSVD_69 265 -#define GPIO_RSVD_70 266 -#define GPIO_RSVD_71 267 -#define GPIO_RSVD_72 268 -#define GPIO_RSVD_73 269 -#define GPIO_RSVD_74 270 -#define GPIO_RSVD_75 271 -#define GPIO_RSVD_76 272 -#define GPIO_RSVD_77 273 -#define GPIO_RSVD_78 274 - -#define NUM_GPIO_COM3_PADS (GPIO_RSVD_78 - HDA_BCLK + 1) - -#define TOTAL_PADS 275 +#define TOTAL_PADS (GPD11 + 1) #endif -- To view, visit https://review.coreboot.org/25241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3acf0a0e3101eadb3464baf8e1a7ba5b32804777 Gerrit-Change-Number: 25241 Gerrit-PatchSet: 1 Gerrit-Owner: Kin Wai Ng <kin.wai.ng(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Enable USB2_P12 and USB2_P13
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

1 0

Change in coreboot[master]: soc/intel/coffeelake: Enable support up to 24 PCIE Root Ports
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

1 0

Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Enable PCIE X1, X4 and X16 slot
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

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coreboot-gerrit March 2018