coreboot-gerrit March 2018

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Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Enable SATA in device tree
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

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Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Enable LAN CLK REQ and CLK USAGE
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

1 0

Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Enable LAN feature
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

1 0

Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Fix I2C4, I2C5 and UART2 CFL-H specif...
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

Hello Naresh Solanki, Subrata Banik, Balaji Manigandan, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, I'd like you to do a code review. Please visit https://review.coreboot.org/25234 to review the following change. Change subject: mainboard/intel/coffeelake_rvp: Fix I2C4, I2C5 and UART2 CFL-H specific device ...................................................................... mainboard/intel/coffeelake_rvp: Fix I2C4, I2C5 and UART2 CFL-H specific device 1. I2C4, I2C5 not found in CFL-H. 2. Add UART2 device Change-Id: Ic00782f2a186b4f1fff169044e25246e1e13248b Signed-off-by: Ng Kin Wai <kin.wai.ng(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb M src/soc/intel/coffeelake/chip.c M src/soc/intel/coffeelake/i2c.c M src/soc/intel/coffeelake/include/soc/pci_devs.h 4 files changed, 3 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/25234/1 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb index 0a18432..fe6736e 100755 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb @@ -117,9 +117,7 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 off end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 + device pci 19.0 on end # UART #2 device pci 1a.0 on end # eMMC device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN diff --git a/src/soc/intel/coffeelake/chip.c b/src/soc/intel/coffeelake/chip.c old mode 100644 new mode 100755 index cf6a334..9819ee1 --- a/src/soc/intel/coffeelake/chip.c +++ b/src/soc/intel/coffeelake/chip.c @@ -51,8 +51,6 @@ case PCH_DEVFN_CSE_3: return "CSE3"; case PCH_DEVFN_SATA: return "SATA"; case PCH_DEVFN_UART2: return "UAR2"; - case PCH_DEVFN_I2C4: return "I2C4"; - case PCH_DEVFN_I2C5: return "I2C5"; case PCH_DEVFN_PCIE1: return "RP01"; case PCH_DEVFN_PCIE2: return "RP02"; case PCH_DEVFN_PCIE3: return "RP03"; @@ -104,8 +102,6 @@ PCH_DEVFN_I2C1, PCH_DEVFN_I2C2, PCH_DEVFN_I2C3, - PCH_DEVFN_I2C4, - PCH_DEVFN_I2C5, PCH_DEVFN_GSPI0, PCH_DEVFN_GSPI1, PCH_DEVFN_GSPI2, diff --git a/src/soc/intel/coffeelake/i2c.c b/src/soc/intel/coffeelake/i2c.c old mode 100644 new mode 100755 index df46ef3..8536fc0 --- a/src/soc/intel/coffeelake/i2c.c +++ b/src/soc/intel/coffeelake/i2c.c @@ -53,10 +53,6 @@ return 2; case PCH_DEVFN_I2C3: return 3; - case PCH_DEVFN_I2C4: - return 4; - case PCH_DEVFN_I2C5: - return 5; } return -1; } @@ -72,10 +68,6 @@ return PCH_DEVFN_I2C2; case 3: return PCH_DEVFN_I2C3; - case 4: - return PCH_DEVFN_I2C4; - case 5: - return PCH_DEVFN_I2C5; } return -1; } diff --git a/src/soc/intel/coffeelake/include/soc/pci_devs.h b/src/soc/intel/coffeelake/include/soc/pci_devs.h old mode 100644 new mode 100755 index d98f81f..6b66cbc --- a/src/soc/intel/coffeelake/include/soc/pci_devs.h +++ b/src/soc/intel/coffeelake/include/soc/pci_devs.h @@ -100,12 +100,8 @@ #define PCH_DEV_SATA _PCH_DEV(SATA, 0) #define PCH_DEV_SLOT_SIO2 0x19 -#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO2, 0) -#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO2, 1) -#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO2, 2) -#define PCH_DEV_I2C4 _PCH_DEV(SIO2, 0) -#define PCH_DEV_I2C5 _PCH_DEV(SIO2, 1) -#define PCH_DEV_UART2 _PCH_DEV(SIO2, 2) +#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO2, 0) +#define PCH_DEV_UART2 _PCH_DEV(SIO2, 0) #define PCH_DEV_SLOT_STORAGE 0x1A #define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0) -- To view, visit https://review.coreboot.org/25234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic00782f2a186b4f1fff169044e25246e1e13248b Gerrit-Change-Number: 25234 Gerrit-PatchSet: 1 Gerrit-Owner: Kin Wai Ng <kin.wai.ng(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Fix PID_ITSS value
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

1 0

Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Increase MAX_CPUS to 12 for CFL
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

1 0

Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Modified memory dimm settings
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

1 0

Change in coreboot[master]: soc/intel/coffeelake/romstage: Updated BoardType for RVP11
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

1 0

Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Modified memory dimm settings
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

Hello Naresh Solanki, Subrata Banik, Balaji Manigandan, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, I'd like you to do a code review. Please visit https://review.coreboot.org/25229 to review the following change. Change subject: mainboard/intel/coffeelake_rvp: Modified memory dimm settings ...................................................................... mainboard/intel/coffeelake_rvp: Modified memory dimm settings 1. Hardcoded SPD Addresses 2. Modified memory dimm values to suit CFL-H RVP11 Change-Id: I4011de101d9a35e4735fc8491015aa56ebe80e7e Signed-off-by: Ng Kin Wai <kin.wai.ng(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/romstage.c M src/mainboard/intel/coffeelake_rvp/spd/spd_util.c 2 files changed, 16 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/25229/1 diff --git a/src/mainboard/intel/coffeelake_rvp/romstage.c b/src/mainboard/intel/coffeelake_rvp/romstage.c old mode 100644 new mode 100755 index e0699da..a2c719b --- a/src/mainboard/intel/coffeelake_rvp/romstage.c +++ b/src/mainboard/intel/coffeelake_rvp/romstage.c @@ -36,8 +36,8 @@ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); - mem_cfg->DqPinsInterleaved = 0; - mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */ + mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; /* VREF_CA->CHA/CHB */ mem_cfg->ECT = 1; /* Early Command Training Enabled */ spd_index = 2; @@ -51,4 +51,9 @@ mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); mem_cfg->RefClk = 0; /* Auto Select CLK freq */ mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + + mem_cfg->SpdAddressTable[0] = 0xA0; + mem_cfg->SpdAddressTable[1] = 0xA2; + mem_cfg->SpdAddressTable[2] = 0xA4; + mem_cfg->SpdAddressTable[3] = 0xA6; } diff --git a/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c b/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c old mode 100644 new mode 100755 index 4e2f31f..ece6b6c --- a/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c @@ -23,8 +23,8 @@ { /* DQ byte map Ch0 */ const u8 dq_map[12] = { - 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00 , - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); } @@ -32,8 +32,8 @@ void mainboard_fill_dq_map_ch1(void *dq_map_ptr) { const u8 dq_map[12] = { - 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); } @@ -41,27 +41,17 @@ void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr) { /* DQS CPU<>DRAM map Ch0 */ - const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 }; + const u8 dqs_map_h[8] = { 0, 1, 3, 2, 4, 5, 6, 7 }; - const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 }; - - if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) - memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); - else - memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); + memcpy(dqs_map_ptr, dqs_map_h, sizeof(dqs_map_h)); } void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr) { /* DQS CPU<>DRAM map Ch1 */ - const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 }; + const u8 dqs_map_h[8] = { 1, 0, 4, 5, 2, 3, 6, 7 }; - const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 }; - - if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) - memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); - else - memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); + memcpy(dqs_map_ptr, dqs_map_h, sizeof(dqs_map_h)); } void mainboard_fill_rcomp_res_data(void *rcomp_ptr) @@ -75,7 +65,7 @@ { /* Rcomp target */ static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { - 80, 40, 40, 40, 30 }; + 100, 33, 32, 33, 28 }; memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); } -- To view, visit https://review.coreboot.org/25229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4011de101d9a35e4735fc8491015aa56ebe80e7e Gerrit-Change-Number: 25229 Gerrit-PatchSet: 1 Gerrit-Owner: Kin Wai Ng <kin.wai.ng(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>

1 0

Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Ensure MP Initialization
by Kin Wai Ng (Code Review) 16 Mar '18

16 Mar '18

1 0

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coreboot-gerrit March 2018