coreboot-gerrit March 2018

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Change in coreboot[master]: mb/google/kahlee: Adds register address mapping for FCH MISC
by build bot (Jenkins) (Code Review) 19 Mar '18

19 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25263 ) Change subject: mb/google/kahlee: Adds register address mapping for FCH MISC ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23121/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68730/ : SUCCESS -- To view, visit https://review.coreboot.org/25263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia553e55ffb358415067000d2d2d2744322d1c4db Gerrit-Change-Number: 25263 Gerrit-PatchSet: 1 Gerrit-Owner: Akshu Agrawal <akshu.agrawal(a)amd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Mar 2018 05:31:27 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee: Adds register address mapping for FCH MISC
by Akshu Agrawal (Code Review) 19 Mar '18

19 Mar '18

Akshu Agrawal has uploaded this change for review. ( https://review.coreboot.org/25263 Change subject: mb/google/kahlee: Adds register address mapping for FCH MISC ...................................................................... mb/google/kahlee: Adds register address mapping for FCH MISC Audio machine driver will enable/disable clock by making it as a CCF clock in kernel. BUG=b:74570989 TEST=aplay -vv <file> check register to see clock enabled kill aplay check register to see clock disabled Change-Id: Ia553e55ffb358415067000d2d2d2744322d1c4db Signed-off-by: Akshu Agrawal <akshu.agrawal(a)amd.com> --- M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/25263/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl index ea58f89..2cd58e9 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl @@ -20,4 +20,14 @@ Name (_ADR, 1) Name (_HID, "AMD7219") Name (_CID, "AMD7219") + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () { + // Memory resource is for MISC FCH register set. + // It is needed for enabling of clock. + Memory32Fixed(ReadWrite, 0xFED80E00, 0xFF) + }) + + Return (RBUF) + } } -- To view, visit https://review.coreboot.org/25263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia553e55ffb358415067000d2d2d2744322d1c4db Gerrit-Change-Number: 25263 Gerrit-PatchSet: 1 Gerrit-Owner: Akshu Agrawal <akshu.agrawal(a)amd.com>

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Change in coreboot[master]: security/flash: Add hook for get write protect state
by build bot (Jenkins) (Code Review) 18 Mar '18

18 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25262 ) Change subject: security/flash: Add hook for get write protect state ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23120/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68729/ : SUCCESS -- To view, visit https://review.coreboot.org/25262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icda8ac0b60d84fb5f020e790ccda093d477c738c Gerrit-Change-Number: 25262 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 18 Mar 2018 23:30:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/flash: Add hook for get write protect state
by Philipp Deppenwiese (Code Review) 18 Mar '18

18 Mar '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/25262 Change subject: security/flash: Add hook for get write protect state ...................................................................... security/flash: Add hook for get write protect state Change-Id: Icda8ac0b60d84fb5f020e790ccda093d477c738c Signed-off-by: zaolin <zaolin(a)das-labor.org> --- M src/drivers/mrc_cache/mrc_cache.c M src/include/bootmode.h M src/mainboard/google/auron/chromeos.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/chell/chromeos.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/gale/chromeos.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/gru/chromeos.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/kahlee/chromeos.c M src/mainboard/google/lars/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/nyan/chromeos.c M src/mainboard/google/nyan_big/chromeos.c M src/mainboard/google/nyan_blaze/chromeos.c M src/mainboard/google/oak/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/purin/chromeos.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/reef/chromeos.c M src/mainboard/google/rotor/chromeos.c M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/smaug/chromeos.c M src/mainboard/google/storm/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/google/urara/chromeos.c M src/mainboard/google/veyron/chromeos.c M src/mainboard/google/veyron_mickey/chromeos.c M src/mainboard/google/veyron_rialto/chromeos.c M src/mainboard/google/zoombini/chromeos.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/cannonlake_rvp/chromeos.c M src/mainboard/intel/galileo/vboot.c M src/mainboard/intel/glkrvp/chromeos.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c M src/security/flash/flash.c M src/security/flash/flash.h M src/security/vboot/Kconfig M src/security/vboot/bootmode.c M src/security/vboot/vboot_handoff.c 53 files changed, 106 insertions(+), 145 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/25262/1 diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index eec1591..ade62d8 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -26,6 +26,7 @@ #include <region_file.h> #include <security/vboot/vboot_common.h> #include <spi_flash.h> +#include <security/flash/flash.h> #include "mrc_cache.h" @@ -428,30 +429,13 @@ /* Read flash status register to determine if write protect is active */ static int nvm_is_write_protected(void) { - u8 sr1; - u8 wp_gpio; - u8 wp_spi; - if (!IS_ENABLED(CONFIG_CHROMEOS)) return 0; if (!IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) return 0; - /* Read Write Protect GPIO if available */ - wp_gpio = get_write_protect_state(); - - /* Read Status Register 1 */ - if (spi_flash_status(boot_device_spi_flash(), &sr1) < 0) { - printk(BIOS_ERR, "Failed to read SPI status register 1\n"); - return -1; - } - wp_spi = !!(sr1 & 0x80); - - printk(BIOS_DEBUG, "SPI flash protection: WPSW=%d SRP0=%d\n", - wp_gpio, wp_spi); - - return wp_gpio && wp_spi; + return get_write_protect_state(); } /* Apply protection to a range of flash */ diff --git a/src/include/bootmode.h b/src/include/bootmode.h index 5650b3d..a8dad13 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -18,7 +18,6 @@ /* functions implemented per mainboard: */ void init_bootmode_straps(void); -int get_write_protect_state(void); int get_developer_mode_switch(void); int get_recovery_mode_switch(void); int get_recovery_mode_retrain_switch(void); diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 3355136..4727068 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -16,6 +16,7 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> +#include <security/flash/flash.h> /* SPI Write protect is GPIO 16 */ #define CROS_WP_GPIO 58 @@ -36,7 +37,7 @@ } #endif -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return get_gpio(CROS_WP_GPIO); } diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index 7412c62..91d3ae2 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -21,6 +21,7 @@ #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #define GPIO_SPI_WP 58 #define GPIO_REC_MODE 12 @@ -46,7 +47,7 @@ } #endif -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { device_t dev; #ifdef __PRE_RAM__ diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 42f6189..5fbd7097 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -19,6 +19,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pci.h> +#include <security/flash/flash.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> @@ -50,7 +51,7 @@ /* Write Protect: GPIO active Low */ gpios->gpios[0].port = WP_GPIO; gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = !get_write_protect_state(); + gpios->gpios[0].value = !get_spi_wp_pin_state(); strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); @@ -83,7 +84,7 @@ } #endif -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return !get_gpio(WP_GPIO); } diff --git a/src/mainboard/google/chell/chromeos.c b/src/mainboard/google/chell/chromeos.c index 3ff52d9..7e7225b 100644 --- a/src/mainboard/google/chell/chromeos.c +++ b/src/mainboard/google/chell/chromeos.c @@ -19,6 +19,7 @@ #include <soc/gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #include "gpio.h" @@ -28,7 +29,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_spi_wp_pin_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, @@ -40,7 +41,7 @@ } #endif /* ENV_RAMSTAGE */ -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { /* Read PCH_WP GPIO. */ return gpio_get(GPIO_PCH_WP); diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 7885642..25992f5 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -20,6 +20,7 @@ #include <soc/gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> /* The WP status pin lives on MF_ISH_GPIO_4 */ #define WP_STATUS_PAD_CFG0 0x4838 @@ -36,7 +37,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_spi_wp_pin_state(), "write protect"}, {-1, ACTIVE_HIGH, vboot_recovery_mode_enabled(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, @@ -46,7 +47,7 @@ } #endif /* ENV_RAMSTAGE */ -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { /* * The vboot loader queries this function in romstage. The GPIOs have diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index ae456b4..588e2d9 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -22,6 +22,7 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <bootmode.h> +#include <security/flash/flash.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -78,7 +79,7 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return !gpio_get_value(GPIO_D16); } diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index a77a23e..faf480b 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -18,6 +18,7 @@ #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #include "gpio.h" @@ -27,7 +28,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_spi_wp_pin_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, @@ -39,7 +40,7 @@ } #endif /* ENV_RAMSTAGE */ -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { /* Read PCH_WP GPIO. */ return gpio_get(GPIO_PCH_WP); diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index e52ac72..5660f66 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -17,6 +17,7 @@ #include <rules.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #include "gpio.h" @@ -26,7 +27,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_spi_wp_pin_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, 1, "lid"}, /* Lid switch always open */ {-1, ACTIVE_HIGH, 0, "power"}, @@ -38,7 +39,7 @@ } #endif /* ENV_RAMSTAGE */ -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { /* Read PCH_WP GPIO. */ return gpio_get(GPIO_PCH_WP); diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index b4cb332..0a323d8 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -21,6 +21,7 @@ #include <gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -31,7 +32,7 @@ /* Write Protect: active low */ gpios->gpios[count].port = -1; gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = get_write_protect_state(); + gpios->gpios[count].value = get_spi_wp_pin_state(); strncpy((char *)gpios->gpios[count].name, "write protect", GPIO_MAX_NAME_LENGTH); count++; @@ -78,8 +79,3 @@ return 0; #endif } - -int get_write_protect_state(void) -{ - return 0; -} diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index 939b061..eb43f74 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -24,6 +24,7 @@ #include <string.h> #include <timer.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #define REC_POL ACTIVE_LOW #define WP_POL ACTIVE_LOW @@ -171,7 +172,7 @@ return get_switch_state() == wipeout_req; } -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return read_gpio(get_wp_status_gpio_pin()) ^ !WP_POL; } diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 3cb3d89..2c77c51 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -20,6 +20,7 @@ #include <soc/gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #include "gpio.h" @@ -29,7 +30,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_spi_wp_pin_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, @@ -41,7 +42,7 @@ } #endif /* ENV_RAMSTAGE */ -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { /* Read PCH_WP GPIO. */ return gpio_get(GPIO_PCH_WP); diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index ff5368a..7664df7 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -18,10 +18,11 @@ #include <boot/coreboot_tables.h> #include <gpio.h> #include <security/tpm/tis.h> +#include <security/flash/flash.h> #include "board.h" -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return gpio_get(GPIO_WP); } @@ -29,7 +30,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO_WP.raw, ACTIVE_HIGH, get_write_protect_state(), + {GPIO_WP.raw, ACTIVE_HIGH, get_spi_wp_pin_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, #if IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET) diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index f99fd6d..4aa121d 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -22,6 +22,7 @@ #include <ec/google/chromeec/ec.h> #include <soc/gpio.h> #include <soc/sata.h> +#include <security/flash/flash.h> #include "onboard.h" #define GPIO_SPI_WP 58 @@ -49,7 +50,7 @@ } #endif -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { device_t dev; #ifdef __PRE_RAM__ diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index e74e3b9..6d2c800 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -20,11 +20,12 @@ #include <console/console.h> #include <gpio.h> #include <variant/gpio.h> +#include <security/flash/flash.h> void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_spi_wp_pin_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, @@ -35,7 +36,7 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return gpio_get(CROS_WP_GPIO); } diff --git a/src/mainboard/google/lars/chromeos.c b/src/mainboard/google/lars/chromeos.c index 54f9bbe..ed55b3a 100644 --- a/src/mainboard/google/lars/chromeos.c +++ b/src/mainboard/google/lars/chromeos.c @@ -19,6 +19,7 @@ #include <soc/gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #include "gpio.h" @@ -28,7 +29,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_spi_wp_pin_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, @@ -40,7 +41,7 @@ } #endif /* ENV_RAMSTAGE */ -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { /* Read PCH_WP GPIO. */ return gpio_get(GPIO_PCH_WP); diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index 335f1f7..c9bcdef 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -18,6 +18,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> @@ -32,7 +33,7 @@ /* Write Protect: GPIO57 = PCH_SPI_WP_D */ gpios->gpios[0].port = 57; gpios->gpios[0].polarity = ACTIVE_HIGH; - gpios->gpios[0].value = get_write_protect_state(); + gpios->gpios[0].value = get_spi_wp_pin_state(); strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); /* Recovery: the "switch" comes from the EC */ @@ -62,7 +63,7 @@ } #endif -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return get_gpio(57); } diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index 4fb8e78..7d76fbf 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -17,6 +17,7 @@ #include <bootmode.h> #include <gpio.h> #include <string.h> +#include <security/flash/flash.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -31,7 +32,7 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return !gpio_get(GPIO(R1)); } diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index f466d91..752e763 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -17,6 +17,7 @@ #include <bootmode.h> #include <gpio.h> #include <string.h> +#include <security/flash/flash.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -31,7 +32,7 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return !gpio_get(GPIO(R1)); } diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index f466d91..752e763 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -17,6 +17,7 @@ #include <bootmode.h> #include <gpio.h> #include <string.h> +#include <security/flash/flash.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -31,7 +32,7 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return !gpio_get(GPIO(R1)); } diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index 42145f7..fcf0107 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -18,6 +18,7 @@ #include <boot/coreboot_tables.h> #include <gpio.h> #include <string.h> +#include <security/flash/flash.h> #include "gpio.h" @@ -47,7 +48,7 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return !gpio_get(WRITE_PROTECT); } diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index d2448eb..c34c9ab 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -24,6 +24,7 @@ #include <southbridge/intel/common/gpio.h> #include <ec/compal/ene932/ec.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #include "ec.h" @@ -47,7 +48,7 @@ /* Write Protect: GPIO70 active high */ gpios->gpios[0].port = 70; gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = !get_write_protect_state(); + gpios->gpios[0].value = !get_spi_wp_pin_state(); strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); /* Recovery: Virtual GPIO in the EC (Servo GPIO68 active low) */ @@ -82,7 +83,7 @@ return get_gpio(15); } -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return !get_gpio(70); } diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index e782986..7287040 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -22,6 +22,7 @@ #include <soc/gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -78,7 +79,7 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return !gpio_get_value(GPIO_X30); } diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index cf9579e..811607a 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -19,6 +19,7 @@ #include <rules.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #include <variant/gpio.h> @@ -28,7 +29,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_spi_wp_pin_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, @@ -40,7 +41,7 @@ } #endif /* ENV_RAMSTAGE */ -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { /* Read PCH_WP GPIO. */ return gpio_get(GPIO_PCH_WP); diff --git a/src/mainboard/google/purin/chromeos.c b/src/mainboard/google/purin/chromeos.c index 5e7cdfe..f3031fe 100644 --- a/src/mainboard/google/purin/chromeos.c +++ b/src/mainboard/google/purin/chromeos.c @@ -24,8 +24,3 @@ { return 0; } - -int get_write_protect_state(void) -{ - return 0; -} diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index 99a97d8..e2edf5d 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -17,6 +17,7 @@ #include <bootmode.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> /* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ #define WP_STATUS_PAD 36 @@ -27,7 +28,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_spi_wp_pin_state(), "write protect"}, {-1, ACTIVE_HIGH, vboot_recovery_mode_enabled(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, @@ -37,7 +38,7 @@ } #endif -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { /* * The vboot loader queries this function in romstage. The GPIOs have diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index 7b7f2b8..e843f9c 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -19,11 +19,12 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include <variant/gpio.h> +#include <security/flash/flash.h> void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_spi_wp_pin_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, @@ -34,7 +35,7 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { /* Read PCH_WP GPIO. */ return gpio_get(GPIO_PCH_WP); diff --git a/src/mainboard/google/rotor/chromeos.c b/src/mainboard/google/rotor/chromeos.c index c73fe47..37f376f 100644 --- a/src/mainboard/google/rotor/chromeos.c +++ b/src/mainboard/google/rotor/chromeos.c @@ -27,8 +27,3 @@ { return 0; } - -int get_write_protect_state(void) -{ - return 0; -} diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index e26c3fb..8c53837 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -18,6 +18,7 @@ #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> @@ -35,7 +36,7 @@ } #endif -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return get_gpio(58); } diff --git a/src/mainboard/google/smaug/chromeos.c b/src/mainboard/google/smaug/chromeos.c index fe8e5aa..a558302 100644 --- a/src/mainboard/google/smaug/chromeos.c +++ b/src/mainboard/google/smaug/chromeos.c @@ -16,6 +16,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <string.h> +#include <security/flash/flash.h> #include "gpio.h" @@ -32,7 +33,7 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return !gpio_get(WRITE_PROTECT_L); } diff --git a/src/mainboard/google/storm/chromeos.c b/src/mainboard/google/storm/chromeos.c index 3110228..e24c56b 100644 --- a/src/mainboard/google/storm/chromeos.c +++ b/src/mainboard/google/storm/chromeos.c @@ -24,6 +24,7 @@ #include <string.h> #include <timer.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #define DEV_SW 15 #define DEV_POL ACTIVE_LOW @@ -142,7 +143,7 @@ return get_switch_state() == wipeout_req; } -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return read_gpio(WP_SW) ^ !WP_POL; } diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 047e6a1..c49494f 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -25,6 +25,7 @@ #include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include <ec/quanta/it8518/ec.h> +#include <security/flash/flash.h> #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> @@ -39,7 +40,7 @@ /* Write Protect: GPIO7 */ gpios->gpios[0].port = 7; gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = !get_write_protect_state(); + gpios->gpios[0].value = !get_spi_wp_pin_state(); strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); @@ -75,7 +76,7 @@ } #endif -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return !get_gpio(7); } diff --git a/src/mainboard/google/urara/chromeos.c b/src/mainboard/google/urara/chromeos.c index 3f7ec32..6ee3f25 100644 --- a/src/mainboard/google/urara/chromeos.c +++ b/src/mainboard/google/urara/chromeos.c @@ -18,12 +18,6 @@ #include <console/console.h> #include <gpio.h> -int get_write_protect_state(void) -{ - printk(BIOS_ERR, "%s unsupported, but called\n", __func__); - return 0; -} - void fill_lb_gpios(struct lb_gpios *gpios) { printk(BIOS_ERR, "%s unsupported, but called\n", __func__); diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index f99cd81..4902494 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -20,6 +20,7 @@ #include <gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #include "board.h" @@ -68,7 +69,7 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return !gpio_get(GPIO_WP); } diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index 2988ea7..12c2dfb 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -18,6 +18,7 @@ #include <gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #include "board.h" @@ -46,7 +47,7 @@ return !gpio_get(GPIO_RECOVERY); } -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return !gpio_get(GPIO_WP); } diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index c68cd7a..5b35529 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -18,6 +18,7 @@ #include <gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #include "board.h" @@ -56,7 +57,7 @@ gpio_get(GPIO_RECOVERY_PUSHKEY)); } -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { return !gpio_get(GPIO_WP); } diff --git a/src/mainboard/google/zoombini/chromeos.c b/src/mainboard/google/zoombini/chromeos.c index 8ca643e..63a7e51 100644 --- a/src/mainboard/google/zoombini/chromeos.c +++ b/src/mainboard/google/zoombini/chromeos.c @@ -20,11 +20,12 @@ #include <rules.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_spi_wp_pin_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, @@ -35,7 +36,7 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { /* Read PCH_WP GPIO. */ return gpio_get(GPIO_PCH_WP); diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 5ed9e36..4daf2df 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -83,11 +83,6 @@ return get_gpio(69); } -int get_write_protect_state(void) -{ - return 0; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(69, CROS_GPIO_DEVICE_NAME), CROS_GPIO_DEV_AL(48, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c index b7dd91d..5863a05 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.c +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c @@ -20,6 +20,7 @@ #include <soc/gpio.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #if ENV_RAMSTAGE #include <boot/coreboot_tables.h> @@ -27,7 +28,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_spi_wp_pin_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, @@ -48,12 +49,6 @@ return 0; } -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c index 469ec4e..113483c 100644 --- a/src/mainboard/intel/galileo/vboot.c +++ b/src/mainboard/intel/galileo/vboot.c @@ -38,12 +38,6 @@ return 0; } -int get_write_protect_state(void) -{ - /* Not write protected */ - return 0; -} - void log_recovery_mode_switch(void) { } diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index a87ce4a..c7e1bdb 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -20,11 +20,12 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include <variant/gpio.h> +#include <security/flash/flash.h> void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_spi_wp_pin_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, @@ -41,11 +42,6 @@ return 0; } -int get_write_protect_state(void) -{ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index 4bd802a..8164be5 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -24,6 +24,7 @@ #include <string.h> #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #include "gpio.h" #include "ec.h" @@ -34,7 +35,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_spi_wp_pin_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, @@ -81,12 +82,6 @@ return 0; } -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 54f9bbe..ed55b3a 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -19,6 +19,7 @@ #include <soc/gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #include "gpio.h" @@ -28,7 +29,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_spi_wp_pin_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, @@ -40,7 +41,7 @@ } #endif /* ENV_RAMSTAGE */ -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { /* Read PCH_WP GPIO. */ return gpio_get(GPIO_PCH_WP); diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index fbcbcf7..f993347 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -18,6 +18,7 @@ #include <gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #define WP_GPIO GP_E_22 @@ -30,7 +31,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_spi_wp_pin_state(), "write protect"}, {-1, ACTIVE_HIGH, vboot_recovery_mode_enabled(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, @@ -40,7 +41,7 @@ } #endif /* ENV_RAMSTAGE */ -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { /* * The vboot loader queries this function in romstage. The GPIOs have diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index fe98fd8..2de89aa 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -45,11 +45,6 @@ return REC_MODE_SETTING; } -int get_write_protect_state(void) -{ - return 0; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_DEV_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index a287c74..f445fb3 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -22,6 +22,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #define GPIO_SPI_WP 24 #define GPIO_REC_MODE 42 @@ -50,7 +51,7 @@ /* Write Protect: GPIO24 = KBC3_SPI_WP# */ gpios->gpios[0].port = GPIO_SPI_WP; gpios->gpios[0].polarity = ACTIVE_HIGH; - gpios->gpios[0].value = get_write_protect_state(); + gpios->gpios[0].value = get_spi_wp_pin_state(); strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); @@ -85,7 +86,7 @@ } #endif -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev; diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 01d81d7..6fdc144 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -21,6 +21,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/flash/flash.h> #define GPIO_SPI_WP 68 #define GPIO_REC_MODE 42 @@ -46,7 +47,7 @@ /* Write Protect: GPIO68 = CHP3_SPI_WP */ gpios->gpios[0].port = GPIO_SPI_WP; gpios->gpios[0].polarity = ACTIVE_HIGH; - gpios->gpios[0].value = get_write_protect_state(); + gpios->gpios[0].value = get_spi_wp_pin_state(); strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); @@ -82,7 +83,7 @@ } #endif -int get_write_protect_state(void) +int get_spi_wp_pin_state(void) { #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev; diff --git a/src/security/flash/flash.c b/src/security/flash/flash.c index 5f07850..49a2980 100644 --- a/src/security/flash/flash.c +++ b/src/security/flash/flash.c @@ -60,7 +60,7 @@ return result; } -int get_write_protect_state1(void) +int get_write_protect_state(void) { int result = -1; struct region region; diff --git a/src/security/flash/flash.h b/src/security/flash/flash.h index 8c22e94..0d113c8 100644 --- a/src/security/flash/flash.h +++ b/src/security/flash/flash.h @@ -19,6 +19,6 @@ int get_spi_wp_pin_state(void); int set_write_protect_enabled(void); -int get_write_protect_state1(void); +int get_write_protect_state(void); #endif /* FLASH_H_ */ diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index e2a3f20..9e936e7 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -225,8 +225,7 @@ bool "Allow the use of vboot without board support" default n help - Enable weak functions for get_write_protect_state and - get_recovery_mode_switch in order to proceed with refactoring + Enable weak functions for get_recovery_mode_switch in order to proceed with refactoring of the vboot2 code base. Later on this code is removed and replaced by interfaces. diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 05098b4..1601b16 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -171,14 +171,6 @@ } #if IS_ENABLED(CONFIG_VBOOT_NO_BOARD_SUPPORT) -/** - * TODO: Create flash protection interface which implements get_write_protect_state. - * get_recovery_mode_switch should be implemented as default function. - */ -int __attribute__((weak)) get_write_protect_state(void) -{ - return 0; -} int __attribute__((weak)) get_recovery_mode_switch(void) { diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c index 9fecc1a..3190b7d 100644 --- a/src/security/vboot/vboot_handoff.c +++ b/src/security/vboot/vboot_handoff.c @@ -36,6 +36,7 @@ #include <vboot_struct.h> #include <security/vboot/vbnv.h> #include <security/vboot/misc.h> +#include <security/flash/flash.h> /** * Sets vboot_handoff based on the information in vb2_shared_data -- To view, visit https://review.coreboot.org/25262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icda8ac0b60d84fb5f020e790ccda093d477c738c Gerrit-Change-Number: 25262 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: soc/intel/common/opregion: Get rid of opregion.c
by build bot (Jenkins) (Code Review) 18 Mar '18

18 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21703 ) Change subject: soc/intel/common/opregion: Get rid of opregion.c ...................................................................... Patch Set 11: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68728/ : SUCCESS -- To view, visit https://review.coreboot.org/21703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5f78e9030df12da5369d142dda5c59e576ebcef7 Gerrit-Change-Number: 21703 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Abhay Kumar <abhay.kumar(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 18 Mar 2018 19:18:07 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: security/vboot: Extend measurements for all execution flows
by Philipp Deppenwiese (Code Review) 18 Mar '18

18 Mar '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/24993 ) Change subject: security/vboot: Extend measurements for all execution flows ...................................................................... Patch Set 3: Add depends on !ON_DEVICE_ROM_LOAD -- To view, visit https://review.coreboot.org/24993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3ddfeabd63aefec152a9bc439a415c37b814f94f Gerrit-Change-Number: 24993 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 18 Mar 2018 13:20:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: [WIP]nb/intel/sandybridge/raminit: Add ECC support
by build bot (Jenkins) (Code Review) 18 Mar '18

18 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22215 ) Change subject: [WIP]nb/intel/sandybridge/raminit: Add ECC support ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23119/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68727/ : SUCCESS -- To view, visit https://review.coreboot.org/22215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1206746332c9939a78b67e7b48d3098bdef8a2ed Gerrit-Change-Number: 22215 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 18 Mar 2018 13:07:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Add ECC detection support
by build bot (Jenkins) (Code Review) 18 Mar '18

18 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22214 ) Change subject: nb/intel/sandybridge/raminit: Add ECC detection support ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23118/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68726/ : SUCCESS -- To view, visit https://review.coreboot.org/22214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5b7599746195cfa996a48320404a8dbe6820483a Gerrit-Change-Number: 22214 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 18 Mar 2018 12:57:51 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Do not configure GPIO_149 as GPO
by build bot (Jenkins) (Code Review) 17 Mar '18

17 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25259 ) Change subject: mb/google/octopus: Do not configure GPIO_149 as GPO ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23117/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68725/ : SUCCESS -- To view, visit https://review.coreboot.org/25259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie4f21b12fae027cdba54ce147e6d1a88ee854792 Gerrit-Change-Number: 25259 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Mar 2018 07:41:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Do not configure GPIO_149 as GPO
by Furquan Shaikh (Code Review) 17 Mar '18

17 Mar '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/25259 Change subject: mb/google/octopus: Do not configure GPIO_149 as GPO ...................................................................... mb/google/octopus: Do not configure GPIO_149 as GPO GPIO_149 is used as ESPI clock feedback and configuring it as a GPO results in EC communication failure. This change removes the configuration of GPIO_149 as GPO in ramstage so that it remains configured for ESPI (as it was when AP came out of reset). BUG=b:75348718 Change-Id: Ie4f21b12fae027cdba54ce147e6d1a88ee854792 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/baseboard/gpio.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/25259/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index d06de1a..135fab9 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -207,7 +207,6 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_144, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* PANEL1_VDDN */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_145, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* PANEL1_BKLTEN */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_146, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* PANEL1_BKLTCTL */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_149, 1, DEEP, NONE, HIZCRx1, DISPUPD),/* LPC_CLKOUT1 -- EN_PP3300_WLAN */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_154, 1, DEEP, UP_20K, HIZCRx1, DISPUPD),/* LPC_CLKRUNB -- LTE_OFF_ODL */ /* AUDIO COMMUNITY GPIOS*/ -- To view, visit https://review.coreboot.org/25259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie4f21b12fae027cdba54ce147e6d1a88ee854792 Gerrit-Change-Number: 25259 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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coreboot-gerrit March 2018