coreboot-gerrit March 2018

coreboot-gerrit@coreboot.org

1 participants
1399 discussions

Change in coreboot[master]: mainboard/google/zoombini: Enable HAVE_ACPI_RESUME
by Vaibhav Shankar (Code Review) 28 Mar '18

28 Mar '18

Vaibhav Shankar has uploaded this change for review. ( https://review.coreboot.org/25390 Change subject: mainboard/google/zoombini: Enable HAVE_ACPI_RESUME ...................................................................... mainboard/google/zoombini: Enable HAVE_ACPI_RESUME Currently there is a problem with the S3 resume path on Meowth. This patch adds a config parameter which fixes S3 resume. This should be included along with the EC patch where VSTORE is enabled. BUG=b:72472969 TEST=suspend and resume from S3 should work. Change-Id: I9de84dfd450936b3bc08e016bec6cf5ae88eab3d Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> --- M src/mainboard/google/zoombini/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/25390/1 diff --git a/src/mainboard/google/zoombini/Kconfig b/src/mainboard/google/zoombini/Kconfig index 4b523c3..78ef386 100644 --- a/src/mainboard/google/zoombini/Kconfig +++ b/src/mainboard/google/zoombini/Kconfig @@ -8,6 +8,7 @@ select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_CANNONLAKE -- To view, visit https://review.coreboot.org/25390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9de84dfd450936b3bc08e016bec6cf5ae88eab3d Gerrit-Change-Number: 25390 Gerrit-PatchSet: 1 Gerrit-Owner: Vaibhav Shankar <vaibhav.shankar(a)intel.com>

1 0

Change in coreboot[master]: mb/google/poppy: Add variant for Atlas
by Furquan Shaikh (Code Review) 28 Mar '18

28 Mar '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/25389 ) Change subject: mb/google/poppy: Add variant for Atlas ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/25389/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/atlas/devicetree.cb: https://review.coreboot.org/#/c/25389/1/src/mainboard/google/poppy/variants… PS1, Line 8: DSX_EN_WAKE_PIN > It looks like WAKE# is still used but the PE_RST was moved to GPP_B8? The bug does suggest we need […] Ohh okay sounds good. -- To view, visit https://review.coreboot.org/25389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5a0bccd1bda0134aa51885ac2c6e7bb5b45de924 Gerrit-Change-Number: 25389 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 22:45:02 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/google/poppy: Add variant for Atlas
by Duncan Laurie (Code Review) 28 Mar '18

28 Mar '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/25389 ) Change subject: mb/google/poppy: Add variant for Atlas ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/25389/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/atlas/devicetree.cb: https://review.coreboot.org/#/c/25389/1/src/mainboard/google/poppy/variants… PS1, Line 8: DSX_EN_WAKE_PIN > Right. We would need to route to a different pin for S0ix. It looks like WAKE# is still used but the PE_RST was moved to GPP_B8? The bug does suggest we need to move wake as well. (don't want to link to an internal bug here) -- To view, visit https://review.coreboot.org/25389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5a0bccd1bda0134aa51885ac2c6e7bb5b45de924 Gerrit-Change-Number: 25389 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 22:44:02 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/google/poppy: Add variant for Atlas
by Furquan Shaikh (Code Review) 27 Mar '18

27 Mar '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/25389 ) Change subject: mb/google/poppy: Add variant for Atlas ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/25389/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/atlas/devicetree.cb: https://review.coreboot.org/#/c/25389/1/src/mainboard/google/poppy/variants… PS1, Line 8: DSX_EN_WAKE_PIN > it is still connected on atlas, though maybe it should be using a different pin for s0ix to work pro […] Right. We would need to route to a different pin for S0ix. -- To view, visit https://review.coreboot.org/25389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5a0bccd1bda0134aa51885ac2c6e7bb5b45de924 Gerrit-Change-Number: 25389 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 21:14:45 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/google/poppy: Add variant for Atlas
by Duncan Laurie (Code Review) 27 Mar '18

27 Mar '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/25389 ) Change subject: mb/google/poppy: Add variant for Atlas ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/25389/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/atlas/devicetree.cb: https://review.coreboot.org/#/c/25389/1/src/mainboard/google/poppy/variants… PS1, Line 8: DSX_EN_WAKE_PIN > Do we still need this? I thought we removed the wake line going to WAKE# pin. it is still connected on atlas, though maybe it should be using a different pin for s0ix to work properly? I will check. Since we aren't using DS3 these probably don't need to be enabled as wake pins anyway.. -- To view, visit https://review.coreboot.org/25389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5a0bccd1bda0134aa51885ac2c6e7bb5b45de924 Gerrit-Change-Number: 25389 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 21:10:17 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/google/poppy: Add variant for Atlas
by Furquan Shaikh (Code Review) 27 Mar '18

27 Mar '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/25389 ) Change subject: mb/google/poppy: Add variant for Atlas ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/25389/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/atlas/devicetree.cb: https://review.coreboot.org/#/c/25389/1/src/mainboard/google/poppy/variants… PS1, Line 8: DSX_EN_WAKE_PIN Do we still need this? I thought we removed the wake line going to WAKE# pin. -- To view, visit https://review.coreboot.org/25389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5a0bccd1bda0134aa51885ac2c6e7bb5b45de924 Gerrit-Change-Number: 25389 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 20:56:34 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/google/poppy: Add variant for Atlas
by build bot (Jenkins) (Code Review) 27 Mar '18

27 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25389 ) Change subject: mb/google/poppy: Add variant for Atlas ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69126/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23479/ : SUCCESS -- To view, visit https://review.coreboot.org/25389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5a0bccd1bda0134aa51885ac2c6e7bb5b45de924 Gerrit-Change-Number: 25389 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 20:48:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/google/poppy: Add variant for Atlas
by Duncan Laurie (Code Review) 27 Mar '18

27 Mar '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/25389 Change subject: mb/google/poppy: Add variant for Atlas ...................................................................... mb/google/poppy: Add variant for Atlas Add a new variant of Poppy for the Atlas board. BUG=b:75454415 TEST=tested on a P0 board. System boots and is mostly functional, though some peripherals are not ready so there are no touchpad/touchscreen devices configured yet. Change-Id: I5a0bccd1bda0134aa51885ac2c6e7bb5b45de924 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/Kconfig.name A src/mainboard/google/poppy/variants/atlas/Makefile.inc A src/mainboard/google/poppy/variants/atlas/devicetree.cb A src/mainboard/google/poppy/variants/atlas/gpio.c A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl A src/mainboard/google/poppy/variants/atlas/include/variant/ec.h A src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h A src/mainboard/google/poppy/variants/atlas/memory.c A src/mainboard/google/poppy/variants/atlas/nhlt.c 10 files changed, 1,064 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/25389/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 7d98d0e..64230d6 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -25,6 +25,7 @@ config DEVICETREE string + default "variants/atlas/devicetree.cb" if BOARD_GOOGLE_ATLAS default "variants/nami/devicetree.cb" if BOARD_GOOGLE_NAMI default "variants/nautilus/devicetree.cb" if BOARD_GOOGLE_NAUTILUS default "variants/soraka/devicetree.cb" if BOARD_GOOGLE_SORAKA @@ -45,6 +46,7 @@ config GBB_HWID string depends on CHROMEOS + default "ATLAS TEST 1412" if BOARD_GOOGLE_ATLAS default "POPPY TEST 8294" if BOARD_GOOGLE_POPPY default "NAMI TEST 1669" if BOARD_GOOGLE_NAMI default "NAUTILUS TEST 3013" if BOARD_GOOGLE_NAUTILUS @@ -57,6 +59,12 @@ select NHLT_MAX98927 select NHLT_RT5663 +config INCLUDE_NHLT_BLOBS_ATLAS + bool "Include blobs for atlas audio." + select NHLT_DA7219 + select NHLT_DMIC_2CH + select NHLT_MAX98373 + config INCLUDE_NHLT_BLOBS_NAUTILUS bool "Include blobs for nautilus audio." select NHLT_DA7219 @@ -75,6 +83,7 @@ config MAINBOARD_FAMILY string + default "Google_Atlas" if BOARD_GOOGLE_ATLAS default "Google_Poppy" if BOARD_GOOGLE_POPPY default "Google_Nami" if BOARD_GOOGLE_NAMI default "Google_Nautilus" if BOARD_GOOGLE_NAUTILUS @@ -82,6 +91,7 @@ config MAINBOARD_PART_NUMBER string + default "Atlas" if BOARD_GOOGLE_ATLAS default "Poppy" if BOARD_GOOGLE_POPPY default "Nami" if BOARD_GOOGLE_NAMI default "Nautilus" if BOARD_GOOGLE_NAUTILUS @@ -97,6 +107,7 @@ config VARIANT_DIR string + default "atlas" if BOARD_GOOGLE_ATLAS default "poppy" if BOARD_GOOGLE_POPPY default "nami" if BOARD_GOOGLE_NAMI default "nautilus" if BOARD_GOOGLE_NAUTILUS @@ -123,6 +134,16 @@ select SPI_TPM select TPM2 +config VARIANT_SPECIFIC_OPTIONS_ATLAS + def_bool n + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_I2C_MAX98373 + select DRIVERS_I2C_DA7219 + select DRIVERS_PS2_KEYBOARD + select DRIVERS_SPI_ACPI + select EXCLUDE_NATIVE_SD_INTERFACE + select VARIANT_HAS_SPI_TPM if !VBOOT_MOCK_SECDATA + config VARIANT_SPECIFIC_OPTIONS_POPPY def_bool n select DRIVERS_I2C_MAX98927 diff --git a/src/mainboard/google/poppy/Kconfig.name b/src/mainboard/google/poppy/Kconfig.name index d8d685e..686dd1d 100644 --- a/src/mainboard/google/poppy/Kconfig.name +++ b/src/mainboard/google/poppy/Kconfig.name @@ -1,3 +1,8 @@ +config BOARD_GOOGLE_ATLAS + bool "Atlas" + select BOARD_GOOGLE_BASEBOARD_POPPY + select VARIANT_SPECIFIC_OPTIONS_ATLAS + config BOARD_GOOGLE_POPPY bool "Poppy" select BOARD_GOOGLE_BASEBOARD_POPPY diff --git a/src/mainboard/google/poppy/variants/atlas/Makefile.inc b/src/mainboard/google/poppy/variants/atlas/Makefile.inc new file mode 100644 index 0000000..c54d178 --- /dev/null +++ b/src/mainboard/google/poppy/variants/atlas/Makefile.inc @@ -0,0 +1,18 @@ + +SPD_SOURCES = empty # 0b0000 +SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0001 +SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD # 0b0010 +SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0011 +SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR-NUD # 0b0100 +SPD_SOURCES += samsung_dimm_K4EBE304EB-EGCG # 0b0101 +SPD_SOURCES += hynix_dimm_H9CCNNNCLGALAR-NUD # 0b0110 +SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107 # 0b0111 +SPD_SOURCES += micron_dimm_MT52L1G32D4PG-107 # 0b1000 +SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 # 0b1000 + +bootblock-y += gpio.c + +romstage-y += memory.c + +ramstage-y += gpio.c +ramstage-y += nhlt.c diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb new file mode 100644 index 0000000..3d31c40 --- /dev/null +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -0,0 +1,338 @@ +chip soc/intel/skylake + + # Deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # Enable DPTF + register "dptf_enable" = "1" + + # Enable S0ix + register "s0ix_enable" = "1" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "3" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" # FIXME: enable once MIPI is ready + register "SaImguEnable" = "0" # FIXME: enable once MIPI is ready + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "0" + register "IshEnable" = "0" # FIXME: enable once ISH is ready + register "PttSwitch" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "0" + register "FspSkipMpInit" = "1" + register "SaGv" = "3" + register "SerialIrqConfigSirqEnable" = "1" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "1" + register "VmxEnable" = "1" + + register "speed_shift_enable" = "1" + register "dptf_enable" = "1" + register "tdp_pl2_override" = "15" + register "psys_pmax" = "45" + register "tcc_offset" = "10" + register "pch_trip_temp" = "75" + register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 2A | 2A | 2A | 2A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 4A | 24A | 24A | 24A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 14.9 | 5 | 5.7 | 4.57 | + #| DcLoadline | 14.2 | 4.86 | 4.2 | 4.3 | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(2), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(4), + .voltage_limit = 1520, + .ac_loadline = 1490, + .dc_loadline = 1420, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(2), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(24), + .voltage_limit = 1520, + .ac_loadline = 500, + .dc_loadline = 486, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(2), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(24), + .voltage_limit = 1520, + .ac_loadline = 570, + .dc_loadline = 420, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(2), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(24), + .voltage_limit = 1520, + .ac_loadline = 457, + .dc_loadline = 430, + }" + + # PCIe Root port 1 with SRCCLKREQ1# + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpClkSrcNumber[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + + # USB 2.0 + register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Empty + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty + + # USB 3.0 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty + + # Touchscreen + register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 98, + .fall_time_ns = 38, + }" + + # Trackpad + register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 186, + .scl_hcnt = 93, + .sda_hold = 36, + }, + }" + + # Camera + register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 98, + .fall_time_ns = 38, + }" + + # Audio + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" + register "i2c[4]" = "{ + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 176, + .scl_hcnt = 95, + .sda_hold = 36, + } + }" + + # GSPI0 for cr50 TPM + register "gspi[0]" = "{ + .speed_mhz = 1, + .early_init = 1, + }" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSpi0] = PchSerialIoPci, + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, + [PchSerialIoIndexUart0] = PchSerialIoSkipInit, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 on end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C #0 - Touchscreen + device pci 15.1 off end # I2C #1 + device pci 15.2 on end # I2C #2 - Trackpad + device pci 15.3 on end # I2C #3 - Camera + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 off end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 on + chip drivers/i2c/max98373 + register "vmon_slot_no" = "4" + register "imon_slot_no" = "5" + register "uid" = "0" + register "desc" = ""RIGHT SPEAKER AMP"" + register "name" = ""MAXR"" + device i2c 31 on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "6" + register "imon_slot_no" = "7" + register "uid" = "1" + register "desc" = ""LEFT SPEAKER AMP"" + register "name" = ""MAXL"" + device i2c 32 on end + end + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end # I2C #4 - Audio + device pci 1c.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW0_00" + device pci 00.0 on end + end + end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" + device spi 0 on end + end + end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 on end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c new file mode 100644 index 0000000..58b709e --- /dev/null +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -0,0 +1,390 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { + /* A0 : RCIN# ==> NC(TP763) */ + PAD_CFG_NC(GPP_A0), + /* A1 : ESPI_IO0 */ + /* A2 : ESPI_IO1 */ + /* A3 : ESPI_IO2 */ + /* A4 : ESPI_IO3 */ + /* A5 : ESPI_CS# */ + /* A6 : SERIRQ ==> NC(TP764) */ + PAD_CFG_NC(GPP_A6), + /* A7 : PIRQA# ==> NC(TP703) */ + PAD_CFG_NC(GPP_A7), + /* A8 : CLKRUN# ==> NC(TP758)) */ + PAD_CFG_NC(GPP_A8), + /* A9 : ESPI_CLK */ + /* A10 : CLKOUT_LPC1 ==> NC */ + PAD_CFG_NC(GPP_A10), + /* A11 : PME# ==> NC(TP726) */ + PAD_CFG_NC(GPP_A11), + /* A12 : BM_BUSY# ==> NC */ + PAD_CFG_NC(GPP_A12), + /* A13 : SUSWARN# ==> SUSWARN_L */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + /* A14 : ESPI_RESET# */ + /* A15 : SUSACK# ==> SUSACK_L */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : SD_1P8_SEL ==> NC */ + PAD_CFG_NC(GPP_A16), + /* A17 : SD_PWR_EN# ==> NC */ + PAD_CFG_NC(GPP_A17), + /* A18 : ISH_GP0 ==> ISH_GP0 */ + PAD_CFG_NC(GPP_A18), + /* A19 : ISH_GP1 ==> TRACKPAD_INT_L */ + PAD_CFG_GPI_APIC(GPP_A19, NONE, PLTRST), + /* A20 : ISH_GP2 ==> ISH_UART0_RXD */ + PAD_CFG_NC(GPP_A20), + /* A21 : ISH_GP3 */ + PAD_CFG_NC(GPP_A21), + /* A22 : ISH_GP4 */ + PAD_CFG_NC(GPP_A22), + /* A23 : ISH_GP5 */ + PAD_CFG_NC(GPP_A23), + + /* B0 : CORE_VID0 ==> NC(TP42) */ + PAD_CFG_NC(GPP_B0), + /* B1 : CORE_VID1 ==> NC(TP43) */ + PAD_CFG_NC(GPP_B1), + /* B2 : VRALERT# ==> NC */ + PAD_CFG_NC(GPP_B2), + /* B3 : CPU_GP2 ==> NC */ + PAD_CFG_NC(GPP_B3), + /* B4 : CPU_GP3 ==> NC */ + PAD_CFG_NC(GPP_B4), + /* B5 : SRCCLKREQ0# ==> NC */ + PAD_CFG_NC(GPP_B5), + /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : SRCCLKREQ2# ==> NC */ + PAD_CFG_NC(GPP_B7), + /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ + PAD_CFG_GPO(GPP_B8, 0, RSMRST), + /* B9 : SRCCLKREQ4# ==> NC */ + PAD_CFG_NC(GPP_B9), + /* B10 : SRCCLKREQ5# ==> NC */ + PAD_CFG_NC(GPP_B10), + /* B11 : EXT_PWR_GATE# ==> NC */ + PAD_CFG_NC(GPP_B11), + /* B12 : SLP_S0# ==> SLP_S0_L_G */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : SPKR ==> NC */ + PAD_CFG_NC(GPP_B14), + /* B15 : GSPI0_CS# ==> H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> H1_SLAVE_SPI_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* B19 : GSPI1_CS# ==> NC */ + PAD_CFG_NC(GPP_B19), + /* B20 : GSPI1_CLK ==> NC */ + PAD_CFG_NC(GPP_B20), + /* B21 : GSPI1_MISO ==> NC */ + PAD_CFG_NC(GPP_B21), + /* B22 : GSPI1_MOSI ==> NC */ + PAD_CFG_NC(GPP_B22), + /* B23 : SM1ALERT# ==> NC */ + PAD_CFG_NC(GPP_B23), + + /* C0 : SMBCLK ==> NC */ + PAD_CFG_NC(GPP_C0), + /* C1 : SMBDATA ==> NC */ + PAD_CFG_NC(GPP_C1), + /* C2 : SMBALERT# ==> NC */ + PAD_CFG_NC(GPP_C2), + /* C3 : SML0CLK ==> NC */ + PAD_CFG_NC(GPP_C3), + /* C4 : SML0DATA ==> NC */ + PAD_CFG_NC(GPP_C4), + /* C5 : SML0ALERT# ==> NC */ + PAD_CFG_NC(GPP_C5), + /* C6 : SM1CLK ==> EC_IN_RW_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), + /* C7 : SM1DATA ==> NC */ + PAD_CFG_NC(GPP_C7), + /* C8 : UART0_RXD ==> NC */ + PAD_CFG_NC(GPP_C8), + /* C9 : UART0_TXD ==> NC */ + PAD_CFG_NC(GPP_C9), + /* C10 : UART0_RTS# ==> NC */ + PAD_CFG_NC(GPP_C10), + /* C11 : UART0_CTS# ==> NC */ + PAD_CFG_NC(GPP_C11), + /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), + /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), + /* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), + /* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> NC */ + PAD_CFG_NC(GPP_C18), + /* C19 : I2C1_SCL ==> NC */ + PAD_CFG_NC(GPP_C19), + /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> PCH_WP */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + + /* D0 : SPI1_CS# ==> NC */ + PAD_CFG_NC(GPP_D0), + /* D1 : SPI1_CLK ==> TRACKPAD_RESET_1V8_ODL */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : SPI1_MISO ==> NC */ + PAD_CFG_NC(GPP_D2), + /* D3 : SPI1_MOSI ==> NC */ + PAD_CFG_NC(GPP_D3), + /* D4 : FASHTRIG ==> NC */ + PAD_CFG_NC(GPP_D4), + /* D5 : ISH_I2C0_SDA ==> ISH_I2C0_SDA */ + PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1), + /* D6 : ISH_I2C0_SCL ==> ISH_I2C0_SCL */ + PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1), + /* D7 : ISH_I2C1_SDA ==> SPKR_IRQ_L */ + PAD_CFG_GPI_APIC(GPP_D7, NONE, PLTRST), + /* D8 : ISH_I2C1_SCL ==> EN_CAMERA_PWR */ + PAD_CFG_GPO(GPP_D8, 0, DEEP), + /* D9 : ISH_SPI_CS# ==> ISH_SPI_CS_L */ + PAD_CFG_NF_1V8(GPP_D9, NONE, DEEP, NF1), + /* D10 : ISH_SPI_CLK ==> ISH_SPI_CLK */ + PAD_CFG_NF_1V8(GPP_D10, NONE, DEEP, NF1), + /* D11 : ISH_SPI_MISO ==> ISH_SPI_MISO */ + PAD_CFG_NF_1V8(GPP_D11, NONE, DEEP, NF1), + /* D12 : ISH_SPI_MOSI ==> ISH_SPI_MOSI */ + PAD_CFG_NF_1V8(GPP_D12, NONE, DEEP, NF1), + /* D13 : ISH_UART0_RXD ==> ISH_UART0_RXD */ + PAD_CFG_NF_1V8(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> ISH_UART0_TXD */ + PAD_CFG_NF_1V8(GPP_D14, NONE, DEEP, NF1), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_CFG_NC(GPP_D15), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_CFG_NC(GPP_D16), + /* D17 : DMIC_CLK1 ==> PCH_CAMERA_RESET */ + PAD_CFG_GPO(GPP_D17, 0, DEEP), + /* D18 : DMIC_DATA1 ==> PCH_CAMERA_CLOCK_ENABLE */ + PAD_CFG_GPO(GPP_D18, 0, DEEP), + /* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* D20 : DMIC_DATA0 ==> PCH_DMIC_DATA_IN */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* D21 : SPI1_IO2 ==> NC */ + PAD_CFG_NC(GPP_D21), + /* D22 : SPI1_IO3 ==> NC */ + PAD_CFG_NC(GPP_D22), + /* D23 : I2S_MCLK ==> I2S_MCLK_R */ + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + + /* E0 : SATAXPCI0 ==> CHP3_HAVEN_INT_L */ + PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + /* E1 : SATAXPCIE1 ==> NC */ + PAD_CFG_NC(GPP_E1), + /* E2 : SATAXPCIE2 ==> NC */ + PAD_CFG_NC(GPP_E2), + /* E3 : CPU_GP0 ==> NC */ + PAD_CFG_NC(GPP_E3), + /* E4 : SATA_DEVSLP0 ==> NC */ + PAD_CFG_NC(GPP_E4), + /* E5 : SATA_DEVSLP1 ==> NC */ + PAD_CFG_NC(GPP_E5), + /* E6 : SATA_DEVSLP2 ==> NC */ + PAD_CFG_NC(GPP_E6), + /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + /* E8 : SATALED# ==> NC */ + PAD_CFG_NC(GPP_E8), + /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + /* E11 : USB2_OC2# ==> TOUCHSCREEN_RESET_L */ + PAD_CFG_GPO(GPP_E11, 0, DEEP), + /* E12 : USB2_OC3# ==> NC */ + PAD_CFG_NC(GPP_E12), + /* E13 : DDPB_HPD0 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + /* E14 : DDPC_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + /* E15 : DDPD_HPD2 ==> EN_PP3300_DX_WLAN */ + PAD_CFG_GPO(GPP_E15, 1, DEEP), + /* E16 : DDPE_HPD3 ==> NC */ + PAD_CFG_NC(GPP_E16), + /* E17 : EDP_HPD */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + /* E18 : DDPB_CTRLCLK ==> NC */ + PAD_CFG_NC(GPP_E18), + /* E19 : DDPB_CTRLDATA ==> NC */ + PAD_CFG_NC(GPP_E19), + /* E20 : DDPC_CTRLCLK ==> NC */ + PAD_CFG_NC(GPP_E20), + /* E21 : DDPC_CTRLDATA ==> NC */ + PAD_CFG_NC(GPP_E21), + /* E22 : DDPD_CTRLCLK ==> TRACKPAD_SHDN_L */ + PAD_CFG_GPO(GPP_E22, 1, DEEP), + /* E23 : DDPD_CTRLDATA ==> NC */ + PAD_CFG_NC(GPP_E23), + + /* F0 : I2S2_SCLK ==> BOOT_BEEP_BCLK */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), + /* F1 : I2S2_SFRM ==> BOOT_BEEP_BUFFER_OE */ + PAD_CFG_GPO(GPP_F1, 1, DEEP), + /* F2 : I2S2_TXD ==> BOOT_BEEP_LRCLK */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), + /* F3 : I2S2_RXD ==> NC */ + PAD_CFG_NC(GPP_F3), + /* F4 : I2C2_SDA ==> PCH_I2C2_TRACKPAD_1V8_SDA */ + PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), + /* F5 : I2C2_SCL ==> PCH_I2C2_TRACKPAD_1V8_SCL */ + PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), + /* F6 : I2C3_SDA ==> PCH_I2C3_CAMERA_1V8_SDA */ + PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), + /* F7 : I2C3_SCL ==> PCH_I2C3_CAMERA_1V8_SCL */ + PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), + /* F8 : I2C4_SDA ==> PCH_I2C4_AUDIO_1V8_SDA */ + PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), + /* F9 : I2C4_SCL ==> PCH_I2C4_AUDIO_1V8_SCL */ + PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), + /* F10 : I2C5_SDA ==> HP_IRQ_GPIO */ + PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), + /* F11 : I2C5_SCL ==> SPKR_RST_L */ + PAD_CFG_GPO(GPP_F11, 1, RSMRST), + /* F12 : EMMC_CMD */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA0 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA1 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA2 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA3 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA4 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA5 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA6 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_DATA7 */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_RCLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_CLK */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : RSVD ==> NC */ + PAD_CFG_NC(GPP_F23), + + /* G0 : SD_CMD */ + PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), + /* G1 : SD_DATA0 */ + PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), + /* G2 : SD_DATA1 */ + PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), + /* G3 : SD_DATA2 */ + PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), + /* G4 : SD_DATA3 */ + PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), + /* G5 : SD_CD# */ + PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), + /* G6 : SD_CLK */ + PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), + /* G7 : SD_WP */ + PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), + + /* GPD0: BATLOW# ==> PCH_BATLOW_L */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: ACPRESENT ==> EC_PCH_ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */ + PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + /* GPD4: SLP_S3# ==> SLP_S3_L */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: SLP_S4# ==> SLP_S4_L */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: SLP_A# ==> NC */ + PAD_CFG_NC(GPD6), + /* GPD7: RSVD ==> NC */ + PAD_CFG_NC(GPD7), + /* GPD8: SUSCLK ==> PCH_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: SLP_WLAN# ==> NC */ + PAD_CFG_NC(GPD9), + /* GPD10: SLP_S5# ==> NC */ + PAD_CFG_NC(GPD10), + /* GPD11: LANPHYC ==> NC */ + PAD_CFG_NC(GPD11), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ + PAD_CFG_GPO(GPP_B8, 0, RSMRST), + + /* B15 : GSPI0_CS# ==> H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> H1_SLAVE_SPI_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* Ensure UART pins are in native mode for H1. */ + /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + + /* C23 : UART2_CTS# ==> PCH_WP */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + + /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..bb42351 --- /dev/null +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "systherm0" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 90 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "systherm1" +#define DPTF_TSR1_PASSIVE 48 +#define DPTF_TSR1_CRITICAL 90 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "systherm2" +#define DPTF_TSR2_PASSIVE 65 +#define DPTF_TSR2_CRITICAL 75 + +#define DPTF_TSR3_SENSOR_ID 4 +#define DPTF_TSR3_SENSOR_NAME "systherm3" +#define DPTF_TSR3_PASSIVE 65 +#define DPTF_TSR3_CRITICAL 75 + +#undef DPTF_ENABLE_FAN_CONTROL +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0xbb8, "mA", 0 }, /* 3000mA (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x800, "mA", 0 }, /* 2000mA */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1000mA */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 500mA */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR0 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR1 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR2 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR3 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on TSR0 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 7000, /* PowerLimitMaximum */ + 5000, /* TimeWindowMinimum */ + 5000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h b/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h new file mode 100644 index 0000000..22bcef5 --- /dev/null +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> + +#include <variant/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h b/src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h new file mode 100644 index 0000000..f28fb31 --- /dev/null +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <baseboard/gpio.h> + +#undef EN_PP3300_DX_CAM +#define EN_PP3300_DX_CAM GPP_D8 + +#undef EN_CAM_PMIC_RST_L +#define EN_CAM_PMIC_RST_L GPP_D17 + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/poppy/variants/atlas/memory.c b/src/mainboard/google/poppy/variants/atlas/memory.c new file mode 100644 index 0000000..0b34e72 --- /dev/null +++ b/src/mainboard/google/poppy/variants/atlas/memory.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> + +/* DQ byte map */ +static const u8 dq_map[][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } +}; + +/* DQS CPU<>DRAM map */ +static const u8 dqs_map[][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 3, 2, 6, 7, 0, 1, 4, 5 }, +}; + +/* Rcomp resistor */ +static const u16 rcomp_resistor[] = { 200, 81, 162 }; + +/* Rcomp target */ +static const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; + +void variant_memory_params(struct memory_params *p) +{ + p->type = MEMORY_LPDDR3; + p->dq_map = dq_map; + p->dq_map_size = sizeof(dq_map); + p->dqs_map = dqs_map; + p->dqs_map_size = sizeof(dqs_map); + p->rcomp_resistor = rcomp_resistor; + p->rcomp_resistor_size = sizeof(rcomp_resistor); + p->rcomp_target = rcomp_target; + p->rcomp_target_size = sizeof(rcomp_target); +} diff --git a/src/mainboard/google/poppy/variants/atlas/nhlt.c b/src/mainboard/google/poppy/variants/atlas/nhlt.c new file mode 100644 index 0000000..df62112 --- /dev/null +++ b/src/mainboard/google/poppy/variants/atlas/nhlt.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <console/console.h> +#include <nhlt.h> +#include <soc/nhlt.h> + +void variant_nhlt_init(struct nhlt *nhlt) +{ + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + + /* Dialog DA7219 Headset codec. */ + if (nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add Dialog DA7219 codec.\n"); + + /* MAXIM Smart Amps for left and right speakers. */ + if (nhlt_soc_add_max98373(nhlt, AUDIO_LINK_SSP0)) + printk(BIOS_ERR, "Couldn't add Maxim 98373 codec.\n"); +} + +void variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id, + uint32_t *oem_revision) +{ + *oem_id = "GOOGLE"; + *oem_table_id = "ATLASMAX"; + *oem_revision = 0; +} -- To view, visit https://review.coreboot.org/25389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5a0bccd1bda0134aa51885ac2c6e7bb5b45de924 Gerrit-Change-Number: 25389 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

1 0

Change in coreboot[master]: soc/intel/cannonlake: Add VT-d and VMX programming
by build bot (Jenkins) (Code Review) 27 Mar '18

27 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25118 ) Change subject: soc/intel/cannonlake: Add VT-d and VMX programming ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69125/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23478/ : SUCCESS -- To view, visit https://review.coreboot.org/25118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I589590450aa4b9302ee2f9bb7b879a332f50b73e Gerrit-Change-Number: 25118 Gerrit-PatchSet: 10 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 20:01:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: arch/x86/smbios: Consider corner case of Part Number
by build bot (Jenkins) (Code Review) 27 Mar '18

27 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25377 ) Change subject: arch/x86/smbios: Consider corner case of Part Number ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69124/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23477/ : SUCCESS -- To view, visit https://review.coreboot.org/25377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id870c983584771dc1b60b1c99e95bbe7c0d25c4c Gerrit-Change-Number: 25377 Gerrit-PatchSet: 8 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)google.com> Gerrit-Comment-Date: Tue, 27 Mar 2018 18:57:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2018