coreboot-gerrit March 2018

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Change in libgfxinit[master]: Make Raw_Clock a variable
by Arthur Heymans (Code Review) 28 Mar '18

28 Mar '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/25403 Change subject: Make Raw_Clock a variable ...................................................................... Make Raw_Clock a variable On GMCH the Raw_Clock depends on the FSB frequency. Change-Id: I11af9ecb3504983ba1d3136c1b82bd14363afdba Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/broxton/hw-gfx-gma-power_and_clocks.adb M common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.adb M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-dp_aux_request.adb M common/hw-gfx-gma.adb M common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.adb M common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb 7 files changed, 19 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/03/25403/1 diff --git a/common/broxton/hw-gfx-gma-power_and_clocks.adb b/common/broxton/hw-gfx-gma-power_and_clocks.adb index 12ab308..c0f3075 100644 --- a/common/broxton/hw-gfx-gma-power_and_clocks.adb +++ b/common/broxton/hw-gfx-gma-power_and_clocks.adb @@ -316,6 +316,8 @@ Set_Mask (DBUF_CTL, DBUF_CTL_DBUF_POWER_REQUEST); Wait_Set_Mask (DBUF_CTL, DBUF_CTL_DBUF_POWER_STATE); + + Config.Raw_Clock := Config.Default_RawClk_Freq; end Initialize; end HW.GFX.GMA.Power_And_Clocks; diff --git a/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.adb b/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.adb index 41d340a..c0d1e78 100644 --- a/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.adb +++ b/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.adb @@ -207,6 +207,7 @@ begin -- HSW: disable power down well PDW_Off; + Config.Raw_Clock := Config.Default_RawClk_Freq; end Initialize; procedure Power_Set_To (Configs : Pipe_Configs) is diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 5d136b2..aa1c3cd 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -14,7 +14,7 @@ private package HW.GFX.GMA.Config with - Initializes => Valid_Port_GPU + Initializes => (Valid_Port_GPU, Raw_Clock) is CPU : constant CPU_Type := <<CPU>>; @@ -246,6 +246,10 @@ when Broxton => Frequency_Type'First, -- none needed when Skylake => 24_000_000); + Raw_Clock : Frequency_Type := Default_RawClk_Freq + with Part_Of => GMA.Config_State; + + ---------------------------------------------------------------------------- -- Maximum source width with enabled scaler. This only accounts diff --git a/common/hw-gfx-gma-dp_aux_request.adb b/common/hw-gfx-gma-dp_aux_request.adb index 22064ab..f808dc2 100644 --- a/common/hw-gfx-gma-dp_aux_request.adb +++ b/common/hw-gfx-gma-dp_aux_request.adb @@ -19,6 +19,7 @@ with HW.GFX.GMA.Config; with HW.GFX.GMA.Registers; +with HW.GFX.GMA.Power_And_Clocks; use type HW.Word8; use type HW.GFX.GMA.Registers.Registers_Invalid_Index; @@ -162,7 +163,7 @@ Success : out Boolean) with Global => (In_Out => Registers.Register_State, - Input => Time.State), + Input => (Time.State, Config.Raw_Clock)), Depends => ((Registers.Register_State, Response, @@ -170,6 +171,7 @@ Success) => (Registers.Register_State, + Config.Raw_Clock, Time.State, Port, Request, @@ -232,7 +234,7 @@ (if Port = DP_A then Word32 ((Config.Default_CDClk_Freq + 1_000_000) / 2_000_000) else - Word32 ((Config.Default_RawClk_Freq + 1_000_000) / 2_000_000)) + Word32 ((Config.Raw_Clock + 1_000_000) / 2_000_000)) else 0); Busy : Boolean; diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index d8438ab..a4445ba 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -46,7 +46,7 @@ HPD_Delay, Wait_For_HPD, Linear_FB_Base), Init_State => Initialized, - Config_State => Config.Valid_Port_GPU, + Config_State => (Config.Valid_Port_GPU, Config.Raw_Clock), Device_State => (Dev.PCI_State, Registers.Register_State, Registers.GTT_State)) is @@ -307,7 +307,8 @@ Refined_Global => (In_Out => (Config.Valid_Port_GPU, Dev.PCI_State, - Registers.Register_State, Port_IO.State), + Registers.Register_State, Port_IO.State, + Config.Raw_Clock), Input => (Time.State), Output => diff --git a/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.adb b/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.adb index bff4750..a7b1035 100644 --- a/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.adb +++ b/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.adb @@ -50,6 +50,8 @@ Registers.Posting_Read (Registers.PCH_DREF_CONTROL); Time.U_Delay (20); -- DMI latency end if; + + Config.Raw_Clock := Config.Default_RawClk_Freq; end Initialize; end HW.GFX.GMA.Power_And_Clocks_Ironlake; diff --git a/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb b/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb index e79ea87..ea84992 100644 --- a/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb +++ b/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb @@ -315,6 +315,8 @@ (Register => Registers.DBUF_CTL, Mask => DBUF_CTL_DBUF_POWER_STATE); end if; + + Config.Raw_Clock := Config.Default_RawClk_Freq; end Initialize; procedure Power_Set_To (Configs : Pipe_Configs) is -- To view, visit https://review.coreboot.org/25403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I11af9ecb3504983ba1d3136c1b82bd14363afdba Gerrit-Change-Number: 25403 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: util/intelmetool: Add additional helpful error messages
by build bot (Jenkins) (Code Review) 28 Mar '18

28 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25401 ) Change subject: util/intelmetool: Add additional helpful error messages ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69158/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23511/ : SUCCESS -- To view, visit https://review.coreboot.org/25401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie3361910d48271bcc2cd3b4b74937fbc5df0a176 Gerrit-Change-Number: 25401 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 15:03:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/intelmetool: Fix crash on strict devmem kernels
by build bot (Jenkins) (Code Review) 28 Mar '18

28 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25398 ) Change subject: util/intelmetool: Fix crash on strict devmem kernels ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69155/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23508/ : SUCCESS -- To view, visit https://review.coreboot.org/25398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I33c75a7cccb4cefaa26f70aed4bdc4bd620cdad0 Gerrit-Change-Number: 25398 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 14:42:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: arch/x86/smbios: Add support for table 38
by build bot (Jenkins) (Code Review) 28 Mar '18

28 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25386 ) Change subject: arch/x86/smbios: Add support for table 38 ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69161/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23513/ : SUCCESS -- To view, visit https://review.coreboot.org/25386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I66b4c4658da9d44941430d8040384d022d76f51e Gerrit-Change-Number: 25386 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 14:37:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/hp: Add new port compaq_8200_elite_sff
by build bot (Jenkins) (Code Review) 28 Mar '18

28 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25385 ) Change subject: mb/hp: Add new port compaq_8200_elite_sff ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69160/ : SUCCESS -- To view, visit https://review.coreboot.org/25385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4ee8da6349222fda8b6c30a7210ffdd65c183439 Gerrit-Change-Number: 25385 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 14:33:27 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: [WIP]util/intemetool: Add P2SB interface support
by build bot (Jenkins) (Code Review) 28 Mar '18

28 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25402 ) Change subject: [WIP]util/intemetool: Add P2SB interface support ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69159/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23512/ : SUCCESS -- To view, visit https://review.coreboot.org/25402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6e67238095856d9937f8f392b8113d99af4cd186 Gerrit-Change-Number: 25402 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 14:28:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/intelmetool: Fix bootguard dump
by build bot (Jenkins) (Code Review) 28 Mar '18

28 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25400 ) Change subject: util/intelmetool: Fix bootguard dump ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69157/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23510/ : SUCCESS -- To view, visit https://review.coreboot.org/25400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib6c49ee39dd9962a4981e7de19b1c98c753f2944 Gerrit-Change-Number: 25400 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 14:25:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/intelmetool: Add support for platforms without RCBA
by build bot (Jenkins) (Code Review) 28 Mar '18

28 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25399 ) Change subject: util/intelmetool: Add support for platforms without RCBA ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69156/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23509/ : SUCCESS -- To view, visit https://review.coreboot.org/25399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7926aa80b132d5be9fece0724516701d74dd4d3d Gerrit-Change-Number: 25399 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 14:21:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP]util/intemetool: Add P2SB interface support
by Patrick Rudolph (Code Review) 28 Mar '18

28 Mar '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25402 Change subject: [WIP]util/intemetool: Add P2SB interface support ...................................................................... [WIP]util/intemetool: Add P2SB interface support Try to unhide HECI using P2SB interface. Tests showed that it's not possible to toggle HECI after the interface has been locked. Maybe some other bits need to be toggled first. TODO: Needs test on hardware that hides the interface. Change-Id: I6e67238095856d9937f8f392b8113d99af4cd186 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/intelmetool/Makefile M util/intelmetool/intelmetool.c A util/intelmetool/p2sb.c A util/intelmetool/p2sb.h 4 files changed, 255 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/25402/1 diff --git a/util/intelmetool/Makefile b/util/intelmetool/Makefile index b455a0e..850c46b 100644 --- a/util/intelmetool/Makefile +++ b/util/intelmetool/Makefile @@ -18,9 +18,10 @@ INSTALL ?= /usr/bin/install PREFIX ?= /usr/local CFLAGS ?= -O0 -g -Wall -W -Wno-unused-parameter -Wno-sign-compare -Wno-unused-function +CFLAGS += -I../../src/commonlib/include LDFLAGS += -lpci -lz -OBJS = intelmetool.o me.o me_status.o mmap.o rcba.o msr.o +OBJS = intelmetool.o me.o me_status.o mmap.o rcba.o msr.o p2sb.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/intelmetool/intelmetool.c b/util/intelmetool/intelmetool.c index 0e75a50..34a8012 100644 --- a/util/intelmetool/intelmetool.c +++ b/util/intelmetool/intelmetool.c @@ -28,11 +28,13 @@ #include "mmap.h" #include "msr.h" #include "rcba.h" +#include "p2sb.h" extern int fd_mem; int debug = 0; static uint32_t fd2 = 0; +static uint32_t psfx_t0_shdw_pcien = 0; static int ME_major_ver = 0; static int ME_minor_ver = 0; @@ -176,6 +178,11 @@ return 0; } +#define PSF_BASE_ADDRESS 0xA00 +#define PCR_PSFX_T0_SHDW_PCIEN 0x1C +#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) +#define PID_PSF1 0xBA + static int activate_me(void) { const uint32_t rcba = get_rcba_phys(); @@ -194,6 +201,21 @@ printf("MEI was hidden on PCI, now unlocked\n"); else if (debug) printf("MEI not hidden on PCI, checking if visible\n"); + } else { + const uint64_t p2sb = get_p2sb_phys(); + if (debug) + printf("P2SB bar: 0x%" PRIx64 "\n", p2sb); + if (p2sb > 0) { + if (pcr_read32(PID_PSF1, PSF_BASE_ADDRESS + + PCR_PSFX_T0_SHDW_PCIEN, + &psfx_t0_shdw_pcien)) + printf("Error reading PCR\n"); + + if (pcr_and32(PID_PSF1, PSF_BASE_ADDRESS + + PCR_PSFX_T0_SHDW_PCIEN, + ~PCR_PSFX_T0_SHDW_PCIEN_FUNDIS)) + printf("Error writing PCR\n"); + } } return 0; @@ -217,6 +239,15 @@ if (debug) printf("done\n"); } + } else { + const uint64_t p2sb = get_p2sb_phys(); + if (p2sb > 0 && + (psfx_t0_shdw_pcien & PCR_PSFX_T0_SHDW_PCIEN_FUNDIS)) { + if (pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + + PCR_PSFX_T0_SHDW_PCIEN, + PCR_PSFX_T0_SHDW_PCIEN_FUNDIS)) + printf("Error writing PCR\n"); + } } } diff --git a/util/intelmetool/p2sb.c b/util/intelmetool/p2sb.c new file mode 100644 index 0000000..28ce46f --- /dev/null +++ b/util/intelmetool/p2sb.c @@ -0,0 +1,204 @@ +/* + * Copyright (C) 2014 Damien Zammit <damien(a)zamaudio.com> + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdio.h> +#include <inttypes.h> + +#include "intelmetool.h" +#include "mmap.h" +#include "p2sb.h" +#include "assert.h" +#include "commonlib/helpers.h" + +static const int size = 0x1000000; + +/* Returns the physical P2SB base address or zero on error. */ +u64 get_p2sb_phys(void) +{ + struct pci_access *pacc; + struct pci_dev *sb; + uint64_t p2sb_phys = 0; + + pacc = pci_alloc(); + pacc->method = PCI_ACCESS_I386_TYPE1; + + pci_init(pacc); + pci_scan_bus(pacc); + + sb = pci_get_dev(pacc, 0, 0, 0x1f, 1); + if (!sb) { + printf("Uh oh, southbridge not on BDF(0:31:1), please report " + "this error, exiting.\n"); + pci_cleanup(pacc); + return 0; + } + pci_fill_info(sb, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_SIZES | + PCI_FILL_CLASS); + + const u8 reg8 = pci_read_byte(sb, 0xe1); + + if (pci_read_byte(sb, 0xe2) & 2) { + static int once; + if (!once) + printf("Warning: Endpoint Mask Lock Bit set !\n"); + once = 1; + } + + /* Make device visible */ + pci_write_byte(sb, 0xe1, 0); + + /* someone home ? */ + if (pci_read_word(sb, 0) == 0x0000 || + pci_read_word(sb, 0) == 0xffff) + goto out; + + /* Probe for memory bar */ + if (pci_read_long(sb, 0x10) & 1) + goto out; + + /* Get Sideband Register Access address */ + if ((pci_read_long(sb, 0x10) & 0x6) == 0x0) + p2sb_phys = pci_read_long(sb, 0x10) & 0xfffffff8UL; + else if ((pci_read_long(sb, 0x10) & 0x6) == 0x4) + p2sb_phys = (pci_read_long(sb, 0x10) & 0xfffffff8UL) | + (((unsigned long long)pci_read_long(sb, 0x14)) << 32); + +out: + /* Make device invisible */ + pci_write_byte(sb, 0xe1, reg8 | 1); + + pci_free_dev(sb); + pci_cleanup(pacc); + + return p2sb_phys; +} + +/* + * Writes 'val' to P2SB register at address 'addr'. + * Returns 1 on error and 0 on success. + */ +static int write_p2sb32(uint32_t addr, uint32_t val) +{ + volatile uint8_t *p2sb; + const uint64_t p2sb_phys = get_p2sb_phys(); + + if (!p2sb_phys) { + printf("Could not get P2SB address\n"); + return 1; + } + + p2sb = map_physical((off_t)p2sb_phys, size); + if (p2sb == NULL) { + printf("Could not map P2SB\n"); + return 1; + } + *(uint32_t *)(p2sb + addr) = val; + + munmap((void *)p2sb, size); + return 0; +} + +/* + * Reads P2SB register at address 'addr' and stores it in 'val'. + * Returns 1 on error and 0 on success. + */ +static int read_p2sb32(uint32_t addr, uint32_t *val) +{ + volatile uint8_t *p2sb; + const uint64_t p2sb_phys = get_p2sb_phys(); + + if (!p2sb_phys) { + printf("Could not get P2SB address\n"); + return 1; + } + + p2sb = map_physical((off_t)p2sb_phys, size); + if (p2sb == NULL) { + printf("Could not map P2SB\n"); + return 1; + } + + *val = *(uint32_t *)(p2sb + addr); + + munmap((void *)p2sb, size); + return 0; +} + +/* Port Id lives in bits 23:16 and register offset lives in 15:0 of address. */ +#define PCR_PORTID_SHIFT 16 +#define PCR_OFFSET_SHIFT 0 + +static uint32_t __pcr_reg_address(uint8_t pid, uint16_t offset) +{ + return (pid << PCR_PORTID_SHIFT) | (offset << PCR_OFFSET_SHIFT); +} + +int pcr_read32(uint8_t pid, uint16_t offset, uint32_t *val) +{ + /* Ensure the PCR offset is corretcly aligned. */ + assert(IS_ALIGNED(offset, sizeof(uint32_t))); + return read_p2sb32(__pcr_reg_address(pid, offset), val); +} +/* + * After every write one needs to perform a read an innocuous register to + * ensure the writes are completed for certain ports. This is done for + * all ports so that the callers don't need the per-port knowledge for + * each transaction. + */ +static inline int write_completion(uint8_t pid, uint16_t offset) +{ + uint32_t reg32; + uint32_t a = __pcr_reg_address(pid, ALIGN_DOWN(offset, sizeof(uint32_t))); + return read_p2sb32(a, &reg32); +} + +int pcr_write32(uint8_t pid, uint16_t offset, uint32_t indata) +{ + /* Ensure the PCR offset is corretcly aligned. */ + assert(IS_ALIGNED(offset, sizeof(indata))); + + if (write_p2sb32(__pcr_reg_address(pid, offset), indata)) + return 1; + /* Ensure the writes complete. */ + if (write_completion(pid, offset)) + return 1; + + return 0; +} + +int pcr_or32(uint8_t pid, uint16_t offset, uint32_t ordata) +{ + uint32_t data32; + + if (pcr_read32(pid, offset, &data32)) + return 1; + data32 |= ordata; + if (pcr_write32(pid, offset, data32)) + return 1; + + return 0; +} + +int pcr_and32(uint8_t pid, uint16_t offset, uint32_t anddata) +{ + uint32_t data32; + + if (pcr_read32(pid, offset, &data32)) + return 1; + data32 &= anddata; + if (pcr_write32(pid, offset, data32)) + return 1; + + return 0; +} diff --git a/util/intelmetool/p2sb.h b/util/intelmetool/p2sb.h new file mode 100644 index 0000000..f5c8515 --- /dev/null +++ b/util/intelmetool/p2sb.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +int pcr_read32(uint8_t pid, uint16_t offset, uint32_t *val); +int pcr_write32(uint8_t pid, uint16_t offset, uint32_t indata); +int pcr_or32(uint8_t pid, uint16_t offset, uint32_t ordata); +int pcr_and32(uint8_t pid, uint16_t offset, uint32_t anddata); +u64 get_p2sb_phys(void); -- To view, visit https://review.coreboot.org/25402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6e67238095856d9937f8f392b8113d99af4cd186 Gerrit-Change-Number: 25402 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: util/intelmetool: Add additional helpful error messages
by Patrick Rudolph (Code Review) 28 Mar '18

28 Mar '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25401 Change subject: util/intelmetool: Add additional helpful error messages ...................................................................... util/intelmetool: Add additional helpful error messages Add more verbose error message for common problems on modern operating systems, like Secure Boot and CONFIG_STRICT_DEVMEM. Change-Id: Ie3361910d48271bcc2cd3b4b74937fbc5df0a176 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/intelmetool/intelmetool.c M util/intelmetool/rcba.c 2 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/25401/1 diff --git a/util/intelmetool/intelmetool.c b/util/intelmetool/intelmetool.c index b87a53b..0e75a50 100644 --- a/util/intelmetool/intelmetool.c +++ b/util/intelmetool/intelmetool.c @@ -490,7 +490,8 @@ #ifndef __DARWIN__ fd_mem = open("/dev/mem", O_RDWR); if (fd_mem < 0) { - perror("Can not open /dev/mem"); + perror("Can not open /dev/mem. Do you have disabled " + "Secure Boot ?"); exit(1); } diff --git a/util/intelmetool/rcba.c b/util/intelmetool/rcba.c index c138e89..ee43e65 100644 --- a/util/intelmetool/rcba.c +++ b/util/intelmetool/rcba.c @@ -68,7 +68,8 @@ rcba = map_physical((off_t)rcba_phys, size); if (rcba == NULL) { - printf("Could not map RCBA\n"); + printf("Could not map RCBA\n" + "Do you have cmdline argument 'iomem=relaxed' set ?\n"); return 1; } *(uint32_t *)(rcba + addr) = val; @@ -93,7 +94,8 @@ rcba = map_physical((off_t)rcba_phys, size); if (rcba == NULL) { - printf("Could not map RCBA\n"); + printf("Could not map RCBA\n" + "Do you have cmdline argument 'iomem=relaxed' set ?\n"); return 1; } -- To view, visit https://review.coreboot.org/25401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie3361910d48271bcc2cd3b4b74937fbc5df0a176 Gerrit-Change-Number: 25401 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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coreboot-gerrit March 2018