coreboot-gerrit March 2018

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Change in coreboot[master]: purism/librem13v1: Disable PCI Express AER capability
by Matt DeVillier (Code Review) 28 Mar '18

28 Mar '18

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/25327 ) Change subject: purism/librem13v1: Disable PCI Express AER capability ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/25327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I13d0afa085b426920d7a946e6209f924ce29ae52 Gerrit-Change-Number: 25327 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 18:39:55 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/broadwell: Add option to disable PCIe AER capability
by Matt DeVillier (Code Review) 28 Mar '18

28 Mar '18

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/25326 ) Change subject: soc/intel/broadwell: Add option to disable PCIe AER capability ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/25326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If2e0ec42c93f1fee927eacdf0099004cf9302fbe Gerrit-Change-Number: 25326 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 18:39:51 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/broadwell: If L1 Sub state is disabled, do not set capability
by Matt DeVillier (Code Review) 28 Mar '18

28 Mar '18

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/25325 ) Change subject: soc/intel/broadwell: If L1 Sub state is disabled, do not set capability ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/25325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I293a650db307e77cee024a43fbfc81e1d8c86265 Gerrit-Change-Number: 25325 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 18:39:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: arch/x86/smbios: Consider corner case of Part Number
by build bot (Jenkins) (Code Review) 28 Mar '18

28 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25377 ) Change subject: arch/x86/smbios: Consider corner case of Part Number ...................................................................... Patch Set 9: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69173/ : SUCCESS -- To view, visit https://review.coreboot.org/25377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id870c983584771dc1b60b1c99e95bbe7c0d25c4c Gerrit-Change-Number: 25377 Gerrit-PatchSet: 9 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)google.com> Gerrit-Comment-Date: Wed, 28 Mar 2018 18:02:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/apollolake: Save/restore GMA OpRegion address
by build bot (Jenkins) (Code Review) 28 Mar '18

28 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25416 ) Change subject: soc/intel/apollolake: Save/restore GMA OpRegion address ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69172/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23523/ : SUCCESS -- To view, visit https://review.coreboot.org/25416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4123998b0ab3c263c6a9ff14084a0d8808e5f4cd Gerrit-Change-Number: 25416 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 17:49:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Fix Trackpad interrupt GPIO config
by build bot (Jenkins) (Code Review) 28 Mar '18

28 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25415 ) Change subject: mb/google/octopus: Fix Trackpad interrupt GPIO config ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69171/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23522/ : SUCCESS -- To view, visit https://review.coreboot.org/25415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icc416e7be4e42bda188f74c69db150ba42562128 Gerrit-Change-Number: 25415 Gerrit-PatchSet: 1 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 17:46:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake: Save/restore GMA OpRegion address
by Matt DeVillier (Code Review) 28 Mar '18

28 Mar '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/25416 Change subject: soc/intel/apollolake: Save/restore GMA OpRegion address ...................................................................... soc/intel/apollolake: Save/restore GMA OpRegion address Add global/ACPI nvs variables required for IGD OpRegion. Add functions necessary to save the ACPI OpRegion table address in ASLB, and restore table address upon S3 resume. Implementation modeled on existing Baytrail code. Change-Id: I4123998b0ab3c263c6a9ff14084a0d8808e5f4cd Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/apollolake/graphics.c M src/soc/intel/apollolake/include/soc/nvs.h 3 files changed, 105 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/25416/1 diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 4aad29c..426ea5b 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -46,6 +46,48 @@ EMNA, 64, // 0x2D - 0x34 EPC base address ELNG, 64, // 0x35 - 0x3C EPC Length + /* IGD OpRegion */ + Offset (0xb4), + ASLB, 32, // 0xb4 - IGD OpRegion Base Address + IBTT, 8, // 0xb8 - IGD boot panel device + IPAT, 8, // 0xb9 - IGD panel type cmos option + ITVF, 8, // 0xba - IGD TV format cmos option + ITVM, 8, // 0xbb - IGD TV minor format option + IPSC, 8, // 0xbc - IGD panel scaling + IBLC, 8, // 0xbd - IGD BLC config + IBIA, 8, // 0xbe - IGD BIA config + ISSC, 8, // 0xbf - IGD SSC config + I409, 8, // 0xc0 - IGD 0409 modified settings + I509, 8, // 0xc1 - IGD 0509 modified settings + I609, 8, // 0xc2 - IGD 0609 modified settings + I709, 8, // 0xc3 - IGD 0709 modified settings + IDMM, 8, // 0xc4 - IGD Power conservation feature + IDMS, 8, // 0xc5 - IGD DVMT memory size + IF1E, 8, // 0xc6 - IGD function 1 enable + HVCO, 8, // 0xc7 - IGD HPLL VCO + NXD1, 32, // 0xc8 - IGD _DGS next DID1 + NXD2, 32, // 0xcc - IGD _DGS next DID2 + NXD3, 32, // 0xd0 - IGD _DGS next DID3 + NXD4, 32, // 0xd4 - IGD _DGS next DID4 + NXD5, 32, // 0xd8 - IGD _DGS next DID5 + NXD6, 32, // 0xdc - IGD _DGS next DID6 + NXD7, 32, // 0xe0 - IGD _DGS next DID7 + NXD8, 32, // 0xe4 - IGD _DGS next DID8 + + ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) + PAVP, 8, // 0xe9 - IGD PAVP data + Offset (0xeb), + OSCC, 8, // 0xeb - PCIe OSC control + NPCE, 8, // 0xec - native pcie support + PLFL, 8, // 0xed - platform flavor + BREV, 8, // 0xee - board revision + DPBM, 8, // 0xef - digital port b mode + DPCM, 8, // 0xf0 - digital port c mode + DPDM, 8, // 0xf1 - digital port d mode + ALFP, 8, // 0xf2 - active lfp + IMON, 8, // 0xf3 - current graphics turbo imon value + MMIO, 8, // 0xf4 - 64bit mmio support + /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 4857788..52fc8eb 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -16,12 +16,35 @@ */ #include <arch/acpigen.h> +#include <cbmem.h> #include <console/console.h> #include <fsp/util.h> #include <device/device.h> #include <device/pci.h> #include <intelblocks/graphics.h> #include <drivers/intel/gma/opregion.h> +#include <soc/nvs.h> + +void graphics_soc_init(struct device *dev) +{ + pci_dev_init(dev); + + intel_gma_restore_opregion(); +} + +uintptr_t gma_get_gnvs_aslb(const void *gnvs) +{ + const global_nvs_t *gnvs_ptr = gnvs; + return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); +} + +void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) +{ + global_nvs_t *gnvs_ptr = gnvs; + if (gnvs_ptr) + gnvs_ptr->aslb = aslb; +} + uintptr_t fsp_soc_get_igd_bar(void) { @@ -32,6 +55,7 @@ uintptr_t current, struct acpi_rsdp *rsdp) { igd_opregion_t *opregion; + global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); opregion = (igd_opregion_t *)current; @@ -39,6 +63,9 @@ if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) return current; + if (gnvs) + gnvs->aslb = (u32)(uintptr_t)opregion; + /* FIXME: Add platform specific mailbox initialization */ current += sizeof(igd_opregion_t); diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index c7be979..0b054da 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -48,7 +48,42 @@ uint8_t ecps; /* 0x2C - SGX Enabled status */ uint64_t emna; /* 0x2D - 0x34 EPC base address */ uint64_t elng; /* 0x35 - 0x3C EPC Length */ - uint8_t unused[195]; + uint8_t unused[119]; + + /* IGD OpRegion */ + u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ + u8 ibtt; /* 0xb8 - IGD boot type */ + u8 ipat; /* 0xb9 - IGD panel type */ + u8 itvf; /* 0xba - IGD TV format */ + u8 itvm; /* 0xbb - IGD TV minor format */ + u8 ipsc; /* 0xbc - IGD Panel Scaling */ + u8 iblc; /* 0xbd - IGD BLC configuration */ + u8 ibia; /* 0xbe - IGD BIA configuration */ + u8 issc; /* 0xbf - IGD SSC configuration */ + u8 i409; /* 0xc0 - IGD 0409 modified settings */ + u8 i509; /* 0xc1 - IGD 0509 modified settings */ + u8 i609; /* 0xc2 - IGD 0609 modified settings */ + u8 i709; /* 0xc3 - IGD 0709 modified settings */ + u8 idmm; /* 0xc4 - IGD Power Conservation */ + u8 idms; /* 0xc5 - IGD DVMT memory size */ + u8 if1e; /* 0xc6 - IGD Function 1 Enable */ + u8 hvco; /* 0xc7 - IGD HPLL VCO */ + u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ + u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ + u8 pavp; /* 0xe9 - IGD PAVP data */ + u8 rsvd12; /* 0xea - rsvd */ + u8 oscc; /* 0xeb - PCIe OSC control */ + u8 npce; /* 0xec - native pcie support */ + u8 plfl; /* 0xed - platform flavor */ + u8 brev; /* 0xee - board revision */ + u8 dpbm; /* 0xef - digital port b mode */ + u8 dpcm; /* 0xf0 - digital port c mode */ + u8 dpdm; /* 0xf1 - digital port c mode */ + u8 alfp; /* 0xf2 - active lfp */ + u8 imon; /* 0xf3 - current graphics turbo imon value */ + u8 mmio; /* 0xf4 - 64bit mmio support */ + + u8 unused2[11]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; -- To view, visit https://review.coreboot.org/25416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4123998b0ab3c263c6a9ff14084a0d8808e5f4cd Gerrit-Change-Number: 25416 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: mb/google/octopus: Fix Trackpad interrupt GPIO config
by Hannah Williams (Code Review) 28 Mar '18

28 Mar '18

Hannah Williams has uploaded this change for review. ( https://review.coreboot.org/25415 Change subject: mb/google/octopus: Fix Trackpad interrupt GPIO config ...................................................................... mb/google/octopus: Fix Trackpad interrupt GPIO config BUG=b:73137125 TEST= tested trackpad on Octopus Change-Id: Icc416e7be4e42bda188f74c69db150ba42562128 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- M src/mainboard/google/octopus/variants/baseboard/gpio.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/25415/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 1570223..67761d5 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -191,7 +191,7 @@ // TODO Need to set HIZCRx1 PAD_CFG_GPI(GPIO_134, NONE, DEEP),/* GPIO_134 -- SD_CD_OD */ - PAD_CFG_GPI_APIC_IOS(GPIO_135, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ + PAD_CFG_GPI_APIC_LOW(GPIO_135, NONE, DEEP),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */ PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_137 -- HP_INT_ODL */ PAD_CFG_GPI(GPIO_138, NONE, DEEP),/* GPIO_138 -- PEN_PDCT_ODL */ @@ -201,8 +201,7 @@ // Settings here do not match table // Also we may be able to use eSPI WAKE# Virtual Wire instead PAD_CFG_GPI_SCI_IOS(GPIO_141, UP_20K, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ - //TODO Check all pad settings. Table did not specify interrupt properties. This should be an SCI. - //PAD_CFG_NF_IOSSTATE(GPIO_142, NONE, DEEP, TxDRxE, DISPUPD),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL */ + PAD_CFG_GPI_SCI_LOW(GPIO_142, NONE, DEEP, EDGE_SINGLE),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_143, 1, DEEP, UP_20K, HIZCRx1, ENPU),/* GPIO_143 -- LTE_SAR_ODL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_144, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* PANEL1_VDDN */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_145, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* PANEL1_BKLTEN */ -- To view, visit https://review.coreboot.org/25415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icc416e7be4e42bda188f74c69db150ba42562128 Gerrit-Change-Number: 25415 Gerrit-PatchSet: 1 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com>

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Change in coreboot[master]: src/sb/intel/common/spi.c: Adapt and link in romstage
by build bot (Jenkins) (Code Review) 28 Mar '18

28 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25414 ) Change subject: src/sb/intel/common/spi.c: Adapt and link in romstage ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69170/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23521/ : SUCCESS -- To view, visit https://review.coreboot.org/25414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4671653c0b07ab5c4bf91128f18f142ce4f893cf Gerrit-Change-Number: 25414 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 17:24:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: drivers/spi/flashconsole.c: Fix broken header
by build bot (Jenkins) (Code Review) 28 Mar '18

28 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25413 ) Change subject: drivers/spi/flashconsole.c: Fix broken header ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69169/ : SUCCESS -- To view, visit https://review.coreboot.org/25413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I61d28791fa75a32591448fc2c40186acfddca86d Gerrit-Change-Number: 25413 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 17:21:51 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit March 2018