coreboot-gerrit March 2018

coreboot-gerrit@coreboot.org

1 participants
1399 discussions

Change in coreboot[master]: util/intelmetool: Fix bootguard dump
by Patrick Rudolph (Code Review) 28 Mar '18

28 Mar '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25400 Change subject: util/intelmetool: Fix bootguard dump ...................................................................... util/intelmetool: Fix bootguard dump * Fix broken bootguard report on Intel ME 9.5+ * Fix broken debug statement * Add additional rehide_me() * Move last rehide_me() Tested on Lenovo T470p. It shows correct BootGuard state: Verified & Measured Boot. Tested on Lenovo T430. It shows correct BootGuard state: Disabled. Change-Id: Ib6c49ee39dd9962a4981e7de19b1c98c753f2944 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/intelmetool/intelmetool.c 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/25400/1 diff --git a/util/intelmetool/intelmetool.c b/util/intelmetool/intelmetool.c index 4c74a0a..b87a53b 100644 --- a/util/intelmetool/intelmetool.c +++ b/util/intelmetool/intelmetool.c @@ -322,7 +322,7 @@ { struct pci_dev *dev; char namebuf[1024]; - const char *name; + const char *name = NULL; uint64_t bootguard = 0; if (pci_platform_scan()) @@ -342,16 +342,10 @@ } } - if (debug) { - printf("BootGuard MSR Output: 0x%" PRIx64 "\n", bootguard); - bootguard &= ~0xff; - } - /* ME_major_ver is zero on some platforms (Mac) */ if (ME_major_ver && (ME_major_ver < 9 || - (ME_major_ver == 9 && ME_minor_ver < 5) || - !BOOTGUARD_CAPABILITY(bootguard))) { + (ME_major_ver == 9 && ME_minor_ver < 5))) { print_cap("BootGuard ", 0); printf(CGRN "\nYour system isn't bootguard ready. You can " "flash other firmware!\n" RESET); @@ -362,15 +356,22 @@ if (msr_bootguard(&bootguard, debug) < 0) { printf("ME Capability: %-43s: " CCYN "%s\n" RESET, "BootGuard Mode", "Unknown"); + rehide_me(); return; } + if (debug) { + printf("BootGuard MSR Output: 0x%" PRIx64 "\n", bootguard); + bootguard &= ~0xff; + } + print_cap("BootGuard ", 1); if (pci_read_long(dev, 0x40) & 0x10) printf(CYEL "Your southbridge configuration is insecure!! " "BootGuard keys can be overwritten or wiped, or you are " "in developer mode.\n" RESET); + rehide_me(); switch (bootguard) { case BOOTGUARD_DISABLED: @@ -399,7 +400,6 @@ "firmware.\n" RESET); break; } - rehide_me(); } static void print_version(void) -- To view, visit https://review.coreboot.org/25400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib6c49ee39dd9962a4981e7de19b1c98c753f2944 Gerrit-Change-Number: 25400 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

1 0

Change in coreboot[master]: util/intelmetool: Add support for platforms without RCBA
by Patrick Rudolph (Code Review) 28 Mar '18

28 Mar '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25399 Change subject: util/intelmetool: Add support for platforms without RCBA ...................................................................... util/intelmetool: Add support for platforms without RCBA Only try to unhide MEI if the PCI device wasn't found and probe for RCBA before trying to use it. Allows to run the utility on Skylake and newer hardware that do not have RCBA any more. TODO: Use sideband interface to unhide MEI. Change-Id: I7926aa80b132d5be9fece0724516701d74dd4d3d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/intelmetool/intelmetool.c M util/intelmetool/rcba.c M util/intelmetool/rcba.h 3 files changed, 56 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/25399/1 diff --git a/util/intelmetool/intelmetool.c b/util/intelmetool/intelmetool.c index 9de6bb5..4c74a0a 100644 --- a/util/intelmetool/intelmetool.c +++ b/util/intelmetool/intelmetool.c @@ -178,38 +178,45 @@ static int activate_me(void) { - if (read_rcba32(FD2, &fd2)) { - printf("Error reading RCBA\n"); - return 1; - } - if (write_rcba32(FD2, fd2 & ~0x2)) { - printf("Error writing RCBA\n"); - return 1; - } - if (debug) { - if (fd2 & 0x2) + const uint32_t rcba = get_rcba_phys(); + if (debug) + printf("RCBA addr: 0x%08x\n", rcba); + if (rcba > 0) { + if (read_rcba32(FD2, &fd2)) { + printf("Error reading RCBA\n"); + return 1; + } + if (write_rcba32(FD2, fd2 & ~0x2)) { + printf("Error writing RCBA\n"); + return 1; + } + if (debug && (fd2 & 0x2)) printf("MEI was hidden on PCI, now unlocked\n"); - else + else if (debug) printf("MEI not hidden on PCI, checking if visible\n"); } + return 0; } static void rehide_me(void) { - if (fd2 & 0x2) { - if (debug) - printf("Re-hiding MEI device..."); - if (read_rcba32(FD2, &fd2)) { - printf("Error reading RCBA\n"); - return; + const uint32_t rcba = get_rcba_phys(); + if (rcba > 0) { + if (fd2 & 0x2) { + if (debug) + printf("Re-hiding MEI device..."); + if (read_rcba32(FD2, &fd2)) { + printf("Error reading RCBA\n"); + return; + } + if (write_rcba32(FD2, fd2 | 0x2)) { + printf("Error writing RCBA\n"); + return; + } + if (debug) + printf("done\n"); } - if (write_rcba32(FD2, fd2 | 0x2)) { - printf("Error writing RCBA\n"); - return; - } - if (debug) - printf("done\n"); } } @@ -243,7 +250,6 @@ if (!me) { rehide_me(); - printf("MEI device not found\n"); pci_cleanup(pacc); return NULL; } @@ -259,14 +265,21 @@ const char *name = NULL; if (pci_platform_scan()) - exit(1); - - if (activate_me()) - exit(1); + return; dev = pci_me_interface_scan(&name, namebuf, sizeof(namebuf)); - if (!dev) - exit(1); + if (!dev) { + if (debug) + printf("ME PCI device is hidden\n"); + + if (activate_me()) + return; + dev = pci_me_interface_scan(&name, namebuf, sizeof(namebuf)); + if (!dev) { + printf("Can't find ME PCI device\n"); + return; + } + } if (name == NULL) name = "<unknown>"; @@ -313,15 +326,20 @@ uint64_t bootguard = 0; if (pci_platform_scan()) - exit(1); - - if (activate_me()) - exit(1); + return; dev = pci_me_interface_scan(&name, namebuf, sizeof(namebuf)); if (!dev) { - printf("Can't access ME PCI device\n"); - return; + if (debug) + printf("ME PCI device is hidden\n"); + + if (activate_me()) + return; + dev = pci_me_interface_scan(&name, namebuf, sizeof(namebuf)); + if (!dev) { + printf("Can't find ME PCI device\n"); + return; + } } if (debug) { diff --git a/util/intelmetool/rcba.c b/util/intelmetool/rcba.c index fcc9bc5..c138e89 100644 --- a/util/intelmetool/rcba.c +++ b/util/intelmetool/rcba.c @@ -22,7 +22,7 @@ static const int size = 0x4000; /* Returns the physical RCBA base address or zero on error. */ -static u32 get_rcba_phys(void) +u32 get_rcba_phys(void) { struct pci_access *pacc; struct pci_dev *sb; diff --git a/util/intelmetool/rcba.h b/util/intelmetool/rcba.h index e1a22be..e349d3d 100644 --- a/util/intelmetool/rcba.h +++ b/util/intelmetool/rcba.h @@ -13,3 +13,4 @@ int write_rcba32(uint32_t addr, uint32_t val); int read_rcba32(uint32_t addr, uint32_t *val); +u32 get_rcba_phys(void); -- To view, visit https://review.coreboot.org/25399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7926aa80b132d5be9fece0724516701d74dd4d3d Gerrit-Change-Number: 25399 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

1 0

Change in coreboot[master]: util/intelmetool: Fix crash on strict devmem kernels
by Patrick Rudolph (Code Review) 28 Mar '18

28 Mar '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25398 Change subject: util/intelmetool: Fix crash on strict devmem kernels ...................................................................... util/intelmetool: Fix crash on strict devmem kernels Don't crash if mapping MEI PCI memory fails. This can happen if CONFIG_STRICT_DEVMEM is enabled. Change-Id: I33c75a7cccb4cefaa26f70aed4bdc4bd620cdad0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/intelmetool/intelmetool.c M util/intelmetool/me.c 2 files changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/25398/1 diff --git a/util/intelmetool/intelmetool.c b/util/intelmetool/intelmetool.c index 0b0e509..9de6bb5 100644 --- a/util/intelmetool/intelmetool.c +++ b/util/intelmetool/intelmetool.c @@ -287,17 +287,21 @@ printf("ME: has a broken implementation on your board with" "this firmware\n"); - intel_mei_setup(dev); + if (intel_mei_setup(dev)) + goto out; usleep(ME_COMMAND_DELAY); mei_reset(); usleep(ME_COMMAND_DELAY); - mkhi_get_fw_version(&ME_major_ver, &ME_minor_ver); + if (mkhi_get_fw_version(&ME_major_ver, &ME_minor_ver)) + goto out; usleep(ME_COMMAND_DELAY); mei_reset(); usleep(ME_COMMAND_DELAY); - mkhi_get_fwcaps(); + if (mkhi_get_fwcaps()) + goto out; usleep(ME_COMMAND_DELAY); +out: rehide_me(); } diff --git a/util/intelmetool/me.c b/util/intelmetool/me.c index 6517022..f14f4cd 100644 --- a/util/intelmetool/me.c +++ b/util/intelmetool/me.c @@ -582,7 +582,8 @@ mei_mmap = map_physical(pagerounded, 0x2000); mei_mmap += mei_base_address - pagerounded; if (mei_mmap == NULL) { - printf("Could not map ME setup memory\n"); + printf("Could not map ME setup memory.\n" + "Do you have cmdline argument 'iomem=relaxed' set ?\n"); return 1; } -- To view, visit https://review.coreboot.org/25398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I33c75a7cccb4cefaa26f70aed4bdc4bd620cdad0 Gerrit-Change-Number: 25398 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

1 0

Change in coreboot[master]: [wip] driver/option_table: add option table interface
by build bot (Jenkins) (Code Review) 28 Mar '18

28 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25397 ) Change subject: [wip] driver/option_table: add option table interface ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/69154/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/23507/ : SUCCESS -- To view, visit https://review.coreboot.org/25397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I19b0215170e940c4973e60cbad3d7186a3063cc2 Gerrit-Change-Number: 25397 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <marcello.bauer(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 12:26:07 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: [wip] driver/option_table: add option table interface
by Marcello Sylvester Bauer (Code Review) 28 Mar '18

28 Mar '18

Marcello Sylvester Bauer has uploaded this change for review. ( https://review.coreboot.org/25397 Change subject: [wip] driver/option_table: add option table interface ...................................................................... [wip] driver/option_table: add option table interface introduce an interface for option table, so that other non-volatile storage can be used. This will benefit machines without CMOS as well as those without a battery-backed CMOS TODO: Support VPD read-write section as option table Change-Id: I19b0215170e940c4973e60cbad3d7186a3063cc2 Signed-off-by: Marcello Sylvester Bauer <marcello.bauer(a)9elements.com> --- M src/Kconfig A src/drivers/option_table/Makefile.inc A src/drivers/option_table/option_table_cmos.c M src/drivers/pc80/rtc/mc146818rtc.c M src/include/option.h M src/include/pc80/mc146818rtc.h 6 files changed, 48 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/25397/1 diff --git a/src/Kconfig b/src/Kconfig index 99a704d..38cf13a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -113,11 +113,23 @@ Otherwise, say N to use the provided pregenerated scanner/parser. config USE_OPTION_TABLE - bool "Use CMOS for configuration values" + bool "Use an option table for configuration values" + help + Enable this option if coreboot shall use an option table + instead of hard-coded values. + +choice + prompt "option table to use" + depends on USE_OPTION_TABLE + default USE_OPTION_TABLE_CMOS + +config USE_OPTION_TABLE_CMOS + bool "CMOS" depends on HAVE_OPTION_TABLE help - Enable this option if coreboot shall read options from the "CMOS" - NVRAM instead of using hard-coded values. + read options from the "CMOS" NVRAM + +endchoice config STATIC_OPTION_TABLE bool "Load default configuration values into CMOS on each boot" diff --git a/src/drivers/option_table/Makefile.inc b/src/drivers/option_table/Makefile.inc new file mode 100644 index 0000000..5c07e34 --- /dev/null +++ b/src/drivers/option_table/Makefile.inc @@ -0,0 +1,3 @@ +ifeq ($(CONFIG_USE_OPTION_TABLE_CMOS),y) +ramstage-y += option_table_cmos.c +endif diff --git a/src/drivers/option_table/option_table_cmos.c b/src/drivers/option_table/option_table_cmos.c new file mode 100644 index 0000000..b839f74 --- /dev/null +++ b/src/drivers/option_table/option_table_cmos.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <option.h> +#include <pc80/mc146818rtc.h> + +enum cb_err get_option(void *dest, const char *name) +{ + return get_option_cmos(dest, name); +} diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 928b403..f75dd27 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -240,7 +240,7 @@ return CB_SUCCESS; } -enum cb_err get_option(void *dest, const char *name) +enum cb_err get_option_cmos(void *dest, const char *name) { struct cmos_option_table *ct; struct cmos_entries *ce; diff --git a/src/include/option.h b/src/include/option.h index f6ede96..07ee4b6 100644 --- a/src/include/option.h +++ b/src/include/option.h @@ -6,10 +6,12 @@ * storage can be used. This will benefit machines without CMOS as well as those * without a battery-backed CMOS (e.g. some laptops). */ -#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) -#include <pc80/mc146818rtc.h> -#else + #include <types.h> + +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) +enum cb_err get_option(void *dest, const char *name); +#else static inline enum cb_err get_option(void *dest, const char *name) { return CB_CMOS_OTABLE_DISABLED; diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 5d7497d..bc6c99e 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -183,7 +183,7 @@ void cmos_check_update_date(void); enum cb_err set_option(const char *name, void *val); -enum cb_err get_option(void *dest, const char *name); +enum cb_err get_option_cmos(void *dest, const char *name); unsigned int read_option_lowlevel(unsigned int start, unsigned int size, unsigned int def); -- To view, visit https://review.coreboot.org/25397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I19b0215170e940c4973e60cbad3d7186a3063cc2 Gerrit-Change-Number: 25397 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <marcello.bauer(a)9elements.com>

1 0

Change in coreboot[master]: spi: Add helper functions for bit-banging
by build bot (Jenkins) (Code Review) 28 Mar '18

28 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25394 ) Change subject: spi: Add helper functions for bit-banging ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69153/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23506/ : SUCCESS -- To view, visit https://review.coreboot.org/25394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie3551f51cc9a9f8bf3a47fd5cea6d9c064da8a62 Gerrit-Change-Number: 25394 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 05:36:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: rockchip: Add gpio_set() function
by build bot (Jenkins) (Code Review) 28 Mar '18

28 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25393 ) Change subject: rockchip: Add gpio_set() function ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69152/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23505/ : SUCCESS -- To view, visit https://review.coreboot.org/25393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I201288139a2870e71f55a7af0d79d4a460b30a0c Gerrit-Change-Number: 25393 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 05:34:32 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/google/octopus: update SSP port and DMIC 4CH nhlt support
by build bot (Jenkins) (Code Review) 28 Mar '18

28 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25387 ) Change subject: mb/google/octopus: update SSP port and DMIC 4CH nhlt support ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69151/ : SUCCESS -- To view, visit https://review.coreboot.org/25387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I101ed80f4421925120116b018424ef19d95a2a3a Gerrit-Change-Number: 25387 Gerrit-PatchSet: 4 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Naveen Manohar <naveen.m(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 05:09:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/google/octopus: update SSP port and DMIC 4CH nhlt support
by build bot (Jenkins) (Code Review) 28 Mar '18

28 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25387 ) Change subject: mb/google/octopus: update SSP port and DMIC 4CH nhlt support ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69150/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/23504/ : SUCCESS -- To view, visit https://review.coreboot.org/25387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I101ed80f4421925120116b018424ef19d95a2a3a Gerrit-Change-Number: 25387 Gerrit-PatchSet: 3 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Naveen Manohar <naveen.m(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 05:05:55 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/google/octopus: update SSP port and DMIC 4CH nhlt support
by build bot (Jenkins) (Code Review) 28 Mar '18

28 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25387 ) Change subject: mb/google/octopus: update SSP port and DMIC 4CH nhlt support ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69149/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/23503/ : SUCCESS -- To view, visit https://review.coreboot.org/25387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I101ed80f4421925120116b018424ef19d95a2a3a Gerrit-Change-Number: 25387 Gerrit-PatchSet: 2 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Naveen Manohar <naveen.m(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Mar 2018 05:01:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2018