coreboot-gerrit March 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: lib/bootmem: Extend bootmem_allocate_buffer
by build bot (Jenkins) (Code Review) 27 Mar '18

27 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25383 ) Change subject: lib/bootmem: Extend bootmem_allocate_buffer ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69109/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23463/ : SUCCESS -- To view, visit https://review.coreboot.org/25383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0c983ce43616147c519a43edee3b61d54eadbb9a Gerrit-Change-Number: 25383 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 13:41:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/cavium: Apply additional devicetree fixups
by build bot (Jenkins) (Code Review) 27 Mar '18

27 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25382 ) Change subject: soc/cavium: Apply additional devicetree fixups ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69107/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23461/ : SUCCESS -- To view, visit https://review.coreboot.org/25382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e8eefd913915a879dad28dfb7801a2018ed2985 Gerrit-Change-Number: 25382 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 13:35:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/cavium: Enable MMU
by build bot (Jenkins) (Code Review) 27 Mar '18

27 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25371 ) Change subject: soc/cavium: Enable MMU ...................................................................... Patch Set 2: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69105/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23459/ : SUCCESS -- To view, visit https://review.coreboot.org/25371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I969446da62b4cc7adf9393fab69ff84ebf49220d Gerrit-Change-Number: 25371 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 13:34:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: lib/bootmem: Extend bootmem_allocate_buffer
by Patrick Rudolph (Code Review) 27 Mar '18

27 Mar '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25383 Change subject: lib/bootmem: Extend bootmem_allocate_buffer ...................................................................... lib/bootmem: Extend bootmem_allocate_buffer Extend bootmem_allocate_buffer to return either memory at bottom of DRAM or at top of DRAM. Also pass the alignment as optional argument. Protect the current executable, to prevent the loader from overwriting it. Introduce new weak functions to guard other in use memory regions. For example: TTB, CBFS cache, ATF region, ... To be used by FIT image loading. Tested on Cavium SoC. Change-Id: I0c983ce43616147c519a43edee3b61d54eadbb9a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/mirror_payload.c M src/include/bootmem.h M src/lib/bootmem.c M src/lib/prog_loaders.c M src/lib/selfboot.c 5 files changed, 72 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/25383/1 diff --git a/src/cpu/x86/mirror_payload.c b/src/cpu/x86/mirror_payload.c index 5f0493a..d921a26 100644 --- a/src/cpu/x86/mirror_payload.c +++ b/src/cpu/x86/mirror_payload.c @@ -46,7 +46,7 @@ printk(BIOS_DEBUG, "Payload aligned size: 0x%zx\n", size); - buffer = bootmem_allocate_buffer(size); + buffer = bootmem_allocate_buffer(size, 0, 0); if (buffer == NULL) { printk(BIOS_DEBUG, "No buffer for mirroring payload.\n"); diff --git a/src/include/bootmem.h b/src/include/bootmem.h index 10c8d51..4235317 100644 --- a/src/include/bootmem.h +++ b/src/include/bootmem.h @@ -41,7 +41,16 @@ /* Return 1 if region targets usable RAM, 0 otherwise. */ int bootmem_region_targets_usable_ram(uint64_t start, uint64_t size); +void bootmem_prepare_payload(void); +void bootmem_prepare_payload_arch(void); +void bootmem_prepare_payload_platform(void); + /* Allocate a temporary buffer from the unused RAM areas. */ -void *bootmem_allocate_buffer(size_t size); +void *bootmem_allocate_buffer(const size_t size, const size_t align, + const size_t prefer_low_addr); + +/* Helper to mark region as in use */ +#define BOOTMEM_RESERVED(x) bootmem_add_range((uintptr_t)_##x, _##x##_size, \ + LB_MEM_RESERVED); #endif /* BOOTMEM_H */ diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index ea02a16..6f4bb04 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -20,6 +20,7 @@ #include <cbmem.h> #include <device/resource.h> #include <stdlib.h> +#include <symbols.h> static struct memranges bootmem; @@ -126,7 +127,44 @@ return 0; } -void *bootmem_allocate_buffer(size_t size) +/** + * Overwrite on arch level to guard against overwriting in use memory regions. + * Possible regions: TTB + */ +void __attribute__((weak)) bootmem_prepare_payload_arch(void) +{ +} + +/** + * Overwrite on platform level to guard against overwriting in use memory + * regions. + * Possible regions: TIMESTAMPS + */ +void __attribute__((weak)) bootmem_prepare_payload_platform(void) +{ +} + +void bootmem_prepare_payload(void) +{ + /* Mark current program as reserved. */ + BOOTMEM_RESERVED(program) + BOOTMEM_RESERVED(stack) +} + +/** + * Allocate a slice of memory for payload related operations. + * The returned buffer doesn't overlap with anything in use and targets + * usable DRAM. + * @size: Size of buffer to allocate in bytes. + * @align: Alignment of buffer in bytes. Set to 0 if not used. + * @prefer_low_addr: Set to 1 to get a buffer from start of DRAM. + * + * Returns a buffer with given alignment in 32bit address space. + * + * Returns NULL on error. + */ +void *bootmem_allocate_buffer(const size_t size, const size_t align, + const size_t prefer_low_addr) { const struct range_entry *r; const struct range_entry *region; @@ -136,10 +174,10 @@ resource_t end; /* 4KiB alignment. */ - size = ALIGN(size, 4096); + const size_t real_size = ALIGN(size, MAX(4096, align)); region = NULL; memranges_each_entry(r, &bootmem) { - if (range_entry_size(r) < size) + if (range_entry_size(r) < real_size) continue; if (range_entry_tag(r) != LB_MEM_RAM) @@ -152,24 +190,32 @@ if (end > max_addr) end = max_addr; - if ((end - range_entry_base(r)) < size) + if ((end - range_entry_base(r)) < real_size) continue; region = r; + if (prefer_low_addr) + break; } if (region == NULL) return NULL; - /* region now points to the highest usable region for the given size. */ + /* + * region now points to either the lowest or to the highest usable + * region for the given size. + */ begin = range_entry_base(region); end = range_entry_end(region); - if (end > max_addr) - end = max_addr; - begin = end - size; + + if (!prefer_low_addr) { + if (end > max_addr) + end = max_addr; + begin = end - real_size; + } /* Mark buffer as unusuable for future buffer use. */ - bootmem_add_range(begin, size, LB_MEM_UNUSABLE); + bootmem_add_range(begin, real_size, LB_MEM_UNUSABLE); - return (void *)(uintptr_t)begin; + return (void *)((uintptr_t)ALIGN_UP(begin, align)); } diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 128869b..0aa415a 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -29,6 +29,7 @@ #include <stage_cache.h> #include <symbols.h> #include <timestamp.h> +#include <bootmem.h> /* Only can represent up to 1 byte less than size_t. */ const struct mem_region_device addrspace_32bit = @@ -178,6 +179,9 @@ goto out; mirror_payload(payload); + bootmem_prepare_payload(); + bootmem_prepare_payload_arch(); + bootmem_prepare_payload_platform(); /* Pass cbtables to payload if architecture desires it. */ prog_set_entry(payload, selfload(payload, true), diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 160e8f5..9b97f9d 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -101,7 +101,7 @@ */ lb_size = req_size + lb_size; - buffer = bootmem_allocate_buffer(lb_size); + buffer = bootmem_allocate_buffer(lb_size, 0, 0); printk(BIOS_SPEW, "Bounce Buffer at %p, %lu bytes\n", buffer, lb_size); -- To view, visit https://review.coreboot.org/25383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0c983ce43616147c519a43edee3b61d54eadbb9a Gerrit-Change-Number: 25383 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: soc/cavium: Implement L2C functions without the need of BDK
by build bot (Jenkins) (Code Review) 27 Mar '18

27 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25370 ) Change subject: soc/cavium: Implement L2C functions without the need of BDK ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69104/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23458/ : SUCCESS -- To view, visit https://review.coreboot.org/25370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I697de35522af55fa8f40f4502e8245d31d07ba5f Gerrit-Change-Number: 25370 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 13:34:32 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/cavium/cn8100_sff_evb: Add vboot support
by build bot (Jenkins) (Code Review) 27 Mar '18

27 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25109 ) Change subject: mb/cavium/cn8100_sff_evb: Add vboot support ...................................................................... Patch Set 3: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69103/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23457/ : SUCCESS -- To view, visit https://review.coreboot.org/25109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icb5395e56203fca4a03f2e9a47c21e772ad9ae79 Gerrit-Change-Number: 25109 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 13:34:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: src/drivers/pl011: Add verstage support
by build bot (Jenkins) (Code Review) 27 Mar '18

27 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25108 ) Change subject: src/drivers/pl011: Add verstage support ...................................................................... Patch Set 3: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69102/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23456/ : SUCCESS -- To view, visit https://review.coreboot.org/25108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1ddc372d558b380065ff944fccb0d84eb37d4213 Gerrit-Change-Number: 25108 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 13:33:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/cavium/bootblock: Get rid of register X1
by build bot (Jenkins) (Code Review) 27 Mar '18

27 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23792 ) Change subject: soc/cavium/bootblock: Get rid of register X1 ...................................................................... Patch Set 9: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69100/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23454/ : SUCCESS -- To view, visit https://review.coreboot.org/23792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9324ea9de24ba4baaef9dde890c443dd0f921ad9 Gerrit-Change-Number: 23792 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 13:33:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/cavium: Apply additional devicetree fixups
by Patrick Rudolph (Code Review) 27 Mar '18

27 Mar '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25382 Change subject: soc/cavium: Apply additional devicetree fixups ...................................................................... soc/cavium: Apply additional devicetree fixups Depends on Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d Apply additional devicetree fixes: * Update SCLK from boot fuses * Updated REFCLKUAA from UART ref clock divider settings Fixes Linux console wrong baud rate once the PL011 driver is started. Tested on Cavium SoC. Change-Id: I7e8eefd913915a879dad28dfb7801a2018ed2985 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/cavium/cn81xx/soc.c 1 file changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/25382/1 diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 83ee118..2e331f70 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -27,9 +27,40 @@ #include <stdlib.h> #include <string.h> #include <symbols.h> +#include <console/uart.h> +#include <fit.h> + /* FIXME(dhendrix): Need TZRAM_* definitions from ATF for Cavium */ //#include <arm-trusted-firmware/plat/rockchip/ck3399/include/shared/bl31_param.h> +/* Do additional devicetree modifications. */ +void fit_platform_fixup(struct DeviceTree *tree) +{ + DeviceTreeNode *dt_node; + + /* Set the sclk clock rate. */ + dt_node = dt_find_node_by_path(tree->root, "soc@0/sclk", NULL, NULL, 0); + if (dt_node) { + const u32 freq = thunderx_get_io_clock(); + printk(BIOS_INFO, "%s: Set SCLK to %u Hz\n", __func__, freq); + dt_add_u32_prop(dt_node, "clock-frequency", freq); + } else + printk(BIOS_ERR, "%s: Node not found. OS might miss-behave !\n", + __func__); + + /* Set refclkuaa clock rate. */ + dt_node = dt_find_node_by_path(tree->root, "soc@0/refclkuaa", NULL, + NULL, 0); + if (dt_node) { + const u32 freq = uart_platform_refclk(); + printk(BIOS_INFO, "%s: Set REFCLKUAA to %u Hz\n", __func__, + freq); + dt_add_u32_prop(dt_node, "clock-frequency", freq); + } else + printk(BIOS_ERR, "%s: Node not found. OS might miss-behave !\n", + __func__); +} + static void soc_read_resources(device_t dev) { ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size_mb() * KiB); -- To view, visit https://review.coreboot.org/25382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7e8eefd913915a879dad28dfb7801a2018ed2985 Gerrit-Change-Number: 25382 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: mb/google/poppy/variants/nami: Add SPD file for sona.
by build bot (Jenkins) (Code Review) 27 Mar '18

27 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25379 ) Change subject: mb/google/poppy/variants/nami: Add SPD file for sona. ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69097/ : SUCCESS -- To view, visit https://review.coreboot.org/25379 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I49fa114f07ad2eef10f18de9f6c3380173681bdd Gerrit-Change-Number: 25379 Gerrit-PatchSet: 2 Gerrit-Owner: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 10:25:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit March 2018