coreboot-gerrit March 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: intel/fsp: Update cannonlake fsp header
by build bot (Jenkins) (Code Review) 27 Mar '18

27 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25378 ) Change subject: intel/fsp: Update cannonlake fsp header ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69089/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23444/ : SUCCESS -- To view, visit https://review.coreboot.org/25378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie1c4df162e75535ad458709452a76de01e31907e Gerrit-Change-Number: 25378 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 01:55:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: intel/fsp: Update cannonlake fsp header
by build bot (Jenkins) (Code Review) 27 Mar '18

27 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25378 ) Change subject: intel/fsp: Update cannonlake fsp header ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69088/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/23443/ : SUCCESS -- To view, visit https://review.coreboot.org/25378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie1c4df162e75535ad458709452a76de01e31907e Gerrit-Change-Number: 25378 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 01:48:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: intel/fsp: Update cannonlake fsp header
by Lijian Zhao (Code Review) 27 Mar '18

27 Mar '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/25378 Change subject: intel/fsp: Update cannonlake fsp header ...................................................................... intel/fsp: Update cannonlake fsp header Fsp revison 7.x.2A.20 also updated MemInfoHob.h to fix SMBIOS Type 17 Offset 15h Speed report incorrectly issue. BUG=None TEST=Boot up with meowth platform and run dmidecode to see two dimm entries under Type 17. Change-Id: Ie1c4df162e75535ad458709452a76de01e31907e Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/25378/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h index 941a891..99dd815 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h @@ -202,6 +202,7 @@ UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. + UINT16 Speed; ///< The maximum capable speed of the device, in MHz. } DIMM_INFO; typedef struct { -- To view, visit https://review.coreboot.org/25378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie1c4df162e75535ad458709452a76de01e31907e Gerrit-Change-Number: 25378 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: arch/x86/smbios: Consider conner case of Part Number
by build bot (Jenkins) (Code Review) 27 Mar '18

27 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25377 ) Change subject: arch/x86/smbios: Consider conner case of Part Number ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69087/ : SUCCESS -- To view, visit https://review.coreboot.org/25377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id870c983584771dc1b60b1c99e95bbe7c0d25c4c Gerrit-Change-Number: 25377 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 01:44:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: arch/x86/smbios: Consider conner case of Part Number
by build bot (Jenkins) (Code Review) 27 Mar '18

27 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25377 ) Change subject: arch/x86/smbios: Consider conner case of Part Number ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69086/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/23442/ : SUCCESS -- To view, visit https://review.coreboot.org/25377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id870c983584771dc1b60b1c99e95bbe7c0d25c4c Gerrit-Change-Number: 25377 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 01:38:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: arch/x86/smbios: Consider conner case of Part Number
by Lijian Zhao (Code Review) 27 Mar '18

27 Mar '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/25377 Change subject: arch/x86/smbios: Consider conner case of Part Number ...................................................................... arch/x86/smbios: Consider conner case of Part Number In case of all DMI Type 17 could be all empty, the strip trailing whitespace code will have a zero length Part Number entry, which will cause exception when using (len - 1) where len is zero. Add extra code to cover this corner case. BUG=None TEST=Boot up fine with moowth platform, without this patch system will stuck at "Create SMBIOS type 17". Change-Id: Id870c983584771dc1b60b1c99e95bbe7c0d25c4c Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/arch/x86/smbios.c 1 file changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/25377/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 7079374..c14c231 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -232,10 +232,14 @@ len = strlen(trimmed_part_number); invalid = 0; /* assume valid */ - for (i = 0; i < len - 1; i++) { - if (trimmed_part_number[i] < ' ') { - invalid = 1; - trimmed_part_number[i] = '*'; + if (len == 0) + invalid = 1; + else { + for (i = 0; i < len - 1; i++) { + if (trimmed_part_number[i] < ' ') { + invalid = 1; + trimmed_part_number[i] = '*'; + } } } -- To view, visit https://review.coreboot.org/25377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id870c983584771dc1b60b1c99e95bbe7c0d25c4c Gerrit-Change-Number: 25377 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: mb/google/octopus: Enable i2c4 in devicetree
by build bot (Jenkins) (Code Review) 27 Mar '18

27 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25376 ) Change subject: mb/google/octopus: Enable i2c4 in devicetree ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69085/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23441/ : SUCCESS -- To view, visit https://review.coreboot.org/25376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5d837d62f00d34edf28fd472ae0dbe7c0d94447a Gerrit-Change-Number: 25376 Gerrit-PatchSet: 1 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Mar 2018 00:53:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Enable i2c4 in devicetree
by Shamile Khan (Code Review) 27 Mar '18

27 Mar '18

Shamile Khan has uploaded this change for review. ( https://review.coreboot.org/25376 Change subject: mb/google/octopus: Enable i2c4 in devicetree ...................................................................... mb/google/octopus: Enable i2c4 in devicetree BUG=None BRANCH=None Change-Id: I5d837d62f00d34edf28fd472ae0dbe7c0d94447a Signed-off-by: Shamile Khan <shamile.khan(a)intel.com> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/25376/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 97a1310..1aed797 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -149,7 +149,7 @@ device pci 16.1 on end # - I2C 1 device pci 16.2 on end # - I2C 2 device pci 16.3 on end # - I2C 3 - device pci 17.0 off end # - I2C 4 + device pci 17.0 on end # - I2C 4 device pci 17.1 on chip drivers/i2c/da7219 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" -- To view, visit https://review.coreboot.org/25376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5d837d62f00d34edf28fd472ae0dbe7c0d94447a Gerrit-Change-Number: 25376 Gerrit-PatchSet: 1 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com>

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Change in coreboot[master]: mb/google/octopus: Remove emmc tuning parameters from devicetree
by build bot (Jenkins) (Code Review) 27 Mar '18

27 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25375 ) Change subject: mb/google/octopus: Remove emmc tuning parameters from devicetree ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69084/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23440/ : SUCCESS -- To view, visit https://review.coreboot.org/25375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7ac44a54afd1ecfe355a9654ac8e92133b67637f Gerrit-Change-Number: 25375 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Mar 2018 23:58:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Remove emmc tuning parameters from devicetree
by Furquan Shaikh (Code Review) 27 Mar '18

27 Mar '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/25375 Change subject: mb/google/octopus: Remove emmc tuning parameters from devicetree ...................................................................... mb/google/octopus: Remove emmc tuning parameters from devicetree Current emmc tuning parameters for octopus were copied over from other boards and result in failure to boot from emmc. This change gets rid of the emmc tuning parameters in devicetree. Once emmc tuning tests are run for octopus, these parameters can be added back. BUG=b:75986903 BRANCH=None TEST=Verified that octopus boots from eMMC without any errors in depthcharge. Change-Id: I7ac44a54afd1ecfe355a9654ac8e92133b67637f Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb 1 file changed, 0 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/25375/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index a19d247..7aa7038 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -24,48 +24,6 @@ # GPIO for PERST_0 (WLAN_PE_RST) register "prt0_gpio" = "GPIO_164" - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-16.33. - # [14:8] steps of delay for HS400, each 125ps. - # [6:0] steps of delay for SDR104/HS200, each 125ps. - register "emmc_tx_data_cntl1" = "0x0C3A" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-16.34. - # [30:24] steps of delay for SDR50, each 125ps. - # [22:16] steps of delay for DDR50, each 125ps. - # [14:8] steps of delay for SDR25/HS50, each 125ps. - # [6:0] steps of delay for SDR12, each 125ps. - register "emmc_tx_data_cntl2" = "0x28272929" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-16.35. - # [30:24] steps of delay for SDR50, each 125ps. - # [22:16] steps of delay for DDR50, each 125ps. - # [14:8] steps of delay for SDR25/HS50, each 125ps. - # [6:0] steps of delay for SDR12, each 125ps. - register "emmc_rx_cmd_data_cntl1" = "0x003B263B" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-16.37. - # [17:16] stands for Rx Clock before Output Buffer - # [14:8] steps of delay for Auto Tuning Mode, each 125ps. - # [6:0] steps of delay for HS200, each 125ps. - register "emmc_rx_cmd_data_cntl2" = "0x10008" - - # EMMC RX STROBE Delay - # Refer to EDS-Vol2-16.36. - # [16] Enable Auto Tuning for HS400 Strobe Path - # [14:8] steps of delay for HS400 Mode 1, each 125ps. - # [6:0] steps of delay for HS400 Mode 2, each 125ps. - register "emmc_rx_strobe_cntl" = "0x0a0a" - - # EMMC TX COMMAND Delay - # Refer to EDS-Vol2-16.32. - # [14:8] steps of delay for DDR Mode, each 125ps. - # [6:0] steps of delay for SDR Mode, each 125ps. - register "emmc_tx_cmd_cntl" = "0x1305" - # GPE configuration # Note that GPE events called out in ASL code rely on this # route, i.e., if this route changes then the affected GPE -- To view, visit https://review.coreboot.org/25375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7ac44a54afd1ecfe355a9654ac8e92133b67637f Gerrit-Change-Number: 25375 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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coreboot-gerrit March 2018