Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29996
Change subject: soc/intel/cannonlake: Increase bootblock size
......................................................................
soc/intel/cannonlake: Increase bootblock size
Increase the bootblock size to 48K to match skylake. With UART
enabled we are very near the 32K limit, and with upcoming changes
to add USB devices in devicetree for a cannonlake board it is over
the current 32K limit.
Change-Id: I155cb0a6af1746af6833fa9f35c2ea6fe0bc709f
Signed-off-by: Duncan Laurie <dlaurie(a)google.com>
---
M src/soc/intel/cannonlake/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/29996/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 9452b6d..78c6dfe 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -230,7 +230,7 @@
config C_ENV_BOOTBLOCK_SIZE
hex
- default 0x8000
+ default 0xC000
config CBFS_SIZE
hex
--
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Gerrit-Change-Id: I155cb0a6af1746af6833fa9f35c2ea6fe0bc709f
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Marcello Sylvester Bauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29979 )
Change subject: arch/x86/Kconfig: move MAX_REBOOT_CNT option
......................................................................
Patch Set 2:
(1 comment)
> Patch Set 2:
>
> (1 comment)
>
> Currently, you can't set wrong values. That's a feature I'd like to
> have maintained.
i'll keep that in mind :)
> Everything below the currently defined defaults is
> wrong.
why are they wrong? I tested it with values below and it behaves like it should.
> In other words, this option was hidden on purpose. You can add another
> option for instance and take the minimum of both or something like
> that. But you mustn't lower it.
An other option would be to adapt the range in the Kconfig or fix the issue which cause this wrong behavior.
https://review.coreboot.org/#/c/29979/1//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/29979/1//COMMIT_MSG@11
PS1, Line 11:
> It's not about complete reboots. If you'd set it to 2 you […]
sounds like an unintended behavior if that is true.
but i don't understand why it shouldn't be optional.
The default value of 3 sounds good IMHO, but in some use cases, your may want to change it.
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Gerrit-Owner: Marcello Sylvester Bauer <sylvblck(a)sylv.io>
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29994 )
Change subject: mainboard/asus/am1i-a: add missing GPIO IO ports to devtree
......................................................................
Patch Set 2: Code-Review+2
I would optionally describe what issue this fixes, but other than that I believe this is good enough.
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Gerrit-Owner: Kevin Cody-Little <kcodyjr(a)gmail.com>
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29994 )
Change subject: Add additional IO ports for GPIO to devtree, for ASUS am1i-a port, fixes failure to boot (for me).
......................................................................
Patch Set 1: Code-Review-1
Good to know this fixes your issues, but:
- There is no signed-off line
- The commit summary is way too long
Please check other commits as a reference and please correct these issues.
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 )
Change subject: src: Remove unused variables
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Patch Set 14:
(1 comment)
https://review.coreboot.org/#/c/29917/14/src/cpu/amd/family_10h-family_15h/…
File src/cpu/amd/family_10h-family_15h/init_cpus.c:
https://review.coreboot.org/#/c/29917/14/src/cpu/amd/family_10h-family_15h/…
PS14, Line 1061: if ((get_option(&nvram, "cpu_c_states") == CB_SUCCESS) &&
line over 80 characters
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Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29993
Change subject: riscv: fix non-SMP support
......................................................................
riscv: fix non-SMP support
Change an incorrect zero default of RISCV_HART_NUM to 1.
This causes causes a call to address 0.
Add a die() call to fail gracefully.
Change-Id: I4e3aa09b787ae0f26a4aae375f4e5fcd745a0a1e
Signed-off-by: Philipp Hug <philipp(a)hug.cx>
---
M src/arch/riscv/Kconfig
M src/arch/riscv/smp.c
2 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/29993/1
diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
index ae83be8..2d2ef5d 100644
--- a/src/arch/riscv/Kconfig
+++ b/src/arch/riscv/Kconfig
@@ -35,6 +35,7 @@
config RISCV_HART_NUM
int
+ default 1
config RISCV_WORKING_HARTID
int
diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c
index 8d07d39..b3feb9e 100644
--- a/src/arch/riscv/smp.c
+++ b/src/arch/riscv/smp.c
@@ -81,5 +81,8 @@
if (i != hartid)
set_msip(i, 1);
+ if (HLS()->entry.fn == NULL)
+ die("entry fn not set\n");
+
HLS()->entry.fn(HLS()->entry.arg);
}
--
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