coreboot-gerrit December 2018

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Change in ...coreboot[master]: [WIP]drivers/smmstore: Allow using raw FMAP regions
by build bot (Jenkins) (Code Review) 01 Dec '18

01 Dec '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29991 ) Change subject: [WIP]drivers/smmstore: Allow using raw FMAP regions ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29991/2/src/drivers/smmstore/store.c File src/drivers/smmstore/store.c: https://review.coreboot.org/#/c/29991/2/src/drivers/smmstore/store.c@73 PS2, Line 73: if (fmap_locate_area_as_rdev_rw(CONFIG_SMMSTORE_REGION, rstore)) { line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c2b9b3a0ed16b2d37e6a97e33c671fb54df8de0 Gerrit-Change-Number: 29991 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Dec 2018 14:34:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP]drivers/smmstore: Allow using raw FMAP regions
by build bot (Jenkins) (Code Review) 01 Dec '18

01 Dec '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29991 ) Change subject: [WIP]drivers/smmstore: Allow using raw FMAP regions ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29991/1/src/drivers/smmstore/store.c File src/drivers/smmstore/store.c: https://review.coreboot.org/#/c/29991/1/src/drivers/smmstore/store.c@73 PS1, Line 73: if (fmap_locate_area_as_rdev_rw(CONFIG_SMMSTORE_REGION, rstore)) { line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c2b9b3a0ed16b2d37e6a97e33c671fb54df8de0 Gerrit-Change-Number: 29991 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Dec 2018 14:30:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP]drivers/smmstore: Allow using raw FMAP regions
by Arthur Heymans (Code Review) 01 Dec '18

01 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29991 Change subject: [WIP]drivers/smmstore: Allow using raw FMAP regions ...................................................................... [WIP]drivers/smmstore: Allow using raw FMAP regions Use a raw fmap region SMMSTORE for the SMMSTORE mechanism, while keeping the initial option to use a cbfsfile. I need a board with on which CONFIG_DEBUG_SMI is easy... Change-Id: I8c2b9b3a0ed16b2d37e6a97e33c671fb54df8de0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/smmstore/Kconfig M src/drivers/smmstore/store.c M src/southbridge/intel/common/Kconfig 3 files changed, 30 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/29991/1 diff --git a/src/drivers/smmstore/Kconfig b/src/drivers/smmstore/Kconfig index 4bb48f7..b4e9909 100644 --- a/src/drivers/smmstore/Kconfig +++ b/src/drivers/smmstore/Kconfig @@ -20,13 +20,21 @@ select SPI_FLASH_SMM if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP if SMMSTORE +config SMMSTORE_IN_CBFS + bool + default n + help + Select this if you want to the SMMSTORE region in a + cbfsfile in a cbfs FMAP region + config SMMSTORE_REGION - string "fmap region in which SMM store file is kept" + string "fmap region in which SMM store file is kept" if SMMSTORE_IN_CBFS default "RW_LEGACY" if CHROMEOS default "COREBOOT" + default "SMMSTORE" config SMMSTORE_FILENAME - string "SMM store file name" + string "SMM store file name" if SMMSTORE_IN_CBFS default "smm store" endif diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index 4463bad..409949a 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -15,6 +15,7 @@ #include <boot_device.h> #include <cbfs.h> +#include <fmap.h> #include <commonlib/region.h> #include <console/console.h> #include <smmstore.h> @@ -57,15 +58,25 @@ static int lookup_store(struct region_device *rstore) { struct cbfsf file; - if (cbfs_locate_file_in_region(&file, - CONFIG_SMMSTORE_REGION, CONFIG_SMMSTORE_FILENAME, NULL) < 0) { - printk(BIOS_WARNING, "smm store: " - "Unable to find SMM store file in region '%s'\n", - CONFIG_SMMSTORE_REGION); - return -1; - } + if (IS_ENABLED(CONFIG_SMMSTORE_IN_CBFS)) { + if (cbfs_locate_file_in_region(&file, + CONFIG_SMMSTORE_REGION, + CONFIG_SMMSTORE_FILENAME, NULL) < 0) { + printk(BIOS_WARNING, "smm store: " + "Unable to find SMM store file in region '%s'\n", + CONFIG_SMMSTORE_REGION); + return -1; + } - cbfs_file_data(rstore, &file); + cbfs_file_data(rstore, &file); + } else { + if (fmap_locate_area_as_rdev_rw(CONFIG_SMMSTORE_REGION, rstore)) { + printk(BIOS_WARNING, + "smm store: Unable to find SMM store FMAP region '%s'\n", + CONFIG_SMMSTORE_REGION); + return -1; + } + } return 0; } diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 957faa5..0f3121f 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -16,6 +16,7 @@ config SOUTHBRIDGE_INTEL_COMMON_SPI def_bool n select SPI_FLASH + select BOOT_DEVICE_SUPPORTS_WRITES config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN def_bool n -- To view, visit https://review.coreboot.org/c/coreboot/+/29991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c2b9b3a0ed16b2d37e6a97e33c671fb54df8de0 Gerrit-Change-Number: 29991 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/inteltool: Add support for Sunrise Point LP
by build bot (Jenkins) (Code Review) 01 Dec '18

01 Dec '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28623 ) Change subject: util/inteltool: Add support for Sunrise Point LP ...................................................................... Patch Set 13: (2 comments) https://review.coreboot.org/#/c/28623/13/util/inteltool/gpio_groups.c File util/inteltool/gpio_groups.c: https://review.coreboot.org/#/c/28623/13/util/inteltool/gpio_groups.c@55 PS13, Line 55: "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", line over 80 characters https://review.coreboot.org/#/c/28623/13/util/inteltool/gpio_groups.c@89 PS13, Line 89: "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/28623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16237ffc9a225b46271f2a51d77a7f28dfc36138 Gerrit-Change-Number: 28623 Gerrit-PatchSet: 13 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 01 Dec 2018 14:05:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/lynxpoint: Ensure the finalise handler is called
by Nico Huber (Code Review) 01 Dec '18

01 Dec '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29976 ) Change subject: sb/intel/lynxpoint: Ensure the finalise handler is called ...................................................................... Patch Set 1: (1 comment) Patrick G., not sure if anybody @google still cares, but it seems like Lynx Point was missing the finalize trigger on the resume path all the time. https://review.coreboot.org/#/c/29976/1/src/southbridge/intel/lynxpoint/lpc… File src/southbridge/intel/lynxpoint/lpc.c: https://review.coreboot.org/#/c/29976/1/src/southbridge/intel/lynxpoint/lpc… PS1, Line 972: IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) Should be selected by lynxpoint/Kconfig (instead of every single board. And no need to check here, then. -- To view, visit https://review.coreboot.org/c/coreboot/+/29976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9766a8dcbcb38420e937c810d252fef071851e92 Gerrit-Change-Number: 29976 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sat, 01 Dec 2018 13:48:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/lynxpoint: Make the finalise handler common
by Nico Huber (Code Review) 01 Dec '18

01 Dec '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29975 ) Change subject: sb/intel/lynxpoint: Make the finalise handler common ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/29975/1/src/southbridge/intel/lynxpoint/smi… File src/southbridge/intel/lynxpoint/smihandler.c: https://review.coreboot.org/#/c/29975/1/src/southbridge/intel/lynxpoint/smi… PS1, Line 275: mainboard It's rather `chipset_finalized`. -- To view, visit https://review.coreboot.org/c/coreboot/+/29975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13b581a2219288019a4e0c9e618db3ac7c3c15ab Gerrit-Change-Number: 29975 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Dec 2018 13:39:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/common: Create a common PCH finalise implementation
by Nico Huber (Code Review) 01 Dec '18

01 Dec '18

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Change in ...coreboot[master]: sb/intel/common: Create a common PCH finalise implementation
by Nico Huber (Code Review) 01 Dec '18

01 Dec '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29977 ) Change subject: sb/intel/common: Create a common PCH finalise implementation ...................................................................... Patch Set 2: (4 comments) https://review.coreboot.org/#/c/29977/2/src/southbridge/intel/common/finali… File src/southbridge/intel/common/finalize.c: https://review.coreboot.org/#/c/29977/2/src/southbridge/intel/common/finali… PS2, Line 75: outb(POST_OS_BOOT, 0x80); The name is just misleading. You might want to change that instead (in another patch). It was particularly introduced for this purpose, so it should stay. https://review.coreboot.org/#/c/29977/2/src/southbridge/intel/common/finali… PS2, Line 61: pci_update_config32(lpc_dev, D31F0_ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK); > Public docs don't mention ETR3 for any platform before Sunrise Point, […] It was just called differently: PMIR (same location). https://review.coreboot.org/#/c/29977/2/src/southbridge/intel/common/finali… PS2, Line 62: : /* PMSYNC */ : RCBA32_OR(0x33c4, (1UL << 31)); > Public docs don't mention PMSYNC, as far as I can tell. So I'm not sure […] It's HSW only. So `if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT))`? https://review.coreboot.org/#/c/29977/2/src/southbridge/intel/common/pmutil… File src/southbridge/intel/common/pmutil.h: https://review.coreboot.org/#/c/29977/2/src/southbridge/intel/common/pmutil… PS2, Line 25: D F -- To view, visit https://review.coreboot.org/c/coreboot/+/29977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2 Gerrit-Change-Number: 29977 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Dec 2018 13:32:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Program HD Audio SVID/SSID
by Nico Huber (Code Review) 01 Dec '18

01 Dec '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29651 ) Change subject: soc/intel/cannonlake: Program HD Audio SVID/SSID ...................................................................... Patch Set 5: (1 comment) >> Is this just setting subsystem ids of a PCI device? These should be >> set in the devicetree and no blob needed. >> >> If yes, this seems backwards. Shouldn't we set the id of the PCI >> device first and when configuring the codec take the id of the PCI >> device? > > From https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/sou…, > line 651, we can see kernel driver is comparing the ssid with pci > and verb. > > ass = codec->core.subsystem_id & 0xffff; > if (codec->bus->pci && > ass != codec->bus->pci->subsystem_device && (ass & 1)) > goto do_sku; No need to quote the code, I already believed the commit message. > > I believe the ssid of detail codec is fixed It's been some years since I worked with audio codecs, IIRC, this was writeable. Datasheet? https://review.coreboot.org/#/c/29651/5/src/soc/intel/cannonlake/fsp_params… File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/#/c/29651/5/src/soc/intel/cannonlake/fsp_params… PS5, Line 132: params->SiSsidTablePtr = (uintptr_t)ssidtblptr; If we are passing this to FSP, the struct has to be defined as part of FSP's UPD headers, not by coreboot. -- To view, visit https://review.coreboot.org/c/coreboot/+/29651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Gerrit-Change-Number: 29651 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sat, 01 Dec 2018 12:01:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/{bd82x6x, i82801gx, ibexpeak, lynxpoint}: Use BIOS_CNTL macro
by HAOUAS Elyes (Code Review) 01 Dec '18

01 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29990 Change subject: sb/{bd82x6x,i82801gx,ibexpeak,lynxpoint}: Use BIOS_CNTL macro ...................................................................... sb/{bd82x6x,i82801gx,ibexpeak,lynxpoint}: Use BIOS_CNTL macro Use BIOS_CNTL defined macro instead of magic number. Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 4 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/29990/1 diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7ae538e..16969e9 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -436,9 +436,9 @@ u8 reg8; printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void pch_fixups(struct device *dev) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 7dcec50..c44697d 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -358,15 +358,15 @@ #if TEST_SMM_FLASH_LOCKDOWN /* Now try this: */ printk(BIOS_DEBUG, "Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); printk(BIOS_DEBUG, "ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); @@ -374,9 +374,9 @@ *(volatile u8 *)0xfff00000 = 0x00; printk(BIOS_DEBUG, "Testing:\n"); reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); printk(BIOS_DEBUG, "Done.\n"); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index e5cbc59..d0361f6 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -449,9 +449,9 @@ u8 reg8; printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void pch_fixups(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index ca850c0..75d64b7 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -510,9 +510,9 @@ u8 reg8; printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void pch_fixups(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/29990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6 Gerrit-Change-Number: 29990 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit December 2018