coreboot-gerrit December 2018

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Change in ...coreboot[master]: soc/intel/apollolake: Add support to print ME version
by Furquan Shaikh (Code Review) 01 Dec '18

01 Dec '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29989 Change subject: soc/intel/apollolake: Add support to print ME version ...................................................................... soc/intel/apollolake: Add support to print ME version This change adds support to print ME version if UART_DEBUG is enabled. Check for UART_DEBUG is necessary because talking to ME to get the firmware version adds ~0.6 seconds to boot time. TEST=Verified on octopus that ME version printed is correct. Change-Id: I41217371558da1af694a2705e005429155d62838 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/apollolake/cse.c 1 file changed, 73 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/29989/1 diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index cfb3b8a..26249bc 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -42,6 +42,9 @@ #define READ_FILE_FLAG_EMULATED (1 << 2) #define READ_FILE_FLAG_HW (1 << 3) +#define MKHI_GROUP_ID_GEN 0xff +#define GET_FW_VERSION 0x02 + #define MCA_MAX_FILE_PATH_SIZE 64 #define FUSE_LOCK_FILE "/fpf/intel/SocCfgLock" @@ -55,6 +58,17 @@ #define FPF_STATUS_FMAP "FPF_STATUS" +union mkhi_header { + uint32_t data; + struct { + uint32_t group_id: 8; + uint32_t command: 7; + uint32_t is_response: 1; + uint32_t reserved: 8; + uint32_t result: 8; + } __packed fields; +}; + /* * Read file from CSE internal filesystem. * size is maximum length of provided buffer buff, which is updated with actual @@ -67,17 +81,6 @@ int res; size_t reply_size; - union mkhi_header { - uint32_t data; - struct { - uint32_t group_id: 8; - uint32_t command: 7; - uint32_t is_response: 1; - uint32_t reserved: 8; - uint32_t result: 8; - } __packed fields; - }; - struct mca_command { union mkhi_header mkhi_hdr; char file_name[MCA_MAX_FILE_PATH_SIZE]; @@ -192,6 +195,63 @@ return reg; } +static void dump_cse_version(void) +{ + int res; + size_t reply_size; + + struct fw_version_cmd { + union mkhi_header mkhi_hdr; + } __packed msg; + + struct version { + uint16_t minor; + uint16_t major; + uint16_t build; + uint16_t hotfix; + } __packed; + + struct fw_version_response { + union mkhi_header mkhi_hdr; + struct version code; + struct version nftp; + struct version fitc; + } __packed rsp; + + /* + * Print ME version only if UART debugging is enabled. Else, it takes + * ~0.6 second to talk to ME and get this information. + */ + if (!IS_ENABLED(CONFIG_UART_DEBUG)) + return; + + msg.mkhi_hdr.fields.group_id = MKHI_GROUP_ID_GEN; + msg.mkhi_hdr.fields.command = GET_FW_VERSION; + + res = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); + + if (!res) { + printk(BIOS_ERR, "Failed to send HECI message.\n"); + return; + } + + reply_size = sizeof(rsp); + res = heci_receive(&rsp, &reply_size); + + if (!res) { + printk(BIOS_ERR, "Failed to receive HECI reply.\n"); + return; + } + + if (rsp.mkhi_hdr.fields.result != 0) { + printk(BIOS_ERR, "Failed to get ME version.\n"); + return; + } + + printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", rsp.code.major, + rsp.code.minor, rsp.code.hotfix, rsp.code.build); +} + static void dump_cse_state(void) { uint32_t fwsts1; @@ -222,6 +282,8 @@ printk(BIOS_DEBUG, "unknown"); } printk(BIOS_DEBUG, "\n"); + + dump_cse_version(); } #define PCR_PSFX_T0_SHDW_PCIEN 0x1C -- To view, visit https://review.coreboot.org/c/coreboot/+/29989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41217371558da1af694a2705e005429155d62838 Gerrit-Change-Number: 29989 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Enable melf touchscreen
by Duncan Laurie (Code Review) 01 Dec '18

01 Dec '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29830 ) Change subject: mb/google/sarien/variants/sarien: Enable melf touchscreen ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29830/2/src/mainboard/google/sarien/variant… File src/mainboard/google/sarien/variants/sarien/devicetree.cb: https://review.coreboot.org/#/c/29830/2/src/mainboard/google/sarien/variant… PS2, Line 124: GPP_B13 > According schematic, the reset_gpio is connected with PLTRST. […] This pin is going to get pulsed by the kernel when sequencing power to the touchscreen, and we don't want it pulsing PLTRST and taking the whole system down. This may need to just have the power GPIO and not the reset GPIO. -- To view, visit https://review.coreboot.org/c/coreboot/+/29830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926c988c141628ae2d98206f9eb615d06357a366 Gerrit-Change-Number: 29830 Gerrit-PatchSet: 2 Gerrit-Owner: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sat, 01 Dec 2018 01:48:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Comment-In-Reply-To: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: MAINTAINERS: Add Philipp Hug as reviewer for RISC-V
by Philipp Deppenwiese (Code Review) 01 Dec '18

01 Dec '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29980 ) Change subject: MAINTAINERS: Add Philipp Hug as reviewer for RISC-V ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f2d3a61f66343a6e0350909edfe466d2ee6c089 Gerrit-Change-Number: 29980 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Sat, 01 Dec 2018 01:38:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Program HD Audio SVID/SSID
by Nico Huber (Code Review) 01 Dec '18

01 Dec '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29651 ) Change subject: soc/intel/cannonlake: Program HD Audio SVID/SSID ...................................................................... Patch Set 5: >> Is this just setting subsystem ids of a PCI device? These should be >> set in the devicetree and no blob needed. >> > > FWIW the reason we set subsystem IDs in Kconfig and not devicetree > is so we (google) can easily override them when building firmware > images for unreleased devices. That's a valid case. But why jump through hoops here instead of updating the whole of coreboot to be more flexible about subsystem IDs? -- To view, visit https://review.coreboot.org/c/coreboot/+/29651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Gerrit-Change-Number: 29651 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sat, 01 Dec 2018 00:30:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Program HD Audio SVID/SSID
by Lijian Zhao (Code Review) 01 Dec '18

01 Dec '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29651 ) Change subject: soc/intel/cannonlake: Program HD Audio SVID/SSID ...................................................................... Patch Set 5: > > Is this just setting subsystem ids of a PCI device? These should > be > > set in the devicetree and no blob needed. > > > > If yes, this seems backwards. Shouldn't we set the id of the PCI > > device first and when configuring the codec take the id of the > PCI > > device? > > From https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/sou…, > line 651, we can see kernel driver is comparing the ssid with pci > and verb. > > ass = codec->core.subsystem_id & 0xffff; > if (codec->bus->pci && > ass != codec->bus->pci->subsystem_device && (ass & 1)) > goto do_sku; > > I believe the ssid of detail codec is fixed, then we have to modify > BUS ssid to match with it. I have similar concern earlier in 29490. Sorry I have make same comment more than once, seems something wrong with my browser. -- To view, visit https://review.coreboot.org/c/coreboot/+/29651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Gerrit-Change-Number: 29651 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sat, 01 Dec 2018 00:21:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Program HD Audio SVID/SSID
by Lijian Zhao (Code Review) 01 Dec '18

01 Dec '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29651 ) Change subject: soc/intel/cannonlake: Program HD Audio SVID/SSID ...................................................................... Patch Set 5: > Is this just setting subsystem ids of a PCI device? These should be > set in the devicetree and no blob needed. > > If yes, this seems backwards. Shouldn't we set the id of the PCI > device first and when configuring the codec take the id of the PCI > device? From https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/sound…, I can see the codec driver is comparing ssid in codec and pci bus ssid. Since the codec SSID is fixed with sku, then I believe we can only change pci ssid to match with that. Why we need to go through FSP but not in device tree had been discussed in 29490. -- To view, visit https://review.coreboot.org/c/coreboot/+/29651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Gerrit-Change-Number: 29651 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sat, 01 Dec 2018 00:20:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/poppy/variant/nocturne: increase touch panel power-on delay
by Furquan Shaikh (Code Review) 01 Dec '18

01 Dec '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29988 ) Change subject: mb/google/poppy/variant/nocturne: increase touch panel power-on delay ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1db0b3f5ce666b79d8ada2939ec865233ce52a56 Gerrit-Change-Number: 29988 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Dec 2018 00:19:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/poppy/variant/nocturne: increase touch panel power-on delay
by Duncan Laurie (Code Review) 01 Dec '18

01 Dec '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29988 ) Change subject: mb/google/poppy/variant/nocturne: increase touch panel power-on delay ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1db0b3f5ce666b79d8ada2939ec865233ce52a56 Gerrit-Change-Number: 29988 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Sat, 01 Dec 2018 00:14:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/poppy/variant/nocturne: increase touch panel power-on delay
by Nick Vaccaro (Code Review) 01 Dec '18

01 Dec '18

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29988 Change subject: mb/google/poppy/variant/nocturne: increase touch panel power-on delay ...................................................................... mb/google/poppy/variant/nocturne: increase touch panel power-on delay The WACOM 5C01 touch panel power-up delay of 10mS is too aggressive and causes "failed to change power setting" errors in the kernel, so this change increases the power-up delay to 20mS which allows enough time for the WACOM device's i2c controller to wake up. BUG=b:120090384 BRANCH=none TEST=flash and boot nocturne, log into kernel, execute the following command and make sure the string is not found : dmesg | grep "failed to change power setting" Change-Id: I1db0b3f5ce666b79d8ada2939ec865233ce52a56 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/29988/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 1786502..031c7ff 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -320,7 +320,7 @@ register "generic.speed" = "I2C_SPEED_FAST_PLUS" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)" - register "generic.reset_delay_ms" = "10" + register "generic.reset_delay_ms" = "20" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/29988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1db0b3f5ce666b79d8ada2939ec865233ce52a56 Gerrit-Change-Number: 29988 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Program HD Audio SVID/SSID
by Duncan Laurie (Code Review) 01 Dec '18

01 Dec '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29651 ) Change subject: soc/intel/cannonlake: Program HD Audio SVID/SSID ...................................................................... Patch Set 5: > Patch Set 3: > > Is this just setting subsystem ids of a PCI device? These should be > set in the devicetree and no blob needed. > FWIW the reason we set subsystem IDs in Kconfig and not devicetree is so we (google) can easily override them when building firmware images for unreleased devices. -- To view, visit https://review.coreboot.org/c/coreboot/+/29651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Gerrit-Change-Number: 29651 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sat, 01 Dec 2018 00:11:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2018