coreboot-gerrit December 2018

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: src: Remove unused variables
by Angel Pons (Code Review) 02 Dec '18

02 Dec '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove unused variables ...................................................................... Patch Set 14: (2 comments) https://review.coreboot.org/#/c/29917/14//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29917/14//COMMIT_MSG@7 PS14, Line 7: src: Remove unused variables > why did you fix it ? […] AFAIK, that is the idea. It should also improve code quality. "Should". https://review.coreboot.org/#/c/29917/14/src/southbridge/intel/fsp_rangeley… File src/southbridge/intel/fsp_rangeley/romstage.c: https://review.coreboot.org/#/c/29917/14/src/southbridge/intel/fsp_rangeley… PS14, Line 123: printk(BIOS_DEBUG, "cbmem was initted\n"); > good solution, but I only care about the error case. […] Is the cbmem_was_initted variable needed though? cbmem_recovery could be called from within the if(): if(cbmem_recovery(0)) printk(BIOS_ERR, "whatever"); -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 14 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 02 Dec 2018 09:28:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/{bd82x6x, i82801gx, ibexpeak, lynxpoint}: Use BIOS_CNTL macro
by Patrick Rudolph (Code Review) 02 Dec '18

02 Dec '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29990 ) Change subject: sb/{bd82x6x,i82801gx,ibexpeak,lynxpoint}: Use BIOS_CNTL macro ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29990/1/src/southbridge/intel/i82801gx/lpc.c File src/southbridge/intel/i82801gx/lpc.c: https://review.coreboot.org/#/c/29990/1/src/southbridge/intel/i82801gx/lpc.… PS1, Line 358: #if TEST_SMM_FLASH_LOCKDOWN is this dead code ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6 Gerrit-Change-Number: 29990 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 02 Dec 2018 08:44:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove unused variables
by Patrick Rudolph (Code Review) 02 Dec '18

02 Dec '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove unused variables ...................................................................... Patch Set 14: (2 comments) https://review.coreboot.org/#/c/29917/14//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29917/14//COMMIT_MSG@7 PS14, Line 7: src: Remove unused variables why did you fix it ? Do you want to enable Wunused ? https://review.coreboot.org/#/c/29917/14/src/southbridge/intel/fsp_rangeley… File src/southbridge/intel/fsp_rangeley/romstage.c: https://review.coreboot.org/#/c/29917/14/src/southbridge/intel/fsp_rangeley… PS14, Line 123: printk(BIOS_DEBUG, "cbmem was initted\n"); good solution, but I only care about the error case. Same for other cbmem_recovery invocations. if (!cbmem_was_initted) printk(BIOS_ERR, ...) -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 14 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 02 Dec 2018 08:41:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/asus/am1i-a: add missing GPIO IO ports
by Angel Pons (Code Review) 02 Dec '18

02 Dec '18

Angel Pons has uploaded a new patch set (#4) to the change originally created by Kevin Cody-Little. ( https://review.coreboot.org/c/coreboot/+/29994 ) Change subject: mb/asus/am1i-a: add missing GPIO IO ports ...................................................................... mb/asus/am1i-a: add missing GPIO IO ports This makes the mainboard able to boot again. Change-Id: Id96fbfd5c815431dba2f030fca62a5ea16b97393 Signed-off-by: Kevin Cody-Little <kcodyjr(a)gmail.com> --- M src/mainboard/asus/am1i-a/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/29994/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id96fbfd5c815431dba2f030fca62a5ea16b97393 Gerrit-Change-Number: 29994 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Cody-Little <kcodyjr(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/octopus: Enable mode change as wake source from S3/S0ix
by Furquan Shaikh (Code Review) 02 Dec '18

02 Dec '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30001 Change subject: mb/google/octopus: Enable mode change as wake source from S3/S0ix ...................................................................... mb/google/octopus: Enable mode change as wake source from S3/S0ix This change enables mode change as a wake source from S3 and S0ix. Thus, any time the device switches between clamshell and tablet mode while it is suspended, it will be treated as a valid user event and hence wake source. BUG=b:120349473 BRANCH=octopus TEST=Verified that octopus wakes up on mode transitions. Change-Id: Ib224df434730f873ce5514303e5d043cbc85a9a4 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h 1 file changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/30001/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h index 3398875..d416673 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h @@ -43,10 +43,17 @@ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) -/* EC can wake from S3 with lid or power button or key press */ +/* + * EC can wake from S3/S0ix with: + * 1. Lid open + * 2. Power button + * 3. Key press + * 4. Mode change + */ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) #define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) -- To view, visit https://review.coreboot.org/c/coreboot/+/30001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib224df434730f873ce5514303e5d043cbc85a9a4 Gerrit-Change-Number: 30001 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: acpi_pld: Make it easier to define the ACPI USB device groups
by Duncan Laurie (Code Review) 02 Dec '18

02 Dec '18

Duncan Laurie has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/29998 ) Change subject: acpi_pld: Make it easier to define the ACPI USB device groups ...................................................................... acpi_pld: Make it easier to define the ACPI USB device groups The Linux kernel can use the ACPI _PLD group information to determine peer ports. Currently to define the group information the devicetree must provide a complete _PLD structure. This change pulls the group information into a separate structure that can be defined in devicetree. This makes it easier to set for USB devices in devicetree that do not need a full custom PLD. This was tested on a sarien board with the USB devices defined by verifying that the USB 2/3 ports are correctly identified with their peer in sysfs. Change-Id: Ifd4cadf0f6c901eb3832ad4e1395904f99c2f5a0 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/arch/x86/acpi_pld.c M src/arch/x86/include/arch/acpi_pld.h M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/usb_acpi.c 4 files changed, 33 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/29998/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd4cadf0f6c901eb3832ad4e1395904f99c2f5a0 Gerrit-Change-Number: 29998 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/sarien: Define USB devices for ACPI
by Duncan Laurie (Code Review) 02 Dec '18

02 Dec '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30000 Change subject: mb/google/sarien: Define USB devices for ACPI ...................................................................... mb/google/sarien: Define USB devices for ACPI Add the USB device information for the sarien/arcada variants. This includes the ACPI _PLD group definitions for the external ports that indicate which USB2 and USB3 ports share the same physical interface. Change-Id: I0b936127954ba09c61ccb871bfc62ee7d99da263 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/Kconfig M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 3 files changed, 181 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/30000/1 diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 9b4696b..c9e4c0b 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -6,6 +6,7 @@ select DRIVERS_I2C_HID select DRIVERS_SPI_ACPI select DRIVERS_PS2_KEYBOARD + select DRIVERS_USB_ACPI select EC_GOOGLE_WILCO select GENERIC_SPD_BIN select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 4bd2d90..f487979 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -33,21 +33,21 @@ register "dptf_enable" = "1" # Intel Common SoC Config - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C - register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Ext USB2 Port 3 - register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Ext USB2 Port 4 + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port + register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port + register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port register "usb2_ports[3]" = "USB2_PORT_EMPTY" register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # FPR in PB - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 2230 (BT) + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Ext USB3 Port 3 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Ext USB3 Port 4 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 3042 (WWAN) + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Left Type-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN register "usb3_ports[4]" = "USB3_PORT_EMPTY" register "usb3_ports[5]" = "USB3_PORT_EMPTY" @@ -109,7 +109,80 @@ device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""USH"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.7 on end + end + chip drivers/usb/acpi + register "desc" = ""Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.8 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.3 on end + end + end + end + end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) chip drivers/intel/wifi register "wake" = "PME_B0_EN_BIT" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 66f1711..4696d7f 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -33,22 +33,22 @@ register "dptf_enable" = "1" # Intel Common SoC Config - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C - register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Ext USB2 Port 1 Charge - register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Ext USB2 Port 2 - register "usb2_ports[3]" = "USB2_PORT_LONG(OC2)" # Ext USB2 Port 3 + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port + register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Right Type-A Port 1 + register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Left Type-A Port + register "usb2_ports[3]" = "USB2_PORT_LONG(OC2)" # Right Type-A Port 2 register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # FPR in PB - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 2230 (BT) + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Ext USB3 Port 1 Charge - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Ext USB3 Port 2 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Ext USB3 Port 3 - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 3042 (WWAN) + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Left Type-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Right Type-A Port 2 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config @@ -109,7 +109,92 @@ device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port 2"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""USH"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.7 on end + end + chip drivers/usb/acpi + register "desc" = ""Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.8 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port 1"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port 2"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.4 on end + end + end + end + end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) chip drivers/intel/wifi register "wake" = "PME_B0_EN_BIT" -- To view, visit https://review.coreboot.org/c/coreboot/+/30000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b936127954ba09c61ccb871bfc62ee7d99da263 Gerrit-Change-Number: 30000 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/eve: Define USB port peers
by Duncan Laurie (Code Review) 02 Dec '18

02 Dec '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29999 Change subject: mb/google/eve: Define USB port peers ...................................................................... mb/google/eve: Define USB port peers Add ACPI _PLD group definitions for the external ports that indicate which USB2 and USB3 ports share the same physical interface. Change-Id: I7f85720a878a3774d453a9adb82518722f7ba23d Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/eve/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/29999/1 diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index e0ef3b0..44449a5 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -260,6 +260,7 @@ chip drivers/usb/acpi register "desc" = ""USB2 Type-C Left"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" device usb 2.0 on end end chip drivers/usb/acpi @@ -275,6 +276,7 @@ chip drivers/usb/acpi register "desc" = ""USB2 Type-C Right"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" device usb 2.4 on end end chip drivers/usb/acpi @@ -285,11 +287,13 @@ chip drivers/usb/acpi register "desc" = ""USB3 Type-C Left"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" device usb 3.0 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Right"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" device usb 3.1 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/29999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f85720a878a3774d453a9adb82518722f7ba23d Gerrit-Change-Number: 29999 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Add USB device names
by Duncan Laurie (Code Review) 02 Dec '18

02 Dec '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29997 Change subject: soc/intel/cannonlake: Add USB device names ...................................................................... soc/intel/cannonlake: Add USB device names Add the ACPI device names for the USB ports to match what is in the DSDT so USB ports can be defined in the SSDT. Change-Id: Ibb323bbd324811fa3178b0cba3d7f0a315169486 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/cannonlake/chip.c 1 file changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/29997/1 diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 17b173a..4604d80 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -35,6 +35,43 @@ if (dev->path.type == DEVICE_PATH_DOMAIN) return "PCI0"; + if (dev->path.type == DEVICE_PATH_USB) { + switch (dev->path.usb.port_type) { + case 0: + /* Root Hub */ + return "RHUB"; + case 2: + /* USB2 ports */ + switch (dev->path.usb.port_id) { + case 0: return "HS01"; + case 1: return "HS02"; + case 2: return "HS03"; + case 3: return "HS04"; + case 4: return "HS05"; + case 5: return "HS06"; + case 6: return "HS07"; + case 7: return "HS08"; + case 8: return "HS09"; + case 9: return "HS10"; + case 10: return "HS11"; + case 11: return "HS12"; + } + break; + case 3: + /* USB3 ports */ + switch (dev->path.usb.port_id) { + case 0: return "SS01"; + case 1: return "SS02"; + case 2: return "SS03"; + case 3: return "SS04"; + case 4: return "SS05"; + case 5: return "SS06"; + } + break; + } + return NULL; + } + if (dev->path.type != DEVICE_PATH_PCI) return NULL; -- To view, visit https://review.coreboot.org/c/coreboot/+/29997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb323bbd324811fa3178b0cba3d7f0a315169486 Gerrit-Change-Number: 29997 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: acpi_pld: Make it easier to define the ACPI USB device groups
by Duncan Laurie (Code Review) 02 Dec '18

02 Dec '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29998 Change subject: acpi_pld: Make it easier to define the ACPI USB device groups ...................................................................... acpi_pld: Make it easier to define the ACPI USB device groups The Linux kernel can use the ACPI _PLD group information to determine peer ports. Currently to define the group information the devicetree must provide a complete _PLD structure. This change pulls the group information into a separate structure that can be defined in devicetree. This makes it easier to set for USB devices in devicetree that do not need a full custom PLD. This was tested on a sarien board with the USB devices defined by verifying that the USB 2/3 ports are correctly identified with their peer in sysfs. Change-Id: Ifd4cadf0f6c901eb3832ad4e1395904f99c2f5a0 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/arch/x86/acpi_pld.c M src/arch/x86/include/arch/acpi_pld.h M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/usb_acpi.c 4 files changed, 34 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/29998/1 diff --git a/src/arch/x86/acpi_pld.c b/src/arch/x86/acpi_pld.c index d399ea6..d20bdf2 100644 --- a/src/arch/x86/acpi_pld.c +++ b/src/arch/x86/acpi_pld.c @@ -18,7 +18,8 @@ #include <arch/acpi.h> #include <arch/acpi_pld.h> -int acpi_pld_fill_usb(struct acpi_pld *pld, enum acpi_upc_type type) +int acpi_pld_fill_usb(struct acpi_pld *pld, enum acpi_upc_type type, + struct acpi_pld_group *group) { if (!pld) return -1; @@ -33,6 +34,9 @@ pld->rotation = PLD_ROTATE_0; pld->visible = 1; + /* Fill the group information */ + memcpy(&pld->group, group, sizeof(*group)); + /* Set the shape based on port type */ switch (type) { case UPC_TYPE_A: @@ -114,16 +118,16 @@ /* [77:74] Shape */ buf[9] |= (pld->shape & 0xf) << 2; - /* [78] Group Orientation */ - buf[9] |= (pld->group_orientation & 0x1) << 6; + /* [78] Orientation */ + buf[9] |= (pld->orientation & 0x1) << 6; /* [86:79] Group Token (incorrectly defined as 1 bit in ACPI 6.2A) */ - buf[9] |= (pld->group_token & 0x1) << 7; - buf[10] |= (pld->group_token >> 0x1) & 0x7f; + buf[9] |= (pld->group.token & 0x1) << 7; + buf[10] |= (pld->group.token >> 0x1) & 0x7f; /* [94:87] Group Position */ - buf[10] |= (pld->group_position & 0x1) << 7; - buf[11] |= (pld->group_position >> 0x1) & 0x7f; + buf[10] |= (pld->group.position & 0x1) << 7; + buf[11] |= (pld->group.position >> 0x1) & 0x7f; /* [95] Bay */ buf[11] |= (pld->bay & 0x1) << 7; diff --git a/src/arch/x86/include/arch/acpi_pld.h b/src/arch/x86/include/arch/acpi_pld.h index ce279a0..1b4417d 100644 --- a/src/arch/x86/include/arch/acpi_pld.h +++ b/src/arch/x86/include/arch/acpi_pld.h @@ -75,6 +75,17 @@ PLD_ROTATE_315 }; +#define ACPI_PLD_GROUP(__token, __position) \ + { \ + .token = __token, \ + .position = __position, \ + } + +struct acpi_pld_group { + uint8_t token; + uint8_t position; +}; + struct acpi_pld { /* Color field can be explicitly ignored */ bool ignore_color; @@ -100,9 +111,8 @@ enum acpi_pld_rotate rotation; /* Port grouping */ - enum acpi_pld_orientation group_orientation; - uint8_t group_token; - uint8_t group_position; + enum acpi_pld_orientation orientation; + struct acpi_pld_group group; uint8_t draw_order; uint8_t cabinet_number; uint8_t card_cage_number; @@ -112,7 +122,8 @@ }; /* Fill out PLD structure with defaults based on USB port type */ -int acpi_pld_fill_usb(struct acpi_pld *pld, enum acpi_upc_type type); +int acpi_pld_fill_usb(struct acpi_pld *pld, enum acpi_upc_type type, + struct acpi_pld_group *group); /* Turn PLD structure into a 20 byte ACPI buffer */ int acpi_pld_to_buffer(const struct acpi_pld *pld, uint8_t *buf, int buf_len); diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index 6429f13..512893d 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -46,7 +46,13 @@ */ enum acpi_upc_type type; - /* Define a custom physical location for the port */ + /* Group peer ports */ + struct acpi_pld_group group; + + /* + * Define a custom physical location for the port. + * If enabled, this takes precedence over the 'group' field. + */ bool use_custom_pld; struct acpi_pld custom_pld; diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index f049e68..abc1718 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -57,7 +57,7 @@ } else { /* Fill PLD strucutre based on port type */ struct acpi_pld pld; - acpi_pld_fill_usb(&pld, config->type); + acpi_pld_fill_usb(&pld, config->type, &config->group); acpigen_write_pld(&pld); } -- To view, visit https://review.coreboot.org/c/coreboot/+/29998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd4cadf0f6c901eb3832ad4e1395904f99c2f5a0 Gerrit-Change-Number: 29998 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit December 2018