coreboot-gerrit December 2018

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Change in ...coreboot[master]: sb/intel/common/smihandler: Compile test CONFIG_ELOG_GSMI
by Arthur Heymans (Code Review) 03 Dec '18

03 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30013 Change subject: sb/intel/common/smihandler: Compile test CONFIG_ELOG_GSMI ...................................................................... sb/intel/common/smihandler: Compile test CONFIG_ELOG_GSMI Change-Id: I2491c14c4fd45c74dbf584a07d6d3bf5ede7f69c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/smihandler.c 1 file changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/30013/1 diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index bd3af3a..5a33dd5 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -244,7 +244,6 @@ return NULL; } -#if IS_ENABLED(CONFIG_ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -265,7 +264,6 @@ /* drivers/elog/gsmi.c */ *ret = gsmi_exec(sub_command, param); } -#endif static void southbridge_smi_store(void) { @@ -336,11 +334,10 @@ southbridge_finalize_all(); mainboard_finalized = 1; break; -#if IS_ENABLED(CONFIG_ELOG_GSMI) case ELOG_GSMI_APM_CNT: - southbridge_smi_gsmi(); + if (IS_ENABLED(CONFIG_ELOG_GSMI)) + southbridge_smi_gsmi(); break; -#endif case SMMSTORE_APM_CNT: if (IS_ENABLED(CONFIG_SMMSTORE)) southbridge_smi_store(); -- To view, visit https://review.coreboot.org/c/coreboot/+/30013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2491c14c4fd45c74dbf584a07d6d3bf5ede7f69c Gerrit-Change-Number: 30013 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP]sb/intel/common/smihandler: Hook up smmstore
by Arthur Heymans (Code Review) 03 Dec '18

03 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30012 Change subject: [WIP]sb/intel/common/smihandler: Hook up smmstore ...................................................................... [WIP]sb/intel/common/smihandler: Hook up smmstore TESTED on Asus P5QC Change-Id: I20b87f3dcb898656ad31478820dd5153e4053cb2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/lapic/Makefile.inc M src/southbridge/intel/common/smihandler.c 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/30012/1 diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 9454f8f..7637250 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -4,6 +4,7 @@ romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c +smm-$(CONFIG_UDELAY_LAPIC) += apic_timer.c bootblock-y += boot_cpu.c verstage-y += boot_cpu.c romstage-y += boot_cpu.c diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 0ad400c..bd3af3a 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -25,6 +25,7 @@ #include <halt.h> #include <pc80/mc146818rtc.h> #include <southbridge/intel/common/pmbase.h> +#include <smmstore.h> #include "pmutil.h" @@ -266,6 +267,26 @@ } #endif +static void southbridge_smi_store(void) +{ + u8 sub_command, ret; + em64t101_smm_state_save_area_t *io_smi = + smi_apmc_find_state_save(SMMSTORE_APM_CNT); + uint32_t reg_ebx; + + if (!io_smi) + return; + /* Command and return value in EAX */ + sub_command = (io_smi->rax >> 8) & 0xff; + + /* Parameter buffer in EBX */ + reg_ebx = io_smi->rbx; + + /* drivers/smmstore/smi.c */ + ret = smmstore_exec(sub_command, (void *)reg_ebx); + io_smi->rax = ret; +} + static int mainboard_finalized = 0; static void southbridge_smi_apmc(void) @@ -320,6 +341,10 @@ southbridge_smi_gsmi(); break; #endif + case SMMSTORE_APM_CNT: + if (IS_ENABLED(CONFIG_SMMSTORE)) + southbridge_smi_store(); + break; } mainboard_smi_apmc(reg8); -- To view, visit https://review.coreboot.org/c/coreboot/+/30012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20b87f3dcb898656ad31478820dd5153e4053cb2 Gerrit-Change-Number: 30012 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/i82801jx: Fix the x_pm2_cnt_blk addrl
by Arthur Heymans (Code Review) 03 Dec '18

03 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30011 Change subject: sb/intel/i82801jx: Fix the x_pm2_cnt_blk addrl ...................................................................... sb/intel/i82801jx: Fix the x_pm2_cnt_blk addrl Removes a warning in Linux about FACP. Change-Id: Ia12302a4dcd34eacdcc8ae16bd39e951e616c6ea Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801jx/lpc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/30011/1 diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index ba79e73..b9f2e4b 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -562,7 +562,7 @@ fadt->x_pm2_cnt_blk.bit_width = 8; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/30011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia12302a4dcd34eacdcc8ae16bd39e951e616c6ea Gerrit-Change-Number: 30011 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src: Remove unused variables
by Angel Pons (Code Review) 02 Dec '18

02 Dec '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove unused variables ...................................................................... Patch Set 15: (6 comments) I feel there are some variables that could be removed completely instead of putting assignments to make them seem used. https://review.coreboot.org/#/c/29917/15/src/cpu/amd/family_10h-family_15h/… File src/cpu/amd/family_10h-family_15h/init_cpus.c: https://review.coreboot.org/#/c/29917/15/src/cpu/amd/family_10h-family_15h/… PS15, Line 1062: !! not needed https://review.coreboot.org/#/c/29917/15/src/northbridge/intel/pineview/ear… File src/northbridge/intel/pineview/early_init.c: https://review.coreboot.org/#/c/29917/15/src/northbridge/intel/pineview/ear… PS15, Line 123: u32 reg32; is it me or is reg32 not needed at all? https://review.coreboot.org/#/c/29917/15/src/northbridge/intel/x4x/early_in… File src/northbridge/intel/x4x/early_init.c: https://review.coreboot.org/#/c/29917/15/src/northbridge/intel/x4x/early_in… PS15, Line 226: reg16 = RCBA16(0x1a8); : reg16 &= ~0x3; : RCBA16(0x1a8) = reg16; What do we need reg16 for? https://review.coreboot.org/#/c/29917/15/src/soc/intel/fsp_baytrail/romstag… File src/soc/intel/fsp_baytrail/romstage/romstage.c: https://review.coreboot.org/#/c/29917/15/src/soc/intel/fsp_baytrail/romstag… PS15, Line 253: cbmem_was_initted Do we need this variable? I would call cbmem_recovery inside here instead. https://review.coreboot.org/#/c/29917/15/src/soc/intel/fsp_broadwell_de/rom… File src/soc/intel/fsp_broadwell_de/romstage/romstage.c: https://review.coreboot.org/#/c/29917/15/src/soc/intel/fsp_broadwell_de/rom… PS15, Line 119: cbmem_was_initted Same https://review.coreboot.org/#/c/29917/15/src/southbridge/intel/fsp_rangeley… File src/southbridge/intel/fsp_rangeley/romstage.c: https://review.coreboot.org/#/c/29917/15/src/southbridge/intel/fsp_rangeley… PS15, Line 122: cbmem_was_initted Same -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 15 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 02 Dec 2018 21:51:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: include/device/smbus.h: Don't use device_t
by HAOUAS Elyes (Code Review) 02 Dec '18

02 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30010 Change subject: include/device/smbus.h: Don't use device_t ...................................................................... include/device/smbus.h: Don't use device_t Use of device_t is deprecated. Change-Id: I76088d9ebfa0bb1edcb73c29e0e8023d489bb5a9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/device/smbus.h 1 file changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/30010/1 diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h index 639e938..621300d 100644 --- a/src/include/device/smbus.h +++ b/src/include/device/smbus.h @@ -51,9 +51,13 @@ return i2c_dev_writeb_at(dev, addr, val); } -int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer); -int smbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buffer); - +#ifdef __SIMPLE_DEVICE__ +int smbus_block_read(pci_devfn_t dev, u8 cmd, u8 bytes, u8 *buffer); +int smbus_block_write(pci_devfn_t dev, u8 cmd, u8 bytes, const u8 *buffer); +#else +int smbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buffer); +int smbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buffer); +#endif #if IS_ENABLED(CONFIG_SMBUS_HAS_AUX_CHANNELS) void smbus_switch_to_channel(uint8_t channel_number); uint8_t smbus_get_current_channel(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/30010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76088d9ebfa0bb1edcb73c29e0e8023d489bb5a9 Gerrit-Change-Number: 30010 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: include/device/pci_ops.h: Don't use device_t
by HAOUAS Elyes (Code Review) 02 Dec '18

02 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30009 Change subject: include/device/pci_ops.h: Don't use device_t ...................................................................... include/device/pci_ops.h: Don't use device_t Use of device_t is deprecated. Change-Id: Idadb93a561ca8bf4382eba0eb404087ecf34cce7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/device/pci_ops.h 1 file changed, 60 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/30009/1 diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 5e60e8d..c79abdd 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -12,36 +12,29 @@ void pci_write_config8(struct device *dev, unsigned int where, u8 val); void pci_write_config16(struct device *dev, unsigned int where, u16 val); void pci_write_config32(struct device *dev, unsigned int where, u32 val); - -#endif - -/* - * Use device_t here as the functions are to be used with either - * __SIMPLE_DEVICE__ defined or undefined. - */ static __always_inline -void pci_or_config8(device_t dev, unsigned int where, u8 ormask) +void pci_or_config8(struct device *dev, unsigned int where, u8 ormask) { u8 value = pci_read_config8(dev, where); pci_write_config8(dev, where, value | ormask); } static __always_inline -void pci_or_config16(device_t dev, unsigned int where, u16 ormask) +void pci_or_config16(struct device *dev, unsigned int where, u16 ormask) { u16 value = pci_read_config16(dev, where); pci_write_config16(dev, where, value | ormask); } static __always_inline -void pci_or_config32(device_t dev, unsigned int where, u32 ormask) +void pci_or_config32(struct device *dev, unsigned int where, u32 ormask) { u32 value = pci_read_config32(dev, where); pci_write_config32(dev, where, value | ormask); } static __always_inline -void pci_update_config8(device_t dev, int reg, u8 mask, u8 or) +void pci_update_config8(struct device *dev, int reg, u8 mask, u8 or) { u8 reg8; @@ -52,7 +45,7 @@ } static __always_inline -void pci_update_config16(device_t dev, int reg, u16 mask, u16 or) +void pci_update_config16(struct device *dev, int reg, u16 mask, u16 or) { u16 reg16; @@ -63,7 +56,7 @@ } static __always_inline -void pci_update_config32(device_t dev, int reg, u32 mask, u32 or) +void pci_update_config32(struct device *dev, int reg, u32 mask, u32 or) { u32 reg32; @@ -72,7 +65,61 @@ reg32 |= or; pci_write_config32(dev, reg, reg32); } +#else +static __always_inline +void pci_or_config8(pci_devfn_t dev, unsigned int where, u8 ormask) +{ + u8 value = pci_read_config8(dev, where); + pci_write_config8(dev, where, value | ormask); +} +static __always_inline +void pci_or_config16(pci_devfn_t dev, unsigned int where, u16 ormask) +{ + u16 value = pci_read_config16(dev, where); + pci_write_config16(dev, where, value | ormask); +} + +static __always_inline +void pci_or_config32(pci_devfn_t dev, unsigned int where, u32 ormask) +{ + u32 value = pci_read_config32(dev, where); + pci_write_config32(dev, where, value | ormask); +} + +static __always_inline +void pci_update_config8(pci_devfn_t dev, int reg, u8 mask, u8 or) +{ + u8 reg8; + + reg8 = pci_read_config8(dev, reg); + reg8 &= mask; + reg8 |= or; + pci_write_config8(dev, reg, reg8); +} + +static __always_inline +void pci_update_config16(pci_devfn_t dev, int reg, u16 mask, u16 or) +{ + u16 reg16; + + reg16 = pci_read_config16(dev, reg); + reg16 &= mask; + reg16 |= or; + pci_write_config16(dev, reg, reg16); +} + +static __always_inline +void pci_update_config32(pci_devfn_t dev, int reg, u32 mask, u32 or) +{ + u32 reg32; + + reg32 = pci_read_config32(dev, reg); + reg32 &= mask; + reg32 |= or; + pci_write_config32(dev, reg, reg32); +} +#endif /* !__SIMPLE_DEVICE__ */ const struct pci_bus_operations *pci_bus_default_ops(struct device *dev); #endif /* PCI_OPS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idadb93a561ca8bf4382eba0eb404087ecf34cce7 Gerrit-Change-Number: 30009 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/block/pcr: Don't use device_t
by HAOUAS Elyes (Code Review) 02 Dec '18

02 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30008 Change subject: soc/intel/common/block/pcr: Don't use device_t ...................................................................... soc/intel/common/block/pcr: Don't use device_t Use of device_t is deprecated. Change-Id: I9d7f1bc22d960d93173760c1bfe4db2dd9277967 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/common/block/pcr/pcr.c 1 file changed, 18 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/30008/1 diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c index 58eb13a..57b2c2b 100644 --- a/src/soc/intel/common/block/pcr/pcr.c +++ b/src/soc/intel/common/block/pcr/pcr.c @@ -220,20 +220,35 @@ } #if !IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0) - -static int pcr_wait_for_completion(device_t dev) +#ifdef __SIMPLE_DEVICE__ +static int pcr_wait_for_completion(pci_devfn_t dev) { struct stopwatch sw; stopwatch_init_msecs_expire(&sw, PCR_SBI_CMD_TIMEOUT); do { if ((pci_read_config16(dev, P2SB_CR_SBI_STATUS) & - P2SB_CR_SBI_STATUS_BUSY) == 0) + P2SB_CR_SBI_STATUS_BUSY) == 0) return 0; } while (!stopwatch_expired(&sw)); return -1; } +#else +static int pcr_wait_for_completion(struct device *dev) +{ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, PCR_SBI_CMD_TIMEOUT); + do { + if ((pci_read_config16(dev, P2SB_CR_SBI_STATUS) & + P2SB_CR_SBI_STATUS_BUSY) == 0) + return 0; + } while (!stopwatch_expired(&sw)); + + return -1; +} +#endif /* __SIMPLE_DEVICE__ */ /* * API to perform sideband communication -- To view, visit https://review.coreboot.org/c/coreboot/+/30008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d7f1bc22d960d93173760c1bfe4db2dd9277967 Gerrit-Change-Number: 30008 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/amd/sr5650/cmn.h: Don't use device_t
by build bot (Jenkins) (Code Review) 02 Dec '18

02 Dec '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30007 ) Change subject: sb/amd/sr5650/cmn.h: Don't use device_t ...................................................................... Patch Set 1: (6 comments) https://review.coreboot.org/#/c/30007/1/src/southbridge/amd/sr5650/cmn.h File src/southbridge/amd/sr5650/cmn.h: https://review.coreboot.org/#/c/30007/1/src/southbridge/amd/sr5650/cmn.h@185 PS1, Line 185: if (reg != reg_old) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/30007/1/src/southbridge/amd/sr5650/cmn.h@217 PS1, Line 217: if (reg != reg_old) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/30007/1/src/southbridge/amd/sr5650/cmn.h@229 PS1, Line 229: if (reg != reg_old) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/30007/1/src/southbridge/amd/sr5650/cmn.h@241 PS1, Line 241: if (reg != reg_old) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/30007/1/src/southbridge/amd/sr5650/cmn.h@253 PS1, Line 253: if (reg != reg_old) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/30007/1/src/southbridge/amd/sr5650/cmn.h@265 PS1, Line 265: if (reg != reg_old) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/30007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddbec373bfb3f8dc208397727de32db3844a333a Gerrit-Change-Number: 30007 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 02 Dec 2018 20:41:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/amd/sr5650/cmn.h: Don't use device_t
by HAOUAS Elyes (Code Review) 02 Dec '18

02 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30007 Change subject: sb/amd/sr5650/cmn.h: Don't use device_t ...................................................................... sb/amd/sr5650/cmn.h: Don't use device_t Use of device_t is deprecated. Change-Id: Iddbec373bfb3f8dc208397727de32db3844a333a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/sr5650/cmn.h 1 file changed, 140 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/30007/1 diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h index 859e15d..f5047d9 100644 --- a/src/southbridge/amd/sr5650/cmn.h +++ b/src/southbridge/amd/sr5650/cmn.h @@ -34,30 +34,32 @@ #define AB_INDX 0xCD8 #define AB_DATA (AB_INDX+4) -static inline u32 nb_read_index(device_t dev, u32 index_reg, u32 index) +#ifdef __SIMPLE_DEVICE__ +static inline u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index) { pci_write_config32(dev, index_reg, index); return pci_read_config32(dev, index_reg + 0x4); } -static inline void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) +static inline void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, + u32 data) { pci_write_config32(dev, index_reg, index); pci_write_config32(dev, index_reg + 0x4, data); } -static inline u32 nbmisc_read_index(device_t nb_dev, u32 index) +static inline u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index) { return nb_read_index((nb_dev), NBMISC_INDEX, (index)); } -static inline void nbmisc_write_index(device_t nb_dev, u32 index, u32 data) +static inline void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) { nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); } -static inline void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, - u32 val) +static inline void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, + u32 mask, u32 val) { u32 reg_old, reg; reg = reg_old = nbmisc_read_index(nb_dev, reg_pos); @@ -68,28 +70,28 @@ } } -static inline u32 htiu_read_index(device_t nb_dev, u32 index) +static inline u32 htiu_read_index(pci_devfn_t nb_dev, u32 index) { return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); } -static inline void htiu_write_index(device_t nb_dev, u32 index, u32 data) +static inline void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data) { nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); } -static inline u32 nbmc_read_index(device_t nb_dev, u32 index) +static inline u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index) { return nb_read_index((nb_dev), NBMC_INDEX, (index)); } -static inline void nbmc_write_index(device_t nb_dev, u32 index, u32 data) +static inline void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) { nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); } -static inline void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, - u32 val) +static inline void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, + u32 mask, u32 val) { u32 reg_old, reg; reg = reg_old = htiu_read_index(nb_dev, reg_pos); @@ -100,8 +102,8 @@ } } -static inline void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, - u32 val) +static inline void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, + u32 mask, u32 val) { u32 reg_old, reg; reg = reg_old = pci_read_config32(nb_dev, reg_pos); @@ -112,8 +114,8 @@ } } -static inline void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, - u8 val) +static inline void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, + u8 mask, u8 val) { u8 reg_old, reg; reg = reg_old = pci_read_config8(nb_dev, reg_pos); @@ -124,8 +126,8 @@ } } -static inline void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, - u32 val) +static inline void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, + u32 mask, u32 val) { u32 reg_old, reg; reg = reg_old = nbmc_read_index(nb_dev, reg_pos); @@ -136,7 +138,8 @@ } } -static inline void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val) +static inline void set_pcie_enable_bits(pci_devfn_t dev, u32 reg_pos, u32 mask, + u32 val) { u32 reg_old, reg; reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos); @@ -147,6 +150,124 @@ } } +#else +static inline u32 nb_read_index(struct device *dev, u32 index_reg, u32 index) +{ + pci_write_config32(dev, index_reg, index); + return pci_read_config32(dev, index_reg + 0x4); +} + +static inline void nb_write_index(struct device *dev, u32 index_reg, u32 index, + u32 data) +{ + pci_write_config32(dev, index_reg, index); + pci_write_config32(dev, index_reg + 0x4, data); +} + +static inline u32 nbmisc_read_index(struct device *nb_dev, u32 index) +{ + return nb_read_index((nb_dev), NBMISC_INDEX, (index)); +} + +static inline void nbmisc_write_index(struct device *nb_dev, u32 index, + u32 data) +{ + nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); +} + +static inline void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos, + u32 mask, u32 val) +{ + u32 reg_old, reg; + reg = reg_old = nbmisc_read_index(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + nbmisc_write_index(nb_dev, reg_pos, reg); + } +} + +static inline u32 htiu_read_index(struct device *nb_dev, u32 index) +{ + return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); +} + +static inline void htiu_write_index(struct device *nb_dev, u32 index, u32 data) +{ + nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); +} + +static inline u32 nbmc_read_index(struct device *nb_dev, u32 index) +{ + return nb_read_index((nb_dev), NBMC_INDEX, (index)); +} + +static inline void nbmc_write_index(struct device *nb_dev, u32 index, u32 data) +{ + nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); +} + +static inline void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos, + u32 mask, u32 val) +{ + u32 reg_old, reg; + reg = reg_old = htiu_read_index(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + htiu_write_index(nb_dev, reg_pos, reg); + } +} + +static inline void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos, + u32 mask, u32 val) +{ + u32 reg_old, reg; + reg = reg_old = pci_read_config32(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + pci_write_config32(nb_dev, reg_pos, reg); + } +} + +static inline void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos, + u8 mask, u8 val) +{ + u8 reg_old, reg; + reg = reg_old = pci_read_config8(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + pci_write_config8(nb_dev, reg_pos, reg); + } +} + +static inline void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos, + u32 mask, u32 val) +{ + u32 reg_old, reg; + reg = reg_old = nbmc_read_index(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + nbmc_write_index(nb_dev, reg_pos, reg); + } +} + +static inline void set_pcie_enable_bits(struct device *dev, u32 reg_pos, + u32 mask, u32 val) +{ + u32 reg_old, reg; + reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + nb_write_index(dev, NBPCIE_INDEX, reg_pos, reg); + } +} +#endif /* __SIMPLE_DEVICE__ */ + void set_pcie_reset(void); void set_pcie_dereset(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/30007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddbec373bfb3f8dc208397727de32db3844a333a Gerrit-Change-Number: 30007 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/stoneyridge: Don't use device_t
by HAOUAS Elyes (Code Review) 02 Dec '18

02 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30006 Change subject: soc/amd/stoneyridge: Don't use device_t ...................................................................... soc/amd/stoneyridge: Don't use device_t Use of device_t is deprecated. Change-Id: I7ef5fc14672da70e90952f7e844f4e583ca31506 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/30006/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index cb9c4c6..96193f0 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -426,7 +426,11 @@ void configure_stoneyridge_i2c(void); void sb_clk_output_48Mhz(void); void sb_disable_4dw_burst(void); -void sb_enable(device_t dev); +#ifdef __SIMPLE_DEVICE__ +void sb_enable(pci_devfn_t dev); +#else +void sb_enable(struct device *dev); +#endif void southbridge_final(void *chip_info); void southbridge_init(void *chip_info); void sb_lpc_port80(void); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 6157e50..3516fed 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -703,10 +703,17 @@ sb_print_pmxc0_status(); } -void sb_enable(device_t dev) +#ifdef __SIMPLE_DEVICE__ +void sb_enable(pci_devfn_t dev) { printk(BIOS_DEBUG, "%s\n", __func__); } +#else +void sb_enable(struct device *dev) +{ + printk(BIOS_DEBUG, "%s\n", __func__); +} +#endif static void sb_init_acpi_ports(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/30006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ef5fc14672da70e90952f7e844f4e583ca31506 Gerrit-Change-Number: 30006 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit December 2018