coreboot-gerrit December 2018

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Change in ...coreboot[master]: soc/intel/denverton_ns: Don't use device_t
by David Guckian (Code Review) 03 Dec '18

03 Dec '18

David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30004 ) Change subject: soc/intel/denverton_ns: Don't use device_t ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic29891d78514db3b7eed48414a14e4ff579436c0 Gerrit-Change-Number: 30004 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Dec 2018 09:24:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/intel/icelake_rvp: Fill Icelake U and Y RVP devicetree parameters
by Aamir Bohra (Code Review) 03 Dec '18

03 Dec '18

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30015 Change subject: mb/intel/icelake_rvp: Fill Icelake U and Y RVP devicetree parameters ...................................................................... mb/intel/icelake_rvp: Fill Icelake U and Y RVP devicetree parameters This implementation configures below parameters: 1. Enable SaGv, isclk. 2. Set Pcie rootport enable, Clock source usage and clkreq. 3. Configure SATA and LPSS controllers parameters. 4. Enable CNVI controller, configure Wifi end device under PCIE RP1. 5. Add TPM device support under GSPI1. Change-Id: I585e82799eea0bad19ad2c94d6b4b3024f930ed4 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb M src/soc/intel/icelake/chip.h 3 files changed, 279 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/30015/1 diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index a971332..0d2ea76 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -4,28 +4,40 @@ device lapic 0 on end end + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + # FSP configuration - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1" + register "SdCardPowerEnableActiveHigh" = "1" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB3/2 Type A port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # USB2 WWAN - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # USB2 Bluetooth + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2 WWAN + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-C Port1 register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-C Port3 - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Type-C Port4 + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4 register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 - register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" # USB2 Type A port2 - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" # USB2 Type A port2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port1 + register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port2 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3 WLAN - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WLAN + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + + # Enable Pch iSCLK + register "pch_isclk" = "1" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" @@ -36,6 +48,8 @@ register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" + register "PrmrrSize" = "0x10000000" + register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" register "PcieRpEnable[2]" = "1" @@ -53,12 +67,22 @@ register "PcieRpEnable[14]" = "1" register "PcieRpEnable[15]" = "1" - register "PcieClkSrcUsage[0]" = "1" + register "PcieClkSrcUsage[0]" = "2" register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" - register "PcieClkSrcUsage[3]" = "13" + register "PcieClkSrcUsage[2]" = "0xC" + register "PcieClkSrcUsage[3]" = "0x70" register "PcieClkSrcUsage[4]" = "4" - register "PcieClkSrcUsage[5]" = "14" + register "PcieClkSrcUsage[5]" = "0xE" + register "PcieClkSrcUsage[6]" = "0x80" + register "PcieClkSrcUsage[7]" = "0x80" + register "PcieClkSrcUsage[8]" = "0x80" + register "PcieClkSrcUsage[9]" = "0x80" + register "PcieClkSrcUsage[10]" = "0x80" + register "PcieClkSrcUsage[11]" = "0x80" + register "PcieClkSrcUsage[12]" = "0x80" + register "PcieClkSrcUsage[13]" = "0x80" + register "PcieClkSrcUsage[14]" = "0x80" + register "PcieClkSrcUsage[15]" = "0x80" register "PcieClkSrcClkReq[0]" = "0" register "PcieClkSrcClkReq[1]" = "1" @@ -66,6 +90,69 @@ register "PcieClkSrcClkReq[3]" = "3" register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[6]" = "6" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcClkReq[9]" = "9" + register "PcieClkSrcClkReq[10]" = "10" + register "PcieClkSrcClkReq[11]" = "11" + register "PcieClkSrcClkReq[12]" = "12" + register "PcieClkSrcClkReq[13]" = "13" + register "PcieClkSrcClkReq[14]" = "14" + register "PcieClkSrcClkReq[15]" = "15" + + register "SataEnable" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "SataPortsDevSlp[0]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsDevSlp[2]" = "1" + register "SataPortsDevSlp[3]" = "1" + register "SataPortsDevSlp[4]" = "1" + register "SataPortsDevSlp[5]" = "1" + register "SataPortsDevSlp[6]" = "1" + register "SataPortsDevSlp[7]" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, + [PchSerialIoIndexGSPI2] = 1, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" @@ -74,29 +161,32 @@ register "sdcard_cd_gpio" = "GPP_G5" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| I2C3 | Audio | + #| GSPI1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | #+-------------------+---------------------------+ + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .i2c[3] = { - .speed = I2C_SPEED_STANDARD, - .rise_time_ns = 104, - .fall_time_ns = 52, + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, }, }" device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem + device pci 04.0 off end # SA Thermal device + device pci 12.0 off end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 device pci 14.0 on @@ -188,6 +278,7 @@ end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # PMC SRAM chip drivers/intel/wifi register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi wifi @@ -203,7 +294,7 @@ end end # I2C 0 device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 + device pci 15.2 on end # I2C #2 device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 @@ -211,12 +302,17 @@ device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA + device pci 17.0 on end # SATA device pci 19.0 on end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_PCI_EXP" + device pci 00.0 on end + end + end # PCI Express Port 1 x4 SLOT1 device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 @@ -232,12 +328,15 @@ device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + device spi 0 on end end - end # LPC Interface + end # GSPI #1 + device pci 1f.0 on end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel HDA diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index 787097e..62c7a82 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -4,28 +4,40 @@ device lapic 0 on end end + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + # FSP configuration - register "SaGv" = "3" + register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1" + register "SdCardPowerEnableActiveHigh" = "1" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB3/2 Type A port1 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB3/2 Type A port2 - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # Bluetooth + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB3/2 Type A port2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-C Port1 register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-C Port3 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" # UNUSED - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # UNUSED - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # USB2 Type A port1 - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" # USB2 Type A port2 + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # UNUSED + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # UNUSED + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port1 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port2 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3 WLAN - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WLAN + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + + # Enable Pch iSCLK + register "pch_isclk" = "1" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" @@ -35,8 +47,8 @@ register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" - register "PchHdaAudioLinkSsp0" = "1" - register "PchHdaAudioLinkSsp1" = "1" + + register "PrmrrSize" = "0x10000000" register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" @@ -52,13 +64,25 @@ register "PcieRpEnable[11]" = "1" register "PcieRpEnable[12]" = "1" register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[15]" = "1" - register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[0]" = "0x80" register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" - register "PcieClkSrcUsage[3]" = "14" - register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[5]" = "1" + register "PcieClkSrcUsage[2]" = "0xC" + register "PcieClkSrcUsage[3]" = "0x70" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcUsage[5]" = "2" + register "PcieClkSrcUsage[6]" = "0x80" + register "PcieClkSrcUsage[7]" = "0x80" + register "PcieClkSrcUsage[8]" = "0x80" + register "PcieClkSrcUsage[9]" = "0x80" + register "PcieClkSrcUsage[10]" = "0x80" + register "PcieClkSrcUsage[11]" = "0x80" + register "PcieClkSrcUsage[12]" = "0x80" + register "PcieClkSrcUsage[13]" = "0x80" + register "PcieClkSrcUsage[14]" = "0x80" + register "PcieClkSrcUsage[15]" = "0x80" register "PcieClkSrcClkReq[0]" = "0" register "PcieClkSrcClkReq[1]" = "1" @@ -66,6 +90,69 @@ register "PcieClkSrcClkReq[3]" = "3" register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[6]" = "6" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcClkReq[9]" = "9" + register "PcieClkSrcClkReq[10]" = "10" + register "PcieClkSrcClkReq[11]" = "11" + register "PcieClkSrcClkReq[12]" = "12" + register "PcieClkSrcClkReq[13]" = "13" + register "PcieClkSrcClkReq[14]" = "14" + register "PcieClkSrcClkReq[15]" = "15" + + register "SataEnable" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "SataPortsDevSlp[0]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsDevSlp[2]" = "1" + register "SataPortsDevSlp[3]" = "1" + register "SataPortsDevSlp[4]" = "1" + register "SataPortsDevSlp[5]" = "1" + register "SataPortsDevSlp[6]" = "1" + register "SataPortsDevSlp[7]" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, + [PchSerialIoIndexGSPI2] = 1, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" @@ -74,13 +161,32 @@ register "sdcard_cd_gpio" = "GPP_G5" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #+-------------------+---------------------------+ + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem + device pci 04.0 off end # SA Thermal device + device pci 12.0 off end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 device pci 14.0 on @@ -172,6 +278,7 @@ end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # PMC SRAM chip drivers/intel/wifi register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi wifi @@ -187,20 +294,25 @@ end end # I2C 0 device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 on end # I2C #3 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA + device pci 17.0 on end # SATA device pci 19.0 on end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_PCI_EXP" + device pci 00.0 on end + end + end # PCI Express Port 1 x4 SLOT1 device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 @@ -216,12 +328,15 @@ device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + device spi 0 on end end - end # LPC Interface + end # GSPI #1 + device pci 1f.0 on end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel HDA diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index c8653b2..3e2b78a 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -115,6 +115,7 @@ uint16_t usb3_wake_enable_bitmap; /* SATA related */ + uint8_t SataEnable; uint8_t SataMode; uint8_t SataSalpSupport; uint8_t SataPortsEnable[8]; -- To view, visit https://review.coreboot.org/c/coreboot/+/30015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585e82799eea0bad19ad2c94d6b4b3024f930ed4 Gerrit-Change-Number: 30015 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/spi/winbond: Fix TB bit
by Patrick Rudolph (Code Review) 03 Dec '18

03 Dec '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30014 Change subject: drivers/spi/winbond: Fix TB bit ...................................................................... drivers/spi/winbond: Fix TB bit The TB has to be inverted to actually protected the correct region. Tested on elgon using I67eb4ee8e0ad297a8d1984d55102146688c291fc. Change-Id: I715791b8ae5d1db1ef587321ae5c9daa10eb7dbc Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/spi/winbond.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/30014/1 diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 9eb3352..f8ea247 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -303,7 +303,7 @@ tb = !tb; } - out->offset = tb ? flash_size - protected_size : 0; + out->offset = tb ? 0 : flash_size - protected_size; out->size = protected_size; } @@ -519,9 +519,9 @@ wp_region = *region; if (region_offset(&wp_region) == 0) - tb = 0; - else tb = 1; + else + tb = 0; if (region_sz(&wp_region) > flash->size / 2) { cmp = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/30014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I715791b8ae5d1db1ef587321ae5c9daa10eb7dbc Gerrit-Change-Number: 30014 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86/Kconfig: move MAX_REBOOT_CNT option
by Marcello Sylvester Bauer (Code Review) 03 Dec '18

03 Dec '18

Marcello Sylvester Bauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29979 ) Change subject: arch/x86/Kconfig: move MAX_REBOOT_CNT option ...................................................................... Patch Set 2: > Patch Set 2: > > >> Everything below the currently defined defaults is wrong. > > > > why are they wrong? I tested it with values below and it behaves > > like it should. > > Tested on what board and tested how? With/without MRC cache might make > a difference for instance, plus there are about half a dozen of software > reset methods, which one was used? I only tested the behavior on qemu and especially on my own maschine. (boot, reboot, resume to disk, S3 resume) > > Take modern Intel systems for instance. It's possible to reset the > CPU only, causing an INIT, the cores reset the x86 register state, > BSP restarts at the reset vector. Let's call it Reset#1. This is not > enough to rerun coreboot, though. Hence you'll usually find a 0x6 -> > 0xcf9 reset (aka. system reset, still a warm reset) early in the > romstage: Reset#2. If no mrc.cache is present (bug or not) the raminit > will refuse to retrain on warm resets: 0xe -> 0xcf9 (full reset, goes > into S5 and back into S0 after a few seconds, hence a cold reset). > That'd be Reset#3. > > So if MAX_REBOOT_CNT is < 3 and you hit the path described above, it > will run into fallback for no reason. Now i understand dimension of the problem. Thanks for the detailed explanation :) > > While that's the only path that comes to mind atm, there may be more > like that. If you can prove that a board doesn't have any valid path > with 3 resets, you can set MAX_REBOOT_CNT lower, and I won't call it > wrong ;) > > > > >> In other words, this option was hidden on purpose. You can add another > >> option for instance and take the minimum of both or something like > >> that. But you mustn't lower it. > > > > An other option would be to adapt the range in the Kconfig or fix > > the issue which cause this wrong behavior. > > What wrong behaviour? I meant the reset sequel, which causes a fallback even if nothing failed, but now i understand that it isn't possible. I will update the entry to warn about any value below. -- To view, visit https://review.coreboot.org/c/coreboot/+/29979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice26e2ef349f1172b564edc14f1012c33546a93c Gerrit-Change-Number: 29979 Gerrit-PatchSet: 2 Gerrit-Owner: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 03 Dec 2018 08:34:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove unused variables
by HAOUAS Elyes (Code Review) 03 Dec '18

03 Dec '18

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove unused variables ...................................................................... Patch Set 15: Code-Review-1 (6 comments) https://review.coreboot.org/#/c/29917/15/src/cpu/amd/family_10h-family_15h/… File src/cpu/amd/family_10h-family_15h/init_cpus.c: https://review.coreboot.org/#/c/29917/15/src/cpu/amd/family_10h-family_15h/… PS15, Line 1062: !! > not needed are you sure? I'm fine with removing this, but it was used this way (and it is also used at line #1076). I believe, that the Author know that (!!x = x), so if he used !!nvram, maybe there is a reason. https://review.coreboot.org/#/c/29917/15/src/northbridge/intel/pineview/ear… File src/northbridge/intel/pineview/early_init.c: https://review.coreboot.org/#/c/29917/15/src/northbridge/intel/pineview/ear… PS15, Line 123: u32 reg32; > is it me or is reg32 not needed at all? I don't know if that register needs a read before a write ... in fact, I didn't find the datasheet :( https://review.coreboot.org/#/c/29917/15/src/northbridge/intel/x4x/early_in… File src/northbridge/intel/x4x/early_init.c: https://review.coreboot.org/#/c/29917/15/src/northbridge/intel/x4x/early_in… PS15, Line 243: is it needed to read reg16 over DIMBAR32 here ? https://review.coreboot.org/#/c/29917/15/src/soc/intel/fsp_baytrail/romstag… File src/soc/intel/fsp_baytrail/romstage/romstage.c: https://review.coreboot.org/#/c/29917/15/src/soc/intel/fsp_baytrail/romstag… PS15, Line 253: cbmem_was_initted > Do we need this variable? I would call cbmem_recovery inside here instead. You are right, but that will be some "crowded" Usually, we don't put an instruction inside the is "condition". https://review.coreboot.org/#/c/29917/15/src/soc/intel/fsp_broadwell_de/rom… File src/soc/intel/fsp_broadwell_de/romstage/romstage.c: https://review.coreboot.org/#/c/29917/15/src/soc/intel/fsp_broadwell_de/rom… PS15, Line 119: cbmem_was_initted > Same Oops, it shoild be '!cbmem_was_initted' https://review.coreboot.org/#/c/29917/15/src/southbridge/intel/fsp_rangeley… File src/southbridge/intel/fsp_rangeley/romstage.c: https://review.coreboot.org/#/c/29917/15/src/southbridge/intel/fsp_rangeley… PS15, Line 122: cbmem_was_initted > Same sould be "!cbmem_was_initted" -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 15 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Dec 2018 07:28:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/i82801jx: Fix the x_pm2_cnt_blk addrl
by Patrick Rudolph (Code Review) 02 Dec '18

02 Dec '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30011 ) Change subject: sb/intel/i82801jx: Fix the x_pm2_cnt_blk addrl ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia12302a4dcd34eacdcc8ae16bd39e951e616c6ea Gerrit-Change-Number: 30011 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Dec 2018 06:34:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: riscv: save FDT pointer from mscratch to HLS
by build bot (Jenkins) (Code Review) 02 Dec '18

02 Dec '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27545 ) Change subject: riscv: save FDT pointer from mscratch to HLS ...................................................................... Patch Set 23: (1 comment) https://review.coreboot.org/#/c/27545/23/src/arch/riscv/include/arch/stages… File src/arch/riscv/include/arch/stages.h: https://review.coreboot.org/#/c/27545/23/src/arch/riscv/include/arch/stages… PS23, Line 21: void stage_entry(int hartid, void *fdt) __attribute__((section(".text.stage_entry"))); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/27545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24554528969e36c9e98c0ebd733e002e215a52e5 Gerrit-Change-Number: 27545 Gerrit-PatchSet: 23 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Dec 2018 06:34:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove unused variables
by Patrick Rudolph (Code Review) 02 Dec '18

02 Dec '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove unused variables ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/#/c/29917/15/src/northbridge/intel/x4x/early_in… File src/northbridge/intel/x4x/early_init.c: https://review.coreboot.org/#/c/29917/15/src/northbridge/intel/x4x/early_in… PS15, Line 226: reg16 = RCBA16(0x1a8); : reg16 &= ~0x3; : RCBA16(0x1a8) = reg16; > What do we need reg16 for? It's a 16bit register. Using 8bit access here could brick things, as there are many read,write-to-clear registers. Unlikely here, but I'd always use full register width access. -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 15 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Dec 2018 05:42:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: riscv: save FDT pointer from mscratch to HLS
by build bot (Jenkins) (Code Review) 02 Dec '18

02 Dec '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27545 ) Change subject: riscv: save FDT pointer from mscratch to HLS ...................................................................... Patch Set 22: (1 comment) https://review.coreboot.org/#/c/27545/22/src/arch/riscv/include/arch/stages… File src/arch/riscv/include/arch/stages.h: https://review.coreboot.org/#/c/27545/22/src/arch/riscv/include/arch/stages… PS22, Line 21: void stage_entry(int hartid, void *fdt) __attribute__((section(".text.stage_entry"))); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/27545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24554528969e36c9e98c0ebd733e002e215a52e5 Gerrit-Change-Number: 27545 Gerrit-PatchSet: 22 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Dec 2018 04:28:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: riscv: add support to select the privilege level of the payload running
by build bot (Jenkins) (Code Review) 02 Dec '18

02 Dec '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29494 ) Change subject: riscv: add support to select the privilege level of the payload running ...................................................................... Patch Set 19: (1 comment) https://review.coreboot.org/#/c/29494/19/src/arch/riscv/boot.c File src/arch/riscv/boot.c: https://review.coreboot.org/#/c/29494/19/src/arch/riscv/boot.c@46 PS19, Line 46: void (*doit)(void *) = prog_entry(prog); function definition argument 'void *' should also have an identifier name -- To view, visit https://review.coreboot.org/c/coreboot/+/29494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951 Gerrit-Change-Number: 29494 Gerrit-PatchSet: 19 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Dec 2018 04:18:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2018