coreboot-gerrit December 2018

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Change in ...coreboot[master]: cpu/intel/fsp_model_406dx: Drop dead microcode reference
by Angel Pons (Code Review) 03 Dec '18

03 Dec '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29931 ) Change subject: cpu/intel/fsp_model_406dx: Drop dead microcode reference ...................................................................... Patch Set 1: Code-Review+2 I wonder how stuff ends up like this. -- To view, visit https://review.coreboot.org/c/coreboot/+/29931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia724262a526fe960c17ae4b248acfa42fc342331 Gerrit-Change-Number: 29931 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Fei Wang Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Dec 2018 12:48:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel/fsp_model_406dx: Drop dead microcode reference
by Nico Huber (Code Review) 03 Dec '18

03 Dec '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29931 ) Change subject: cpu/intel/fsp_model_406dx: Drop dead microcode reference ...................................................................... Patch Set 1: > Patch Set 1: Code-Review+1 Thanks. David, may I assume that you'd given +2 if your account allowed it? Do you need help to get access to your account registered as <david.guckian(a)intel.com>? Fei, we have Gerrit set up to automatically add people to reviews that are mentioned in the MAINTAINERS file. I assume that doesn't work in your case yet, because your email address in that file is not associated to your account. -- To view, visit https://review.coreboot.org/c/coreboot/+/29931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia724262a526fe960c17ae4b248acfa42fc342331 Gerrit-Change-Number: 29931 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Fei Wang Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Dec 2018 12:38:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/lenovo: Add ThinkPad T431s
by Bill XIE (Code Review) 03 Dec '18

03 Dec '18

Hello Alexander Couzens, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30021 to look at the new patch set (#3). Change subject: mainboard/lenovo: Add ThinkPad T431s ...................................................................... mainboard/lenovo: Add ThinkPad T431s The code is based on autoport and that for T430s Tested: - CPU i5-3337U - Slotted DIMM 2GiB - Soldered RAM 4GiB from samsung (There may be more models here) - Camera - pci-e and usb2 on M.2 slot with A key for wlan - sata and usb2 (no superspeed components) on M.2 slot with B key for wwan - On board SDHCI connected to pci-e - USB3 ports - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - TPM1 on LPC - EHCI debug on SSP2 (USB3 port on the left) - Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from Linux payload (Heads), Seabios may also work. Not tested: - Fingerprint reader on USB2 (not present on mine) - Keyboard backlight (not present on mine) - "sticky_fn" flag in nvram Not implemented yet: - Fn locking in nvram (may not be identical to "sticky_fn") - Detecting the model of Soldered RAM at runtime, and loading the corresponding SPD datum (3 observed) from CBFS (the mechanism may be similar to that on x1_carbon_gen1 and s230u, but I do not know how to find gpio ports for that, and SPD data stored in vendor firmware.) Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a Signed-off-by: Bill XIE <persmule(a)gmail.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/t431s.md A Documentation/mainboard/lenovo/t431s_bc_removed.jpg A Documentation/mainboard/lenovo/t431s_flash_chip.jpg A Documentation/mainboard/lenovo/t431s_programming.jpg A src/mainboard/lenovo/t431s/Kconfig A src/mainboard/lenovo/t431s/Kconfig.name A src/mainboard/lenovo/t431s/Makefile.inc A src/mainboard/lenovo/t431s/acpi/ec.asl A src/mainboard/lenovo/t431s/acpi/platform.asl A src/mainboard/lenovo/t431s/acpi/superio.asl A src/mainboard/lenovo/t431s/acpi_tables.c A src/mainboard/lenovo/t431s/board_info.txt A src/mainboard/lenovo/t431s/cmos.default A src/mainboard/lenovo/t431s/cmos.layout A src/mainboard/lenovo/t431s/data.vbt A src/mainboard/lenovo/t431s/devicetree.cb A src/mainboard/lenovo/t431s/dsdt.asl A src/mainboard/lenovo/t431s/gma-mainboard.ads A src/mainboard/lenovo/t431s/gpio.c A src/mainboard/lenovo/t431s/hda_verb.c A src/mainboard/lenovo/t431s/mainboard.c A src/mainboard/lenovo/t431s/romstage.c A src/mainboard/lenovo/t431s/spd/Makefile.inc A src/mainboard/lenovo/t431s/spd/samsung_4gb.spd.hex A src/mainboard/lenovo/t431s/thermal.h 26 files changed, 1,134 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/30021/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/30021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a Gerrit-Change-Number: 30021 Gerrit-PatchSet: 3 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mainboard/lenovo: Add ThinkPad T431s
by Bill XIE (Code Review) 03 Dec '18

03 Dec '18

Hello Alexander Couzens, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30021 to look at the new patch set (#2). Change subject: mainboard/lenovo: Add ThinkPad T431s ...................................................................... mainboard/lenovo: Add ThinkPad T431s The code is based on autoport and that for T430s Tested: - CPU i5-3337U - Slotted DIMM 2GiB - Soldered RAM 4GiB from samsung (There may be more models here) - Camera - pci-e and usb2 on M.2 slot with A key for wlan - sata and usb2 (no superspeed components) on M.2 slot with B key for wwan - On board SDHCI connected to pci-e - USB3 ports - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - TPM1 on LPC - EHCI debug on SSP2 (USB3 port on the left) - Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from Linux payload (Heads), Seabios may also work. Not tested: - Fingerprint reader on USB2 (not present on mine) - Keyboard backlight (not present on mine) - "sticky_fn" flag in nvram Not implemented yet: - Fn locking in nvram (may not be identical to "sticky_fn") - Detecting the model of Soldered RAM at runtime, and loading the corresponding SPD datum (3 observed) from CBFS (the mechanism may be similar to that on x1_carbon_gen1 and s230u, but I do not know how to find gpio ports for that, and SPD data stored in vendor firmware.) Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a Signed-off-by: Bill XIE <persmule(a)gmail.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/t431s.md A Documentation/mainboard/lenovo/t431s_bc_removed.jpg A Documentation/mainboard/lenovo/t431s_flash_chip.jpg A Documentation/mainboard/lenovo/t431s_programming.jpg A src/mainboard/lenovo/t431s/Kconfig A src/mainboard/lenovo/t431s/Kconfig.name A src/mainboard/lenovo/t431s/Makefile.inc A src/mainboard/lenovo/t431s/acpi/ec.asl A src/mainboard/lenovo/t431s/acpi/platform.asl A src/mainboard/lenovo/t431s/acpi/superio.asl A src/mainboard/lenovo/t431s/acpi_tables.c A src/mainboard/lenovo/t431s/board_info.txt A src/mainboard/lenovo/t431s/cmos.default A src/mainboard/lenovo/t431s/cmos.layout A src/mainboard/lenovo/t431s/data.vbt A src/mainboard/lenovo/t431s/devicetree.cb A src/mainboard/lenovo/t431s/dsdt.asl A src/mainboard/lenovo/t431s/gma-mainboard.ads A src/mainboard/lenovo/t431s/gpio.c A src/mainboard/lenovo/t431s/hda_verb.c A src/mainboard/lenovo/t431s/mainboard.c A src/mainboard/lenovo/t431s/romstage.c A src/mainboard/lenovo/t431s/spd/Makefile.inc A src/mainboard/lenovo/t431s/spd/samsung_4gb.spd.hex A src/mainboard/lenovo/t431s/thermal.h 26 files changed, 1,134 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/30021/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a Gerrit-Change-Number: 30021 Gerrit-PatchSet: 2 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mainboard/lenovo: Add ThinkPad T431s
by build bot (Jenkins) (Code Review) 03 Dec '18

03 Dec '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30021 ) Change subject: mainboard/lenovo: Add ThinkPad T431s ...................................................................... Patch Set 1: (16 comments) https://review.coreboot.org/#/c/30021/1/src/mainboard/lenovo/t431s/romstage… File src/mainboard/lenovo/t431s/romstage.c: https://review.coreboot.org/#/c/30021/1/src/mainboard/lenovo/t431s/romstage… PS1, Line 62: void mainboard_get_spd(spd_raw_data *spd, bool id_only) { open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/30021/1/src/mainboard/lenovo/t431s/spd/sams… File src/mainboard/lenovo/t431s/spd/samsung_4gb.spd.hex: https://review.coreboot.org/#/c/30021/1/src/mainboard/lenovo/t431s/spd/sams… PS1, Line 1: 92 11 0b 03 04 00 00 01 03 52 01 08 0a 00 80 00 trailing whitespace https://review.coreboot.org/#/c/30021/1/src/mainboard/lenovo/t431s/spd/sams… PS1, Line 2: 6e 78 6e 32 6e 11 18 81 20 08 3c 3c 00 f0 00 00 trailing whitespace https://review.coreboot.org/#/c/30021/1/src/mainboard/lenovo/t431s/spd/sams… PS1, Line 3: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 trailing whitespace https://review.coreboot.org/#/c/30021/1/src/mainboard/lenovo/t431s/spd/sams… PS1, Line 4: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00 trailing whitespace https://review.coreboot.org/#/c/30021/1/src/mainboard/lenovo/t431s/spd/sams… PS1, Line 5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 trailing whitespace https://review.coreboot.org/#/c/30021/1/src/mainboard/lenovo/t431s/spd/sams… PS1, Line 6: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 trailing whitespace https://review.coreboot.org/#/c/30021/1/src/mainboard/lenovo/t431s/spd/sams… PS1, Line 7: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 trailing whitespace https://review.coreboot.org/#/c/30021/1/src/mainboard/lenovo/t431s/spd/sams… PS1, Line 8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b6 3b trailing whitespace https://review.coreboot.org/#/c/30021/1/src/mainboard/lenovo/t431s/spd/sams… PS1, Line 9: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 trailing whitespace https://review.coreboot.org/#/c/30021/1/src/mainboard/lenovo/t431s/spd/sams… PS1, Line 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 trailing whitespace https://review.coreboot.org/#/c/30021/1/src/mainboard/lenovo/t431s/spd/sams… PS1, Line 11: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 trailing whitespace https://review.coreboot.org/#/c/30021/1/src/mainboard/lenovo/t431s/spd/sams… PS1, Line 12: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 trailing whitespace https://review.coreboot.org/#/c/30021/1/src/mainboard/lenovo/t431s/spd/sams… PS1, Line 13: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 trailing whitespace https://review.coreboot.org/#/c/30021/1/src/mainboard/lenovo/t431s/spd/sams… PS1, Line 14: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 trailing whitespace https://review.coreboot.org/#/c/30021/1/src/mainboard/lenovo/t431s/spd/sams… PS1, Line 15: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/30021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a Gerrit-Change-Number: 30021 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Dec 2018 12:20:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/lenovo: Add ThinkPad T431s
by Bill XIE (Code Review) 03 Dec '18

03 Dec '18

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30021 Change subject: mainboard/lenovo: Add ThinkPad T431s ...................................................................... mainboard/lenovo: Add ThinkPad T431s The code is based on autoport and that for T430s Tested: - CPU i5-3337U - Slotted DIMM 2GiB - Soldered RAM 4GiB from samsung (There may be more models here) - Camera - pci-e and usb2 on M.2 slot with A key for wlan - sata and usb2 (no superspeed components) on M.2 slot with B key for wwan - On board SDHCI connected to pci-e - USB3 ports - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - TPM1 on LPC - EHCI debug on SSP2 (USB3 port on the left) - Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from Linux payload (Heads), Seabios may also work. Not tested: - Fingerprint reader on USB2 (not present on mine) - Keyboard backlight (not present on mine) - "sticky_fn" flag in nvram Not implemented yet: - Fn locking in nvram (may not be identical to "sticky_fn") - Detecting the model of Soldered RAM at runtime, and loading the corresponding SPD datum (3 observed) from CBFS (the mechanism may be similar to that on x1_carbon_gen1 and s230u, but I do not know how to find gpio ports for that, and SPD data stored in vendor firmware.) Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a Signed-off-by: Bill XIE <persmule(a)gmail.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/t431s.md A Documentation/mainboard/lenovo/t431s_bc_removed.jpg A Documentation/mainboard/lenovo/t431s_flash_chip.jpg A Documentation/mainboard/lenovo/t431s_programming.jpg A src/mainboard/lenovo/t431s/Kconfig A src/mainboard/lenovo/t431s/Kconfig.name A src/mainboard/lenovo/t431s/Makefile.inc A src/mainboard/lenovo/t431s/acpi/ec.asl A src/mainboard/lenovo/t431s/acpi/platform.asl A src/mainboard/lenovo/t431s/acpi/superio.asl A src/mainboard/lenovo/t431s/acpi_tables.c A src/mainboard/lenovo/t431s/board_info.txt A src/mainboard/lenovo/t431s/cmos.default A src/mainboard/lenovo/t431s/cmos.layout A src/mainboard/lenovo/t431s/data.vbt A src/mainboard/lenovo/t431s/devicetree.cb A src/mainboard/lenovo/t431s/dsdt.asl A src/mainboard/lenovo/t431s/gma-mainboard.ads A src/mainboard/lenovo/t431s/gpio.c A src/mainboard/lenovo/t431s/hda_verb.c A src/mainboard/lenovo/t431s/mainboard.c A src/mainboard/lenovo/t431s/romstage.c A src/mainboard/lenovo/t431s/spd/Makefile.inc A src/mainboard/lenovo/t431s/spd/samsung_4gb.spd.hex A src/mainboard/lenovo/t431s/thermal.h 26 files changed, 1,133 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/30021/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 128f0c1..356f203 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -60,6 +60,7 @@ - [T530](lenovo/w530.md) - [W530](lenovo/w530.md) - [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md) +- [T431s](lenovo/t431s.md) ## SiFive diff --git a/Documentation/mainboard/lenovo/t431s.md b/Documentation/mainboard/lenovo/t431s.md new file mode 100644 index 0000000..9a8a4b9 --- /dev/null +++ b/Documentation/mainboard/lenovo/t431s.md @@ -0,0 +1,33 @@ +# Lenovo T431s + +## disassembly instructions + +You must remove the following parts before flipping the mainboard +off the main frame: + +![t431s_bc_removed](t431s_bc_removed.jpg) + +* Base cover +* Hard disk drive +* Battery pack +* Keyboard + +Its [Hardware Maintenance Manual](https://thinkpads.com/support/hmm/hmm_pdf/t431s_hmm_en_0c10894_02.p… could be used as a guidance of disassembly. + +![t431s_flash_chip](t431s_flash_chip.jpg) + +The WSON-8 flash chip (surrounded with red circle in the photo above) +sits on the opposite side of the mainboard, under a piece of insulating +stick. If solders between the chip and soldering pads fortunately +overflows beside the chip as tiny tin balls attached to soldering pads, +it will be possible to use a pomona 5250 clip to hold the chip, with +its metal tips just attached to tin balls, thus connecting the chip to +the programmer. + +![t431s_programming](t431s_programming.jpg) + +```eval_rst +:doc:`../../flash_tutorial/ext_power` +``` + +[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md diff --git a/Documentation/mainboard/lenovo/t431s_bc_removed.jpg b/Documentation/mainboard/lenovo/t431s_bc_removed.jpg new file mode 100644 index 0000000..4f8ddd6 --- /dev/null +++ b/Documentation/mainboard/lenovo/t431s_bc_removed.jpg Binary files differ diff --git a/Documentation/mainboard/lenovo/t431s_flash_chip.jpg b/Documentation/mainboard/lenovo/t431s_flash_chip.jpg new file mode 100644 index 0000000..48c861e --- /dev/null +++ b/Documentation/mainboard/lenovo/t431s_flash_chip.jpg Binary files differ diff --git a/Documentation/mainboard/lenovo/t431s_programming.jpg b/Documentation/mainboard/lenovo/t431s_programming.jpg new file mode 100644 index 0000000..c49562a --- /dev/null +++ b/Documentation/mainboard/lenovo/t431s_programming.jpg Binary files differ diff --git a/src/mainboard/lenovo/t431s/Kconfig b/src/mainboard/lenovo/t431s/Kconfig new file mode 100644 index 0000000..b6e06c6 --- /dev/null +++ b/src/mainboard/lenovo/t431s/Kconfig @@ -0,0 +1,65 @@ +if BOARD_LENOVO_T431S + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SYSTEM_TYPE_LAPTOP + select CPU_INTEL_SOCKET_RPGA989 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select USE_NATIVE_RAMINIT + select SOUTHBRIDGE_INTEL_C216 + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select NO_UART_ON_SUPERIO + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select INTEL_INT15 + select SANDYBRIDGE_IVYBRIDGE_LVDS + select ENABLE_VMX + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select MAINBOARD_HAS_LIBGFXINIT + select INTEL_GMA_HAVE_VBT + + # Workaround for EC/KBC IRQ1. + select SERIRQ_CONTINUOUS_MODE + +config MAINBOARD_DIR + string + default lenovo/t431s + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad T431s" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config DRAM_RESET_GATE_GPIO + int + default 10 + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x17aa + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2208 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +endif # BOARD_LENOVO_T431S diff --git a/src/mainboard/lenovo/t431s/Kconfig.name b/src/mainboard/lenovo/t431s/Kconfig.name new file mode 100644 index 0000000..4a0fdba --- /dev/null +++ b/src/mainboard/lenovo/t431s/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_T431S + bool "ThinkPad T431s" diff --git a/src/mainboard/lenovo/t431s/Makefile.inc b/src/mainboard/lenovo/t431s/Makefile.inc new file mode 100644 index 0000000..a312a0f --- /dev/null +++ b/src/mainboard/lenovo/t431s/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +subdirs-y += spd \ No newline at end of file diff --git a/src/mainboard/lenovo/t431s/acpi/ec.asl b/src/mainboard/lenovo/t431s/acpi/ec.asl new file mode 100644 index 0000000..d631f12 --- /dev/null +++ b/src/mainboard/lenovo/t431s/acpi/ec.asl @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/lenovo/h8/acpi/ec.asl> + +Scope(\_SB.PCI0.LPCB.EC) +{ +} diff --git a/src/mainboard/lenovo/t431s/acpi/platform.asl b/src/mainboard/lenovo/t431s/acpi/platform.asl new file mode 100644 index 0000000..e4c8a24 --- /dev/null +++ b/src/mainboard/lenovo/t431s/acpi/platform.asl @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) + \_SB.PCI0.LPCB.EC.RADI(0) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + + /* Not implemented. */ + Return(Package(){0,0}) +} diff --git a/src/mainboard/lenovo/t431s/acpi/superio.asl b/src/mainboard/lenovo/t431s/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/lenovo/t431s/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/t431s/acpi_tables.c b/src/mainboard/lenovo/t431s/acpi_tables.c new file mode 100644 index 0000000..279674d --- /dev/null +++ b/src/mainboard/lenovo/t431s/acpi_tables.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + acpi_update_thermal_table(gnvs); +} diff --git a/src/mainboard/lenovo/t431s/board_info.txt b/src/mainboard/lenovo/t431s/board_info.txt new file mode 100644 index 0000000..11f5e87 --- /dev/null +++ b/src/mainboard/lenovo/t431s/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-8 / WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2013 diff --git a/src/mainboard/lenovo/t431s/cmos.default b/src/mainboard/lenovo/t431s/cmos.default new file mode 100644 index 0000000..979f132 --- /dev/null +++ b/src/mainboard/lenovo/t431s/cmos.default @@ -0,0 +1,16 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +volume=0x3 +first_battery=Primary +bluetooth=Enable +wwan=Enable +wlan=Enable +touchpad=Enable +sata_mode=AHCI +fn_ctrl_swap=Disable +sticky_fn=Disable +trackpoint=Enable +backlight=Both +usb_always_on=Disable diff --git a/src/mainboard/lenovo/t431s/cmos.layout b/src/mainboard/lenovo/t431s/cmos.layout new file mode 100644 index 0000000..62a6ad45 --- /dev/null +++ b/src/mainboard/lenovo/t431s/cmos.layout @@ -0,0 +1,136 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 12 usb_always_on +421 1 e 9 sata_mode +422 2 e 10 backlight + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 1 e 1 enable_dual_graphics +#436 4 r 0 unused +440 8 h 0 volume + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Disable +12 1 AC and battery +12 2 AC only + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/lenovo/t431s/data.vbt b/src/mainboard/lenovo/t431s/data.vbt new file mode 100644 index 0000000..7593154 --- /dev/null +++ b/src/mainboard/lenovo/t431s/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/t431s/devicetree.cb b/src/mainboard/lenovo/t431s/devicetree.cb new file mode 100644 index 0000000..a4286e6 --- /dev/null +++ b/src/mainboard/lenovo/t431s/devicetree.cb @@ -0,0 +1,193 @@ +chip northbridge/intel/sandybridge + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + + # Enable DisplayPort Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + + # Enable Panel as eDP and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms + register "gpu_panel_power_up_delay" = "2000" # T1+T2: 10ms + register "gpu_panel_power_down_delay" = "500" # T5+T6: 10ms + register "gpu_panel_power_backlight_on_delay" = "1" # T3: 210ms + register "gpu_panel_power_backlight_off_delay" = "1" # T4: 210ms + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.link_frequency_270_mhz" = "1" + register "gpu_cpu_backlight" = "0x03d2" + register "gpu_pch_backlight" = "0x11551155" + + device cpu_cluster 0 on + chip cpu/intel/socket_rPGA989 + device lapic 0 on end + end + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + end + end + + register "pci_mmio_size" = "2048" + + device domain 0 on + device pci 00.0 on + subsystemid 0x17aa 0x2208 + end # host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on + subsystemid 0x17aa 0x2208 + end # Integrated Graphics Controller + + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi1_routing" = "2" + register "gpi13_routing" = "2" + + # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock) + register "sata_port_map" = "0x17" + # Set max SATA speed to 6.0 Gb/s + register "sata_interface_speed_support" = "0x3" + + register "gen1_dec" = "0x7c1601" + register "gen2_dec" = "0x0c15e1" + register "gen4_dec" = "0x0c06a1" + + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + + # Wire port 4 (wwan usb) to ehci for it lacks superspeed components + register "xhci_switchable_ports" = "0x7" + register "superspeed_capable_ports" = "0xf" + register "xhci_overcurrent_mapping" = "0x4000201" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + register "c2_latency" = "101" # c2 not supported + register "p_cnt_throttling_supported" = "1" + register "docking_supported" = "1" + + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + + device pci 14.0 on + subsystemid 0x17aa 0x2208 + end # USB 3.0 Controller + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on + subsystemid 0x17aa 0x21f3 + end # Intel Gigabit Ethernet + device pci 1a.0 on + subsystemid 0x17aa 0x2208 + end # USB Enhanced Host Controller #2 + device pci 1b.0 on + subsystemid 0x17aa 0x2208 + end # High Definition Audio Controller + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x17aa 0x2208 + chip drivers/ricoh/rce822 # Ricoh cardreader + register "disable_mask" = "0x87" + register "sdwppol" = "0" + device pci 00.0 on # Ricoh SD card reader + subsystemid 0x17aa 0x2208 + end + end + end + device pci 1c.1 on + subsystemid 0x17aa 0x2208 + end # PCIe Port #2 Integrated Wireless LAN + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on + subsystemid 0x17aa 0x2208 + end # USB Enhanced Host Controller #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + subsystemid 0x17aa 0x2208 + chip ec/lenovo/pmh7 + device pnp ff.1 on # dummy + end + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + end + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + + chip ec/lenovo/h8 + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + + register "config0" = "0xa6" + register "config1" = "0x09" + register "config2" = "0xa0" + register "config3" = "0xc0" + + register "has_keyboard_backlight" = "1" + + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "has_power_management_beeps" = "0" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xd0" + register "event5_enable" = "0x3c" + register "event6_enable" = "0x00" + register "event7_enable" = "0x01" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventa_enable" = "0x00" + register "eventb_enable" = "0x00" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x1d" + + # T431s only has BT on wlan card + register "has_bdc_detection" = "0" + end + end # LPC Controller + device pci 1f.2 on + subsystemid 0x17aa 0x2208 + end # 6 port SATA AHCI Controller + device pci 1f.3 on + subsystemid 0x17aa 0x2208 + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end # SMBus Controller + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/lenovo/t431s/dsdt.asl b/src/mainboard/lenovo/t431s/dsdt.asl new file mode 100644 index 0000000..1cb4add --- /dev/null +++ b/src/mainboard/lenovo/t431s/dsdt.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define THINKPAD_EC_GPE 17 +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> +} diff --git a/src/mainboard/lenovo/t431s/gma-mainboard.ads b/src/mainboard/lenovo/t431s/gma-mainboard.ads new file mode 100644 index 0000000..d635d88 --- /dev/null +++ b/src/mainboard/lenovo/t431s/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- Copyright (C) 2017 Bill XIE persmule(a)gmail.com +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t431s/gpio.c b/src/mainboard/lenovo/t431s/gpio.c new file mode 100644 index 0000000..5e0684c --- /dev/null +++ b/src/mainboard/lenovo/t431s/gpio.c @@ -0,0 +1,206 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_NATIVE, + .gpio7 = GPIO_MODE_NATIVE, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_NATIVE, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio3 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_LOW, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_NATIVE, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio43 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_NATIVE, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/t431s/hda_verb.c b/src/mainboard/lenovo/t431s/hda_verb.c new file mode 100644 index 0000000..179fba0 --- /dev/null +++ b/src/mainboard/lenovo/t431s/hda_verb.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x17aa2208, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x17aa2208), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x03211020), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x40008000), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x03a11030), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x40f38205), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/t431s/mainboard.c b/src/mainboard/lenovo/t431s/mainboard.c new file mode 100644 index 0000000..6c85aba --- /dev/null +++ b/src/mainboard/lenovo/t431s/mainboard.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011-2012 Google Inc. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <ec/lenovo/h8/h8.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +void h8_mainboard_init_dock(void) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/t431s/romstage.c b/src/mainboard/lenovo/t431s/romstage.c new file mode 100644 index 0000000..c87e218 --- /dev/null +++ b/src/mainboard/lenovo/t431s/romstage.c @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <option.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <console/console.h> +#include <cbfs.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/lenovo/pmh7/pmh7.h> + +void pch_enable_lpc(void) +{ + /* EC Decode Range Port60/64, Port62/66 */ + /* Enable EC, PS/2 Keyboard/Mouse */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, /* SSP1: right */ + { 1, 0, 1 }, /* SSP2: left, EHCI Debug */ + { 1, 1, 3 }, /* SSP3: dock usb3 */ + { 1, 1, -1 }, /* B0P4: wwan usb */ + { 1, 1, 2 }, /* B0P5: dock usb2 */ + { 0, 0, -1 }, /* B0P6 */ + { 0, 0, -1 }, /* B0P7 */ + { 1, 2, -1 }, /* B0P8: unknown */ + { 1, 0, -1 }, /* B1P1: smart card reader */ + { 0, 2, 5 }, /* B1P2 */ + { 1, 1, -1 }, /* B1P3: fingerprint reader */ + { 0, 0, -1 }, /* B1P4 */ + { 1, 1, -1 }, /* B1P5: wlan usb */ + { 1, 1, -1 }, /* B1P6: Camera */ +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) { + /* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */ + size_t spd_file_len = 0; + void *spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + + if (!spd_file || spd_file_len < sizeof(spd_raw_data)) + die("SPD data for C1S0 not found."); + + memcpy(&spd[0], spd_file, spd_file_len); + read_spd(&spd[2], 0x51, id_only); +} + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} diff --git a/src/mainboard/lenovo/t431s/spd/Makefile.inc b/src/mainboard/lenovo/t431s/spd/Makefile.inc new file mode 100644 index 0000000..17bb8fa --- /dev/null +++ b/src/mainboard/lenovo/t431s/spd/Makefile.inc @@ -0,0 +1,31 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Alexander Couzens <lynxis(a)fe80.eu> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = samsung_4gb # 0b0010 4GiB +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd \ No newline at end of file diff --git a/src/mainboard/lenovo/t431s/spd/samsung_4gb.spd.hex b/src/mainboard/lenovo/t431s/spd/samsung_4gb.spd.hex new file mode 100644 index 0000000..252ff3f --- /dev/null +++ b/src/mainboard/lenovo/t431s/spd/samsung_4gb.spd.hex @@ -0,0 +1,16 @@ +92 11 0b 03 04 00 00 01 03 52 01 08 0a 00 80 00 +6e 78 6e 32 6e 11 18 81 20 08 3c 3c 00 f0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 b6 3b +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ No newline at end of file diff --git a/src/mainboard/lenovo/t431s/thermal.h b/src/mainboard/lenovo/t431s/thermal.h new file mode 100644 index 0000000..1d55584 --- /dev/null +++ b/src/mainboard/lenovo/t431s/thermal.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef T430S_THERMAL_H +#define T430S_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* T430S_THERMAL_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a Gerrit-Change-Number: 30021 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: src: Remove unused variables
by Patrick Georgi (Code Review) 03 Dec '18

03 Dec '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove unused variables ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/#/c/29917/15/src/cpu/amd/family_10h-family_15h/… File src/cpu/amd/family_10h-family_15h/init_cpus.c: https://review.coreboot.org/#/c/29917/15/src/cpu/amd/family_10h-family_15h/… PS15, Line 1062: !! > are you sure? […] It transforms nvram (any integer value, where 0 is meant to be false, and everything else is true) into a bool (0 or 1). It's sometimes needed, when you then proceed to interpret the boolean value numerically, but not here. -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 15 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Dec 2018 11:27:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP]sb/intel/common/smihandler: Hook up smmstore
by build bot (Jenkins) (Code Review) 03 Dec '18

03 Dec '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30012 ) Change subject: [WIP]sb/intel/common/smihandler: Hook up smmstore ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/30012/3/src/southbridge/intel/common/smihan… File src/southbridge/intel/common/smihandler.c: https://review.coreboot.org/#/c/30012/3/src/southbridge/intel/common/smihan… PS3, Line 287: io_smi->rax = ret; code indent should use tabs where possible https://review.coreboot.org/#/c/30012/3/src/southbridge/intel/common/smihan… PS3, Line 287: io_smi->rax = ret; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/30012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20b87f3dcb898656ad31478820dd5153e4053cb2 Gerrit-Change-Number: 30012 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Dec 2018 11:22:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: cpu/x86/lapic: Link apic_timer.c into SMM
by Arthur Heymans (Code Review) 03 Dec '18

03 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30020 Change subject: cpu/x86/lapic: Link apic_timer.c into SMM ...................................................................... cpu/x86/lapic: Link apic_timer.c into SMM This provides udelay() and a monotonic timer to SMM. Also remove the custom implementation on i945. Change-Id: Ic14919f89b226b4d5185e49ae857e7dd61bbccce Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/lapic/Makefile.inc M src/northbridge/intel/i945/Makefile.inc D src/northbridge/intel/i945/udelay.c 3 files changed, 1 insertion(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/30020/1 diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 9454f8f..7637250 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -4,6 +4,7 @@ romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c +smm-$(CONFIG_UDELAY_LAPIC) += apic_timer.c bootblock-y += boot_cpu.c verstage-y += boot_cpu.c romstage-y += boot_cpu.c diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index ffeabdc..fa51df7 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -27,8 +27,6 @@ romstage-y += debug.c romstage-y += rcven.c -smm-y += udelay.c - postcar-y += ram_calc.c endif diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c deleted file mode 100644 index 8447453..0000000 --- a/src/northbridge/intel/i945/udelay.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <delay.h> -#include <stdint.h> -#include <cpu/x86/tsc.h> -#include <cpu/x86/msr.h> -#include <cpu/intel/speedstep.h> - -/** - * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock - */ - -void udelay(u32 us) -{ - u32 dword; - tsc_t tsc, tsc1, tscd; - msr_t msr; - u32 fsb = 0, divisor; - u32 d; /* ticks per us */ - - msr = rdmsr(MSR_FSB_FREQ); - switch (msr.lo & 0x07) { - case 5: - fsb = 400; - break; - case 1: - fsb = 533; - break; - case 3: - fsb = 667; - break; - case 2: - fsb = 800; - break; - case 0: - fsb = 1067; - break; - case 4: - fsb = 1333; - break; - case 6: - fsb = 1600; - break; - } - - msr = rdmsr(IA32_PERF_STATUS); - divisor = (msr.hi >> 8) & 0x1f; - - d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ - - multiply_to_tsc(&tscd, us, d); - - tsc1 = rdtsc(); - dword = tsc1.lo + tscd.lo; - if ((dword < tsc1.lo) || (dword < tscd.lo)) - tsc1.hi++; - tsc1.lo = dword; - tsc1.hi += tscd.hi; - - do { - tsc = rdtsc(); - } while ((tsc.hi < tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/30020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic14919f89b226b4d5185e49ae857e7dd61bbccce Gerrit-Change-Number: 30020 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: sb/intel/common/smi.c: Remove unused functions
by Arthur Heymans (Code Review) 03 Dec '18

03 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30019 Change subject: sb/intel/common/smi.c: Remove unused functions ...................................................................... sb/intel/common/smi.c: Remove unused functions Since all targets using sb/intel/common and cpu/intel/smm/gen1 are now using PARALLEL_MP some code is not used anymore. Change-Id: Ibdc2bb0f1412366b945813efbc1b6451d27f376f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/smm/gen1/smi.h M src/cpu/intel/smm/gen1/smmrelocate.c M src/southbridge/intel/common/smi.c 3 files changed, 0 insertions(+), 204 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/30019/1 diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h index d6a6f88..ec62458 100644 --- a/src/cpu/intel/smm/gen1/smi.h +++ b/src/cpu/intel/smm/gen1/smi.h @@ -17,11 +17,8 @@ /* These helpers are for performing SMM relocation. */ void southbridge_smm_init(void); -void southbridge_trigger_smi(void); -void southbridge_clear_smi_status(void); u32 northbridge_get_tseg_base(void); u32 northbridge_get_tseg_size(void); -int cpu_get_apic_id_map(int *apic_id_map); void northbridge_write_smram(u8 smram); void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index f2035f2..fa038a3 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -86,60 +86,6 @@ } } -/* The relocation work is actually performed in SMM context, but the code - * resides in the ramstage module. This occurs by trampolining from the default - * SMRAM entry point to here. */ -static void asmlinkage cpu_smm_do_relocation(void *arg) -{ - em64t101_smm_state_save_area_t *save_state; - msr_t mtrr_cap; - struct smm_relocation_params *relo_params; - const struct smm_module_params *p; - const struct smm_runtime *runtime; - int cpu; - - p = arg; - runtime = p->runtime; - relo_params = p->arg; - cpu = p->cpu; - - if (cpu >= CONFIG_MAX_CPUS) { - printk(BIOS_CRIT, - "Invalid CPU number assigned in SMM stub: %d\n", cpu); - return; - } - - printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); - - /* All threads need to set IEDBASE and SMBASE in the save state area. - * Since one thread runs at a time during the relocation the save state - * is the same for all cpus. */ - save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE - - runtime->save_state_size); - - /* The relocated handler runs with all CPUs concurrently. Therefore - * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. */ - save_state->smbase = relo_params->smram_base - - cpu * runtime->save_state_size; - if (CONFIG_IED_REGION_SIZE != 0) { - save_state->iedbase = relo_params->ied_base; - - printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n", - save_state->smbase, save_state->iedbase, save_state); - } else { - printk(BIOS_DEBUG, "New SMBASE=0x%08x @ %p\n", - save_state->smbase, save_state); - } - - /* Write SMRR MSRs based on indicated support. */ - mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED) - write_smrr(relo_params); - - southbridge_clear_smi_status(); -} - static void fill_in_relocation_params(struct smm_relocation_params *params) { /* All range registers are aligned to 4KiB */ @@ -188,33 +134,6 @@ } } -static int install_relocation_handler(int *apic_id_map, int num_cpus, - struct smm_relocation_params *relo_params) -{ - /* The default SMM entry happens serially at the default location. - * Therefore, there is only 1 concurrent save state area. Set the - * stack size to the save state size, and call into the - * do_relocation handler. */ - int save_state_size = sizeof(em64t101_smm_state_save_area_t); - struct smm_loader_params smm_params = { - .per_cpu_stack_size = save_state_size, - .num_concurrent_stacks = num_cpus, - .per_cpu_save_state_size = save_state_size, - .num_concurrent_save_states = 1, - .handler = &cpu_smm_do_relocation, - .handler_arg = (void *)relo_params, - }; - - default_smm_area = backup_default_smm_area(); - - if (smm_setup_relocation_handler(&smm_params)) - return -1; - int i; - for (i = 0; i < num_cpus; i++) - smm_params.runtime->apic_id_to_cpu[i] = apic_id_map[i]; - return 0; -} - static void setup_ied_area(struct smm_relocation_params *params) { char *ied_base; @@ -234,94 +153,6 @@ memset(ied_base + (1 << 20), 0, (32 << 10)); } -static int install_permanent_handler(int *apic_id_map, int num_cpus, - struct smm_relocation_params *relo_params) -{ - /* There are num_cpus concurrent stacks and num_cpus concurrent save - * state areas. Lastly, set the stack size to the save state size. */ - int save_state_size = sizeof(em64t101_smm_state_save_area_t); - struct smm_loader_params smm_params = { - .per_cpu_stack_size = save_state_size, - .num_concurrent_stacks = num_cpus, - .per_cpu_save_state_size = save_state_size, - .num_concurrent_save_states = num_cpus, - }; - - printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", - relo_params->smram_base); - if (smm_load_module((void *)relo_params->smram_base, - relo_params->smram_size, &smm_params)) - return -1; - int i; - for (i = 0; i < num_cpus; i++) - smm_params.runtime->apic_id_to_cpu[i] = apic_id_map[i]; - return 0; -} - -static int cpu_smm_setup(void) -{ - int num_cpus; - int apic_id_map[CONFIG_MAX_CPUS]; - - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - /* enable the SMM memory window */ - northbridge_write_smram(D_OPEN | G_SMRAME | C_BASE_SEG); - - if (CONFIG_IED_REGION_SIZE != 0) - setup_ied_area(&smm_reloc_params); - - num_cpus = cpu_get_apic_id_map(apic_id_map); - if (num_cpus > CONFIG_MAX_CPUS) { - printk(BIOS_CRIT, - "Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n", - num_cpus, CONFIG_MAX_CPUS); - } - - if (install_relocation_handler(apic_id_map, num_cpus, - &smm_reloc_params)) { - printk(BIOS_CRIT, "SMM Relocation handler install failed.\n"); - return -1; - } - - if (install_permanent_handler(apic_id_map, num_cpus, - &smm_reloc_params)) { - printk(BIOS_CRIT, "SMM Permanent handler install failed.\n"); - return -1; - } - - /* Ensure the SMM handlers hit DRAM before performing first SMI. */ - /* TODO(adurbin): Is this really needed? */ - wbinvd(); - - /* close the SMM memory window and enable normal SMM */ - northbridge_write_smram(G_SMRAME | C_BASE_SEG); - - return 0; -} - -void smm_init(void) -{ - /* Return early if CPU SMM setup failed. */ - if (cpu_smm_setup()) - return; - - southbridge_smm_init(); - - /* Initiate first SMI to kick off SMM-context relocation. Note: this - * SMI being triggered here queues up an SMI in the APs which are in - * wait-for-SIPI state. Once an AP gets an SIPI it will service the SMI - * at the SMM_DEFAULT_BASE before jumping to startup vector. */ - southbridge_trigger_smi(); - - printk(BIOS_DEBUG, "Relocation complete.\n"); - - /* Lock down the SMRAM space. */ - smm_lock(); -} - void smm_init_completion(void) { restore_default_smm_area(default_smm_area); diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 17ac0cb..36c01e6 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -104,38 +104,6 @@ write_pmbase32(SMI_EN, smi_en); } -void southbridge_trigger_smi(void) -{ - /** - * There are several methods of raising a controlled SMI# via - * software, among them: - * - Writes to io 0xb2 (APMC) - * - Writes to the Local Apic ICR with Delivery mode SMI. - * - * Using the local apic is a bit more tricky. According to - * AMD Family 11 Processor BKDG no destination shorthand must be - * used. - * The whole SMM initialization is quite a bit hardware specific, so - * I'm not too worried about the better of the methods at the moment - */ - - /* raise an SMI interrupt */ - printk(BIOS_SPEW, " ... raise SMI#\n"); - outb(0x00, 0xb2); -} - -void southbridge_clear_smi_status(void) -{ - /* Clear SMI status */ - reset_smi_status(); - - /* Clear PM1 status */ - reset_pm1_status(); - - /* Set EOS bit so other SMIs can occur. */ - smi_set_eos(); -} - void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/30019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdc2bb0f1412366b945813efbc1b6451d27f376f Gerrit-Change-Number: 30019 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit December 2018