coreboot-gerrit December 2018

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: src: Remove unused variables
by HAOUAS Elyes (Code Review) 03 Dec '18

03 Dec '18

Hello Patrick Rudolph, Angel Pons, Huang Jin, Julius Werner, York Yang, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Damien Zammit, David Guckian, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#16). Change subject: src: Remove unused variables ...................................................................... src: Remove unused variables Phase 1. fix 'unused variables' in order to enable Wunused. Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm64/boot.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/cpu/amd/quadcore/quadcore.c M src/device/dram/ddr3.c M src/drivers/spi/sst.c M src/lib/selfboot.c M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/early_init.c M src/northbridge/via/vx900/raminit_ddr3.c M src/soc/cavium/common/bootblock.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/i82371eb/fadt.c 22 files changed, 51 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 16 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: sb/intel/lynxpoint: Make the finalise handler common
by Patrick Georgi (Code Review) 03 Dec '18

03 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29975 ) Change subject: sb/intel/lynxpoint: Make the finalise handler common ...................................................................... sb/intel/lynxpoint: Make the finalise handler common The ASRock H81M-HDS doesn't implement a finalise handler. To fix this, and reduce code duplication in the process, make a common implementation. There should be no functional change to boards with existing finalise handlers, since the code is identical among them and the new, common implementation. Tested on an ASRock H81M-HDS. The finalise handler works. Change-Id: I13b581a2219288019a4e0c9e618db3ac7c3c15ab Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/29975 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/google/beltino/smihandler.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/intel/baskingridge/mainboard_smi.c M src/southbridge/intel/lynxpoint/smihandler.c 4 files changed, 15 insertions(+), 60 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/google/beltino/smihandler.c b/src/mainboard/google/beltino/smihandler.c index 3d9324d..074a3e9 100644 --- a/src/mainboard/google/beltino/smihandler.c +++ b/src/mainboard/google/beltino/smihandler.c @@ -27,29 +27,6 @@ #include <superio/ite/it8772f/it8772f.h> #include "onboard.h" -static int mainboard_finalized = 0; - -int mainboard_smi_apmc(u8 apmc) -{ - switch (apmc) { - case APM_CNT_FINALIZE: - if (mainboard_finalized) { - printk(BIOS_DEBUG, "SMI#: Already finalized\n"); - return 0; - } - - intel_pch_finalize_smm(); - intel_northbridge_haswell_finalize_smm(); - intel_cpu_haswell_finalize_smm(); - - mainboard_finalized = 1; - break; - default: - break; - } - return 0; -} - void mainboard_smi_sleep(u8 slp_typ) { switch (slp_typ) { diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index 3480147..bab764a 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -119,24 +119,9 @@ while (google_chromeec_get_event() != 0); } - -static int mainboard_finalized = 0; - int mainboard_smi_apmc(u8 apmc) { switch (apmc) { - case APM_CNT_FINALIZE: - if (mainboard_finalized) { - printk(BIOS_DEBUG, "SMI#: Already finalized\n"); - return 0; - } - - intel_pch_finalize_smm(); - intel_northbridge_haswell_finalize_smm(); - intel_cpu_haswell_finalize_smm(); - - mainboard_finalized = 1; - break; case APM_CNT_ACPI_ENABLE: google_chromeec_set_smi_mask(0); /* Clear all pending events */ diff --git a/src/mainboard/intel/baskingridge/mainboard_smi.c b/src/mainboard/intel/baskingridge/mainboard_smi.c index 229085d..0fd0639 100644 --- a/src/mainboard/intel/baskingridge/mainboard_smi.c +++ b/src/mainboard/intel/baskingridge/mainboard_smi.c @@ -46,25 +46,3 @@ break; } } - - -static int mainboard_finalized = 0; - -int mainboard_smi_apmc(u8 apmc) -{ - switch (apmc) { - case APM_CNT_FINALIZE: - if (mainboard_finalized) { - printk(BIOS_DEBUG, "SMI#: Already finalized\n"); - return 0; - } - - intel_pch_finalize_smm(); - intel_northbridge_haswell_finalize_smm(); - intel_cpu_haswell_finalize_smm(); - - mainboard_finalized = 1; - break; - } - return 0; -} diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 87848c2..12e5ea2 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -25,6 +25,8 @@ #include <elog.h> #include <halt.h> #include <pc80/mc146818rtc.h> +#include <northbridge/intel/haswell/haswell.h> +#include <cpu/intel/haswell/haswell.h> #include "pch.h" #include "nvs.h" @@ -270,11 +272,24 @@ { u8 reg8; em64t101_smm_state_save_area_t *state; + static int chipset_finalized = 0; /* Emulate B2 register as the FADT / Linux expects it */ reg8 = inb(APM_CNT); switch (reg8) { + case APM_CNT_FINALIZE: + if (chipset_finalized) { + printk(BIOS_DEBUG, "SMI#: Already finalized\n"); + return; + } + + intel_pch_finalize_smm(); + intel_northbridge_haswell_finalize_smm(); + intel_cpu_haswell_finalize_smm(); + + chipset_finalized = 1; + break; case APM_CNT_CST_CONTROL: /* Calling this function seems to cause * some kind of race condition in Linux -- To view, visit https://review.coreboot.org/c/coreboot/+/29975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13b581a2219288019a4e0c9e618db3ac7c3c15ab Gerrit-Change-Number: 29975 Gerrit-PatchSet: 3 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/poppy/variant/nocturne: increase touch panel power-on delay
by Patrick Georgi (Code Review) 03 Dec '18

03 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29988 ) Change subject: mb/google/poppy/variant/nocturne: increase touch panel power-on delay ...................................................................... mb/google/poppy/variant/nocturne: increase touch panel power-on delay The WACOM 5C01 touch panel power-up delay of 10mS is too aggressive and causes "failed to change power setting" errors in the kernel, so this change increases the power-up delay to 20mS which allows enough time for the WACOM device's i2c controller to wake up. BUG=b:120090384 BRANCH=none TEST=flash and boot nocturne, log into kernel, execute the following command and make sure the string is not found : dmesg | grep "failed to change power setting" Change-Id: I1db0b3f5ce666b79d8ada2939ec865233ce52a56 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-on: https://review.coreboot.org/c/29988 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 1786502..031c7ff 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -320,7 +320,7 @@ register "generic.speed" = "I2C_SPEED_FAST_PLUS" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)" - register "generic.reset_delay_ms" = "10" + register "generic.reset_delay_ms" = "20" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/29988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1db0b3f5ce666b79d8ada2939ec865233ce52a56 Gerrit-Change-Number: 29988 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group
by Patrick Georgi (Code Review) 03 Dec '18

03 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29872 ) Change subject: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group ...................................................................... mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group We discovered that the gpios previously used for FPMCU_INT_L were in two different groups with two different voltages (C group was at 3.3V and D group was at 1.8V). Moving both to B group which is at 3.3V. BUG=b:119447525 BRANCH=Nami TEST=unlock OS with fingerprint register fingerprint run powerd_dbus_suspend and see if it goes int s0ix Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Signed-off-by: Shelley Chen <shchen(a)google.com> Reviewed-on: https://review.coreboot.org/c/29872 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nami/gpio.c 2 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Ren Kuo: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index edf7ed6..d4e5d2f 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -469,8 +469,8 @@ register "hid" = "ACPI_DT_NAMESPACE_HID" register "uid" = "1" register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)" - register "wake" = "GPE0_DW1_06" # GPP_D6 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B0_IRQ)" + register "wake" = "GPE0_DW0_01" # GPP_B1 device spi 0 on end end # FPMCU end # GSPI #1 diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index 2c9b932..a1a0f92 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -409,6 +409,10 @@ }; static const struct pad_config fpmcu_gpio_table[] = { + /* B0 : CORE_VID0 ==> FPMCU_INT_L */ + PAD_CFG_GPI_APIC(GPP_B0, NONE, DEEP), + /* B1 : CORE_VID1 ==> FPMCU_INT_L */ + PAD_CFG_GPI_ACPI_SCI(GPP_B1, 20K_PU, DEEP, INVERT), /* B11 : EXT_PWR_GATE# ==> PCH_FP_PWR_EN */ PAD_CFG_GPO(GPP_B11, 1, DEEP), /* B19 : GSPI1_CS# ==> PCH_SPI_FP_CS# */ @@ -421,14 +425,10 @@ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */ PAD_CFG_GPO(GPP_C3, 0, DEEP), - /* C8 : UART0_RXD ==> FPMCU_INT_L */ - PAD_CFG_GPI_APIC(GPP_C8, NONE, DEEP), /* C9 : UART0_TXD ==> FP_RST_ODL */ PAD_CFG_GPO(GPP_C9, 1, DEEP), /* D5 : ISH_I2C0_SDA ==> FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_D5, 0, DEEP), - /* D6 : ISH_I2C0_SCL ==> FPMCU_INT_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_D6, 20K_PU, DEEP, INVERT), /* D17 : DMIC_CLK1 ==> NC */ PAD_CFG_NC(GPP_D17), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/29872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Gerrit-Change-Number: 29872 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Update USB port info
by Patrick Georgi (Code Review) 03 Dec '18

03 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29912 ) Change subject: mb/google/fizz/variants/karma: Update USB port info ...................................................................... mb/google/fizz/variants/karma: Update USB port info Update USB port info according to the schematic file. BUG=none BRANCH=master TEST=Compiles successfully and boot on DUT. Change-Id: I7383b3d676fd7c775a6d749c70af65b28cf941eb Signed-off-by: David Wu <David_Wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29912 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/fizz/overridetree.cb M src/mainboard/google/fizz/variants/karma/overridetree.cb 3 files changed, 30 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 45997a9..cc48498 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -345,11 +345,6 @@ device usb 2.1 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Right"" - register "type" = "UPC_TYPE_A" - device usb 2.2 on end - end - chip drivers/usb/acpi register "desc" = ""USB2 Type-A Rear Right"" register "type" = "UPC_TYPE_A" device usb 2.4 on end @@ -375,11 +370,6 @@ device usb 3.1 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Right"" - register "type" = "UPC_TYPE_USB3_A" - device usb 3.2 on end - end - chip drivers/usb/acpi register "desc" = ""USB3 Type-A Rear Right"" register "type" = "UPC_TYPE_USB3_A" device usb 3.4 on end diff --git a/src/mainboard/google/fizz/variants/fizz/overridetree.cb b/src/mainboard/google/fizz/variants/fizz/overridetree.cb index 05d8a97..2b30905 100644 --- a/src/mainboard/google/fizz/variants/fizz/overridetree.cb +++ b/src/mainboard/google/fizz/variants/fizz/overridetree.cb @@ -8,11 +8,21 @@ chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right"" + register "type" = "UPC_TYPE_A" + device usb 2.2 on end + end + chip drivers/usb/acpi register "desc" = ""USB2 Type-A Front Left"" register "type" = "UPC_TYPE_A" device usb 2.3 on end end chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Right"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.2 on end + end + chip drivers/usb/acpi register "desc" = ""USB3 Type-A Front Left"" register "type" = "UPC_TYPE_USB3_A" device usb 3.3 on end diff --git a/src/mainboard/google/fizz/variants/karma/overridetree.cb b/src/mainboard/google/fizz/variants/karma/overridetree.cb index ee88352..0273f78 100644 --- a/src/mainboard/google/fizz/variants/karma/overridetree.cb +++ b/src/mainboard/google/fizz/variants/karma/overridetree.cb @@ -4,12 +4,17 @@ #+----------------+-------+-----------------------------------+ #| Device | Port# | Rev | #+----------------+-------+-----------------------------------+ + #| USB A Side | 3 | 2/3 | #| SD Card | 4 | | + #| Camera | 8 | | #| Touchsreen | 10 | | #+----------------+-------+-----------------------------------+ + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Side register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Card reader + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Touchscreen + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Side register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader register "psys_pmax" = "151" @@ -19,16 +24,31 @@ chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Side"" + register "type" = "UPC_TYPE_A" + device usb 2.2 on end + end + chip drivers/usb/acpi register "desc" = ""USB2 SD Card"" register "type" = "UPC_TYPE_INTERNAL" device usb 2.3 on end end chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.7 on end + end + chip drivers/usb/acpi register "desc" = ""USB2 Touchscreen"" register "type" = "UPC_TYPE_INTERNAL" device usb 2.9 on end end chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Side"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.2 on end + end + chip drivers/usb/acpi register "desc" = ""USB3 SD Card"" register "type" = "UPC_TYPE_INTERNAL" device usb 3.3 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/29912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7383b3d676fd7c775a6d749c70af65b28cf941eb Gerrit-Change-Number: 29912 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Disable native SD card controller
by Patrick Georgi (Code Review) 03 Dec '18

03 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29918 ) Change subject: mb/google/fizz/variants/karma: Disable native SD card controller ...................................................................... mb/google/fizz/variants/karma: Disable native SD card controller This change selects Kconfig option to disable native SD card controller in ACPI tables. BUG=b:119798840 BRANCH=master TEST=Compiles successfully and boot on DUT. Change-Id: I68dc9be511a370d882e4656c165efbe5dc6ee52e Signed-off-by: David Wu <David_Wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29918 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/fizz/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index e1fc38d..26f6f3a 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -11,6 +11,7 @@ select EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC + select EXCLUDE_NATIVE_SD_INTERFACE if BOARD_GOOGLE_KARMA select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT -- To view, visit https://review.coreboot.org/c/coreboot/+/29918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68dc9be511a370d882e4656c165efbe5dc6ee52e Gerrit-Change-Number: 29918 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: Untangle CBFS microcode updates
by Nico Huber (Code Review) 03 Dec '18

03 Dec '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29934 ) Change subject: Untangle CBFS microcode updates ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/29934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib403402e240d3531640a62ce93b7a93b4ef6ca5e Gerrit-Change-Number: 29934 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Dec 2018 13:05:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/lenovo: Add ThinkPad T431s
by Patrick Rudolph (Code Review) 03 Dec '18

03 Dec '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30021 ) Change subject: mainboard/lenovo: Add ThinkPad T431s ...................................................................... Patch Set 5: Please use the variants scheme and merge it with an existing board, like t430s -- To view, visit https://review.coreboot.org/c/coreboot/+/30021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a Gerrit-Change-Number: 30021 Gerrit-PatchSet: 5 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Mon, 03 Dec 2018 13:03:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/gm45: Make fetching the blc_pwm freq global
by Patrick Georgi (Code Review) 03 Dec '18

03 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29925 ) Change subject: nb/intel/gm45: Make fetching the blc_pwm freq global ...................................................................... nb/intel/gm45: Make fetching the blc_pwm freq global This can be used to select the proper VBT. Change-Id: Id3f6ba3ae31a5ab47f44d207678c1c4a6a43b7ec Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29925 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/gma.c 2 files changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 5373e5e..086afd5 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -442,6 +442,7 @@ int pwm_freq; /* In Hz */ }; int get_blc_values(const struct blc_pwm_t **entries); +u16 get_blc_pwm_freq_value(const char *edid_ascii_string); #if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 64b6a57..8acec29 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -668,7 +668,7 @@ return (blc_mod << 16) | blc_mod; } -static u16 get_blc_pwm_freq_value(const char *edid_ascii_string) +u16 get_blc_pwm_freq_value(const char *edid_ascii_string) { static u16 blc_pwm_freq; const struct blc_pwm_t *blc_pwm; -- To view, visit https://review.coreboot.org/c/coreboot/+/29925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3f6ba3ae31a5ab47f44d207678c1c4a6a43b7ec Gerrit-Change-Number: 29925 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: nb/intel/gm45: Make fetching the blc_pwm freq its own function
by Patrick Georgi (Code Review) 03 Dec '18

03 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29924 ) Change subject: nb/intel/gm45: Make fetching the blc_pwm freq its own function ...................................................................... nb/intel/gm45: Make fetching the blc_pwm freq its own function Also check the EDID string using strcmp instead of strncmp. Change-Id: I9ad364f84f3658be98ce7ad3a6f0f0fe3247fc41 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29924 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/northbridge/intel/gm45/gma.c 1 file changed, 36 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index b86e2b3..64b6a57 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -668,6 +668,39 @@ return (blc_mod << 16) | blc_mod; } +static u16 get_blc_pwm_freq_value(const char *edid_ascii_string) +{ + static u16 blc_pwm_freq; + const struct blc_pwm_t *blc_pwm; + int i; + int blc_array_len; + + if (blc_pwm_freq > 0) + return blc_pwm_freq; + + blc_array_len = get_blc_values(&blc_pwm); + /* Find EDID string and pwm freq in lookup table */ + for (i = 0; i < blc_array_len; i++) { + if (!strcmp(blc_pwm[i].ascii_string, edid_ascii_string)) { + blc_pwm_freq = blc_pwm[i].pwm_freq; + printk(BIOS_DEBUG, "Found EDID string: %s in lookup table, pwm: %dHz\n", + blc_pwm[i].ascii_string, blc_pwm_freq); + break; + } + } + + if (i == blc_array_len) + printk(BIOS_NOTICE, "Your panels EDID `%s` wasn't found in the" + "lookup table.\n You may have issues with your panels" + "backlight.\n If you want to help improving coreboot" + "please report: this EDID string\n and the result" + "of `intel_read read BLC_PWM_CTL`" + "(from intel-gpu-tools)\n while running vendor BIOS\n", + edid_ascii_string); + + return blc_pwm_freq; +} + static void gma_pm_init_post_vbios(struct device *const dev, const char *edid_ascii_string) { @@ -675,9 +708,7 @@ u32 reg32; u8 reg8; - const struct blc_pwm_t *blc_pwm; - int blc_array_len, i; - u16 pwm_freq = 0; + u16 pwm_freq; /* Setup Panel Power On Delays */ reg32 = gtt_read(PP_ON_DELAYS); @@ -708,30 +739,10 @@ reg8 = 100; if (conf->duty_cycle != 0) reg8 = conf->duty_cycle; - blc_array_len = get_blc_values(&blc_pwm); - if (conf->default_pwm_freq != 0) + pwm_freq = get_blc_pwm_freq_value(edid_ascii_string); + if (pwm_freq == 0 && conf->default_pwm_freq != 0) pwm_freq = conf->default_pwm_freq; - /* Find EDID string and pwm freq in lookup table */ - for (i = 0; i < blc_array_len; i++) { - if (!strncmp(blc_pwm[i].ascii_string, edid_ascii_string, - strlen(blc_pwm[i].ascii_string))) { - pwm_freq = blc_pwm[i].pwm_freq; - printk(BIOS_DEBUG, "Found EDID string: %s in lookup table, pwm: %dHz\n", - blc_pwm[i].ascii_string, pwm_freq); - break; - } - } - - if (i == blc_array_len) - printk(BIOS_NOTICE, "Your panels EDID `%s` wasn't found in the" - "lookup table.\n You may have issues with your panels" - "backlight.\n If you want to help improving coreboot" - "please report: this EDID string\n and the result" - "of `intel_read read BLC_PWM_CTL`" - "(from intel-gpu-tools)\n while running vendor BIOS\n", - edid_ascii_string); - if (pwm_freq == 0) gtt_write(BLC_PWM_CTL, 0x06100610); else -- To view, visit https://review.coreboot.org/c/coreboot/+/29924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad364f84f3658be98ce7ad3a6f0f0fe3247fc41 Gerrit-Change-Number: 29924 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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