build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 )
Change subject: src: Remove unused variables
......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/#/c/29917/15/src/cpu/amd/family_10h-family_15h/…
File src/cpu/amd/family_10h-family_15h/init_cpus.c:
https://review.coreboot.org/#/c/29917/15/src/cpu/amd/family_10h-family_15h/…
PS15, Line 1061: if ((get_option(&nvram, "cpu_c_states") == CB_SUCCESS) &&
line over 80 characters
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Hello Patrick Rudolph, Angel Pons, Huang Jin, Julius Werner, York Yang, Philipp Deppenwiese, build bot (Jenkins), Damien Zammit, David Guckian, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29917
to look at the new patch set (#15).
Change subject: src: Remove unused variables
......................................................................
src: Remove unused variables
Phase 1. fix 'unused variables' in order to enable Wunused.
Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/arch/arm64/boot.c
M src/cpu/amd/family_10h-family_15h/init_cpus.c
M src/cpu/amd/quadcore/quadcore.c
M src/device/dram/ddr3.c
M src/drivers/spi/sst.c
M src/lib/selfboot.c
M src/northbridge/amd/amdmct/mct/mct_d.c
M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/haswell/raminit.c
M src/northbridge/intel/pineview/early_init.c
M src/northbridge/intel/pineview/raminit.c
M src/northbridge/intel/x4x/dq_dqs.c
M src/northbridge/intel/x4x/early_init.c
M src/northbridge/via/vx900/raminit_ddr3.c
M src/soc/cavium/common/bootblock.c
M src/soc/intel/fsp_baytrail/romstage/romstage.c
M src/soc/intel/fsp_broadwell_de/acpi.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
M src/southbridge/amd/common/amd_pci_util.c
M src/southbridge/intel/fsp_rangeley/romstage.c
M src/southbridge/intel/i82371eb/fadt.c
22 files changed, 50 insertions(+), 85 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/15
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29979 )
Change subject: arch/x86/Kconfig: move MAX_REBOOT_CNT option
......................................................................
Patch Set 2:
>> Everything below the currently defined defaults is wrong.
>
> why are they wrong? I tested it with values below and it behaves
> like it should.
Tested on what board and tested how? With/without MRC cache might make
a difference for instance, plus there are about half a dozen of software
reset methods, which one was used?
Take modern Intel systems for instance. It's possible to reset the
CPU only, causing an INIT, the cores reset the x86 register state,
BSP restarts at the reset vector. Let's call it Reset#1. This is not
enough to rerun coreboot, though. Hence you'll usually find a 0x6 ->
0xcf9 reset (aka. system reset, still a warm reset) early in the
romstage: Reset#2. If no mrc.cache is present (bug or not) the raminit
will refuse to retrain on warm resets: 0xe -> 0xcf9 (full reset, goes
into S5 and back into S0 after a few seconds, hence a cold reset).
That'd be Reset#3.
So if MAX_REBOOT_CNT is < 3 and you hit the path described above, it
will run into fallback for no reason.
While that's the only path that comes to mind atm, there may be more
like that. If you can prove that a board doesn't have any valid path
with 3 resets, you can set MAX_REBOOT_CNT lower, and I won't call it
wrong ;)
>
>> In other words, this option was hidden on purpose. You can add another
>> option for instance and take the minimum of both or something like
>> that. But you mustn't lower it.
>
> An other option would be to adapt the range in the Kconfig or fix
> the issue which cause this wrong behavior.
What wrong behaviour?
The option has a misleading name. Maybe that's what causes the
confusion. What it actually represents should be something like
MAX_EXPECTED_RESET_COUNT_ON_A_SINGLE_REBOOT.
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 )
Change subject: src: Remove unused variables
......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/#/c/29917/14/src/southbridge/intel/fsp_rangeley…
File src/southbridge/intel/fsp_rangeley/romstage.c:
https://review.coreboot.org/#/c/29917/14/src/southbridge/intel/fsp_rangeley…
PS14, Line 123: printk(BIOS_DEBUG, "cbmem was initted\n");
> Is the cbmem_was_initted variable needed though? cbmem_recovery could be called from within the if() […]
that would also work
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29915 )
Change subject: mb/google/dragonegg: Don't use device_t
......................................................................
Patch Set 1: Code-Review+2
Can we add a checkpatch rule to prevent new occurrences of device_t ?
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29860 )
Change subject: nb/amd/pi/00{630F01,730F01}: Use ARRAY_SIZE
......................................................................
Patch Set 1: Code-Review+1
Where is this macro defined? AFAIK, the header it is in should be included.
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