coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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1699 discussions

Change in ...coreboot[master]: broadcom: Remove SoC and board support
by Philipp Deppenwiese (Code Review) 30 Nov '18

30 Nov '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29905 ) Change subject: broadcom: Remove SoC and board support ...................................................................... broadcom: Remove SoC and board support The reason for this code cleanup is the legacy Google Purin board which isn't available anymore and AFAIK never made it into the stores. * Remove broadcom cygnus SoC support * Remove /util/broadcom tool * Remove Google Purin mainboard * Remove MAINTAINERS entries Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/29905 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/util.md M MAINTAINERS M Makefile.inc D src/mainboard/google/purin/Kconfig D src/mainboard/google/purin/Kconfig.name D src/mainboard/google/purin/Makefile.inc D src/mainboard/google/purin/board_info.txt D src/mainboard/google/purin/boardid.c D src/mainboard/google/purin/bootblock.c D src/mainboard/google/purin/chromeos.c D src/mainboard/google/purin/chromeos.fmd D src/mainboard/google/purin/devicetree.cb D src/mainboard/google/purin/mainboard.c D src/mainboard/google/purin/memlayout.ld D src/mainboard/google/purin/reset.c D src/soc/broadcom/Kconfig D src/soc/broadcom/cygnus/Kconfig D src/soc/broadcom/cygnus/Makefile.inc D src/soc/broadcom/cygnus/bootblock.c D src/soc/broadcom/cygnus/cbmem.c D src/soc/broadcom/cygnus/ddr_init.c D src/soc/broadcom/cygnus/ddr_init_table.c D src/soc/broadcom/cygnus/gpio.c D src/soc/broadcom/cygnus/hw_init.c D src/soc/broadcom/cygnus/i2c.c D src/soc/broadcom/cygnus/include/soc/addressmap.h D src/soc/broadcom/cygnus/include/soc/config.h D src/soc/broadcom/cygnus/include/soc/cygnus.h D src/soc/broadcom/cygnus/include/soc/cygnus_types.h D src/soc/broadcom/cygnus/include/soc/ddr_bist.h D src/soc/broadcom/cygnus/include/soc/gpio.h D src/soc/broadcom/cygnus/include/soc/halapis/ddr_regs.h D src/soc/broadcom/cygnus/include/soc/hw_init.h D src/soc/broadcom/cygnus/include/soc/i2c.h D src/soc/broadcom/cygnus/include/soc/memlayout.ld D src/soc/broadcom/cygnus/include/soc/ns16550.h D src/soc/broadcom/cygnus/include/soc/reg_utils.h D src/soc/broadcom/cygnus/include/soc/sdram.h D src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h D src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_reg_access.h D src/soc/broadcom/cygnus/include/soc/shmoo_and28/shmoo_and28.h D src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h D src/soc/broadcom/cygnus/include/soc/tz.h D src/soc/broadcom/cygnus/iomux.c D src/soc/broadcom/cygnus/ns16550.c D src/soc/broadcom/cygnus/phy_reg_access.c D src/soc/broadcom/cygnus/romstage.c D src/soc/broadcom/cygnus/sdram.c D src/soc/broadcom/cygnus/shmoo_and28.c D src/soc/broadcom/cygnus/soc.c D src/soc/broadcom/cygnus/spi.c D src/soc/broadcom/cygnus/timer.c D src/soc/broadcom/cygnus/tz.c D src/soc/broadcom/cygnus/usb.c D src/soc/broadcom/cygnus/ydc_ddr_bist.c M util/README.md D util/broadcom/Makefile.inc D util/broadcom/description.md D util/broadcom/khmacsha256 D util/broadcom/secimage/Makefile D util/broadcom/secimage/Makefile.inc D util/broadcom/secimage/crypto.c D util/broadcom/secimage/io.c D util/broadcom/secimage/misc.c D util/broadcom/secimage/sbi.c D util/broadcom/secimage/secimage.h D util/broadcom/secimage/test/data/expected/binary.xxdump D util/broadcom/secimage/test/data/input/binary.xxdump D util/broadcom/secimage/test/data/input/configfile.xxdump D util/broadcom/secimage/test/data/input/hmac_binary_key.xxdump D util/broadcom/secimage/test/hmac.sh D util/broadcom/unauth.cfg M util/testing/Makefile.inc 73 files changed, 1 insertion(+), 29,729 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve -- To view, visit https://review.coreboot.org/c/coreboot/+/29905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a Gerrit-Change-Number: 29905 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: MAINTAINERS: Add myself as a maintainer
by Philipp Deppenwiese (Code Review) 30 Nov '18

30 Nov '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29913 ) Change subject: MAINTAINERS: Add myself as a maintainer ...................................................................... MAINTAINERS: Add myself as a maintainer Add myself as a maintainer for legacy Intel-based ChromeOS devices for which I provide coreboot images as a comminuty member, and as a maintainer for Purism devices in a professional capacity. Change-Id: I70df3b9e4e36c2e5d73f8888fe0ec220aa8a91b7 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/29913 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M MAINTAINERS 1 file changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/MAINTAINERS b/MAINTAINERS index ad94bc1..8ff21a8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -193,6 +193,20 @@ S: Supported F: src/mainboard/google/panther/ +GOOGLE MAINBOARDS (Intel-based, legacy/inactive) +M: Matt DeVillier <MrChromebox(a)gmail.com> +S: Maintained +F: src/mainboard/google/auron/ +F: src/mainboard/google/beltino/ +F: src/mainboard/google/butterfly/ +F: src/mainboard/google/cyan/ +F: src/mainboard/google/glados/ +F: src/mainboard/google/jecht/ +F: src/mainboard/google/link/ +F: src/mainboard/google/parrot/ +F: src/mainboard/google/slippy/ +F: src/mainboard/google/stout/ + OCP MAINBOARDS M: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> M: Patrick Rudolph <patrick.rudolph(a)9elements.com> @@ -207,6 +221,17 @@ F: src/mainboard/opencellular/rotundu/ F: src/mainboard/opencellular/elgon/ +PURISM MAINBOARDS +M: Matt DeVillier <matt.devillier(a)puri.sm> +S: Supported +F: src/mainboard/purism + +SAMSUNG CHROMEOS MAINBOARDS +M: Matt DeVillier <MrChromebox(a)gmail.com> +S: Maintained +F: src/mainboard/samsung/lumpy/ +F: src/mainboard/samsung/stumpy/ + INTEL MINNOWBOARD MAX MAINBOARD M: Huang Jin <huang.jin(a)intel.com> M: York Yang <york.yang(a)intel.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/29913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70df3b9e4e36c2e5d73f8888fe0ec220aa8a91b7 Gerrit-Change-Number: 29913 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: LinuxBoot: fix initramfs xz compression
by Philipp Deppenwiese (Code Review) 30 Nov '18

30 Nov '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29935 ) Change subject: LinuxBoot: fix initramfs xz compression ...................................................................... LinuxBoot: fix initramfs xz compression Add the flag '--check=crc32' to the xz compression to use CRC32 for the integrity check. The linux kernel does not support CRC64 for integrity checks, which is the default flag on most xz applications. Change-Id: I738bd99ef22aa053dc198df5595e1878069de13e Signed-off-by: Marcello Sylvester Bauer <info(a)marcellobauer.com> Reviewed-on: https://review.coreboot.org/c/29935 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M payloads/external/LinuxBoot/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index 8016095..a67b16a 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -39,7 +39,7 @@ initramfs_compressed: initramfs ifeq ($(CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ),y) - xz --keep --force --lzma2=dict=1MiB $(top)/$(CONFIG_LINUXBOOT_INITRAMFS) + xz --keep --force --check=crc32 --lzma2=dict=1MiB $(top)/$(CONFIG_LINUXBOOT_INITRAMFS) endif ifeq ($(CONFIG_LINUXBOOT_COMPILE_KERNEL),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/29935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I738bd99ef22aa053dc198df5595e1878069de13e Gerrit-Change-Number: 29935 Gerrit-PatchSet: 2 Gerrit-Owner: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: LinuxBoot: fix initramfs xz compression
by Philipp Deppenwiese (Code Review) 30 Nov '18

30 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29935 ) Change subject: LinuxBoot: fix initramfs xz compression ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I738bd99ef22aa053dc198df5595e1878069de13e Gerrit-Change-Number: 29935 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:24:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405 [temp]: Combine BB with QC-Sec for ROM boot
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29973 ) Change subject: qcs405 [temp]: Combine BB with QC-Sec for ROM boot ...................................................................... Patch Set 1: (39 comments) https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py File util/qualcomm/createxbl.py: https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@25 PS1, Line 25: # 09/04/15 et Added -x and -d to embed xbl_sec ELF trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@68 PS1, Line 68: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@84 PS1, Line 84: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@103 PS1, Line 103: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@113 PS1, Line 113: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@121 PS1, Line 121: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@144 PS1, Line 144: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@164 PS1, Line 164: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@172 PS1, Line 172: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@192 PS1, Line 192: header_format = 'reg' trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@223 PS1, Line 223: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@231 PS1, Line 231: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@232 PS1, Line 232: # Create hash table trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@235 PS1, Line 235: target_hash, trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@237 PS1, Line 237: secure_type = image_header_secflag) trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@245 PS1, Line 245: target_hash_hd, trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@254 PS1, Line 254: # Add the hash segment into the ELF trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@272 PS1, Line 272: def merge_elfs(env, trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@284 PS1, Line 284: mbn_tools.preprocess_elf_file(elf_in_file_name1) trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@289 PS1, Line 289: mbn_tools.preprocess_elf_file(elf_in_file_name2) trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@290 PS1, Line 290: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@294 PS1, Line 294: mbn_tools.preprocess_elf_file(elf_in_file_xbl_sec) trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@325 PS1, Line 325: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@364 PS1, Line 364: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@400 PS1, Line 400: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@477 PS1, Line 477: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@512 PS1, Line 512: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@614 PS1, Line 614: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@618 PS1, Line 618: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@621 PS1, Line 621: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@640 PS1, Line 640: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@674 PS1, Line 674: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@675 PS1, Line 675: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@681 PS1, Line 681: inp_data_offset = 0 trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@682 PS1, Line 682: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@689 PS1, Line 689: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@706 PS1, Line 706: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@708 PS1, Line 708: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/mbn_tools.py File util/qualcomm/mbn_tools.py: https://review.coreboot.org/#/c/29973/1/util/qualcomm/mbn_tools.py@1167 PS1, Line 1167: # Check if a shifting is required to accomodate for the hash segment. 'accomodate' may be misspelled - perhaps 'accommodate'? -- To view, visit https://review.coreboot.org/c/coreboot/+/29973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief4d92214cdc7ec06e90b0c7e73c11b6d6deddb9 Gerrit-Change-Number: 29973 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:17:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add blsp spi driver and enable SPI-NOR
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29968 ) Change subject: qcs405: Add blsp spi driver and enable SPI-NOR ...................................................................... Patch Set 1: (95 comments) https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/clock.c File src/soc/qualcomm/qcs405/clock.c: https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/clock.c@206 PS1, Line 206: clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/clock.c@206 PS1, Line 206: clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/clock.c@207 PS1, Line 207: REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/clock.c@207 PS1, Line 207: REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/clock.c@208 PS1, Line 208: BLSP2_AHB_CLK_ENA); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/clock.c@208 PS1, Line 208: BLSP2_AHB_CLK_ENA); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/qup.h: https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 161: unsigned clk_frequency; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 162: unsigned src_frequency; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 164: unsigned initialized; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 173: unsigned data_len; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 178: unsigned size; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c: https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@63 PS1, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@63 PS1, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@63 PS1, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@64 PS1, Line 64: /* BLSP5 registers for SPI interface */ code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@65 PS1, Line 65: { code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@65 PS1, Line 65: { please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@66 PS1, Line 66: BLSP5_SPI_CONFIG_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@66 PS1, Line 66: BLSP5_SPI_CONFIG_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@67 PS1, Line 67: BLSP5_SPI_IO_CONTROL_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@67 PS1, Line 67: BLSP5_SPI_IO_CONTROL_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@68 PS1, Line 68: BLSP5_SPI_ERROR_FLAGS_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@68 PS1, Line 68: BLSP5_SPI_ERROR_FLAGS_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@69 PS1, Line 69: BLSP5_SPI_ERROR_FLAGS_EN_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@69 PS1, Line 69: BLSP5_SPI_ERROR_FLAGS_EN_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@70 PS1, Line 70: BLSP5_QUP_CONFIG_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@70 PS1, Line 70: BLSP5_QUP_CONFIG_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@71 PS1, Line 71: BLSP5_QUP_ERROR_FLAGS_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@71 PS1, Line 71: BLSP5_QUP_ERROR_FLAGS_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@72 PS1, Line 72: BLSP5_QUP_ERROR_FLAGS_EN_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@72 PS1, Line 72: BLSP5_QUP_ERROR_FLAGS_EN_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@73 PS1, Line 73: BLSP5_QUP_OPERATIONAL_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@73 PS1, Line 73: BLSP5_QUP_OPERATIONAL_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@74 PS1, Line 74: BLSP5_QUP_IO_MODES_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@74 PS1, Line 74: BLSP5_QUP_IO_MODES_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@75 PS1, Line 75: BLSP5_QUP_STATE_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@75 PS1, Line 75: BLSP5_QUP_STATE_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@76 PS1, Line 76: BLSP5_QUP_INPUT_FIFOc_REG(0), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@76 PS1, Line 76: BLSP5_QUP_INPUT_FIFOc_REG(0), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@77 PS1, Line 77: BLSP5_QUP_OUTPUT_FIFOc_REG(0), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@77 PS1, Line 77: BLSP5_QUP_OUTPUT_FIFOc_REG(0), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@78 PS1, Line 78: BLSP5_QUP_MX_INPUT_COUNT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@78 PS1, Line 78: BLSP5_QUP_MX_INPUT_COUNT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@79 PS1, Line 79: BLSP5_QUP_MX_OUTPUT_COUNT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@79 PS1, Line 79: BLSP5_QUP_MX_OUTPUT_COUNT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@80 PS1, Line 80: BLSP5_QUP_SW_RESET_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@80 PS1, Line 80: BLSP5_QUP_SW_RESET_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@81 PS1, Line 81: 0, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@81 PS1, Line 81: 0, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@82 PS1, Line 82: 0, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@82 PS1, Line 82: 0, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@83 PS1, Line 83: BLSP5_QUP_OPERATIONAL_MASK, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@83 PS1, Line 83: BLSP5_QUP_OPERATIONAL_MASK, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@84 PS1, Line 84: BLSP5_SPI_DEASSERT_WAIT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@84 PS1, Line 84: BLSP5_SPI_DEASSERT_WAIT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@85 PS1, Line 85: }, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@85 PS1, Line 85: }, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@273 PS1, Line 273: SPI_IO_CTRL_NO_TRI_STATE | SPI_IO_CTRL_MX_CS_MODE); line over 80 characters https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@310 PS1, Line 310: switch(slave->bus) { switch and case should be at the same indent https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@310 PS1, Line 310: switch(slave->bus) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@311 PS1, Line 311: case 5: code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@311 PS1, Line 311: case 5: please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@313 PS1, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@313 PS1, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@313 PS1, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@314 PS1, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@314 PS1, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@314 PS1, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@315 PS1, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@315 PS1, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@315 PS1, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@316 PS1, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@316 PS1, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@316 PS1, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@318 PS1, Line 318: break; code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@318 PS1, Line 318: break; please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@319 PS1, Line 319: default: code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@320 PS1, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); line over 80 characters https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@320 PS1, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@320 PS1, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@321 PS1, Line 321: break; code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@321 PS1, Line 321: break; please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@322 PS1, Line 322: } code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@322 PS1, Line 322: } please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@354 PS1, Line 354: } void function return statements are not generally useful https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@428 PS1, Line 428: } void function return statements are not generally useful https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@684 PS1, Line 684: "or chipselect\n", bus); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@684 PS1, Line 684: "or chipselect\n", bus); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@713 PS1, Line 713: static int xfer_vectors(const struct spi_slave *slave, open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@714 PS1, Line 714: struct spi_op vectors[], size_t count) code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@714 PS1, Line 714: struct spi_op vectors[], size_t count) please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@715 PS1, Line 715: { please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@716 PS1, Line 716: return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@716 PS1, Line 716: return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@717 PS1, Line 717: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Gerrit-Change-Number: 29968 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:17:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: qclib: Add qclib support
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29967 ) Change subject: qclib: Add qclib support ...................................................................... Patch Set 1: (14 comments) https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… File src/soc/qualcomm/qcs405/qclib_execute.c: https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 35: int (*doit)(void *, void *); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 35: int (*doit)(void *, void *); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 43: struct prog pmic = code indent should use tabs where possible https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 43: struct prog pmic = please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 44: PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX PMIC_NAME); code indent should use tabs where possible https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 44: PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX PMIC_NAME); please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 52: if (prog_locate(&pmic)) code indent should use tabs where possible https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 52: if (prog_locate(&pmic)) please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 53: goto fail; code indent should use tabs where possible https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 53: goto fail; please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 55: if (cbfs_prog_stage_load(&pmic)) code indent should use tabs where possible https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 55: if (cbfs_prog_stage_load(&pmic)) please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 56: goto fail; code indent should use tabs where possible https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 56: goto fail; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:17:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: Coreboot: Add support for USB host mode for mistral platform
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29966 ) Change subject: Coreboot: Add support for USB host mode for mistral platform ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/#/c/29966/1/src/soc/qualcomm/qcs405/usb.c File src/soc/qualcomm/qcs405/usb.c: https://review.coreboot.org/#/c/29966/1/src/soc/qualcomm/qcs405/usb.c@137 PS1, Line 137: write8(&dwc3->usb2_phy_dig->override_x0, dwc3->board_data->parameter_override_x0); line over 80 characters https://review.coreboot.org/#/c/29966/1/src/soc/qualcomm/qcs405/usb.c@138 PS1, Line 138: write8(&dwc3->usb2_phy_dig->override_x1, dwc3->board_data->parameter_override_x1); line over 80 characters https://review.coreboot.org/#/c/29966/1/src/soc/qualcomm/qcs405/usb.c@139 PS1, Line 139: write8(&dwc3->usb2_phy_dig->override_x2, dwc3->board_data->parameter_override_x2); line over 80 characters https://review.coreboot.org/#/c/29966/1/src/soc/qualcomm/qcs405/usb.c@140 PS1, Line 140: write8(&dwc3->usb2_phy_dig->override_x3, dwc3->board_data->parameter_override_x3); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Gerrit-Change-Number: 29966 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:16:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: qcs405: Add blsp uart driver
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29964 ) Change subject: qcs405: Add blsp uart driver ...................................................................... Patch Set 1: (25 comments) https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/cdp.h: https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 36: unsigned smem_get_board_machtype(void); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 89: SPI_CS_0 , space prohibited before that ',' (ctx:WxE) https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 119: unsigned count; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 124: unsigned base; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 126: unsigned is_macsec; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 127: unsigned mac_pwr0; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 128: unsigned mac_pwr1; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 129: unsigned mac_conn_to_phy; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 172: unsigned int get_board_index(unsigned machid); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 173: void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/iomap.h: https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 49: #define writel_i(v,a) write32((void *)a, v) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c File src/soc/qualcomm/qcs405/uart.c: https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@50 PS1, Line 50: unsigned blsp_uart; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@54 PS1, Line 54: void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count) Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@56 PS1, Line 56: int i; code indent should use tabs where possible https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@56 PS1, Line 56: int i; please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@58 PS1, Line 58: for (i = 0; i < count; i++) { code indent should use tabs where possible https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@58 PS1, Line 58: for (i = 0; i < count; i++) { please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@59 PS1, Line 59: gpio_configure(gpio->gpio, gpio->func, code indent should use tabs where possible https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@59 PS1, Line 59: gpio_configure(gpio->gpio, gpio->func, please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@60 PS1, Line 60: gpio->pull, gpio->drvstr, gpio->enable); code indent should use tabs where possible https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@60 PS1, Line 60: gpio->pull, gpio->drvstr, gpio->enable); please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@61 PS1, Line 61: gpio++; code indent should use tabs where possible https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@61 PS1, Line 61: gpio++; please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@62 PS1, Line 62: } code indent should use tabs where possible https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@62 PS1, Line 62: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Gerrit-Change-Number: 29964 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:16:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405:Add SPI_RAM_SIMULATION support for QCS405
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29959 ) Change subject: qcs405:Add SPI_RAM_SIMULATION support for QCS405 ...................................................................... Patch Set 1: (6 comments) https://review.coreboot.org/#/c/29959/1/src/soc/qualcomm/qcs405/flash_contr… File src/soc/qualcomm/qcs405/flash_controller.c: https://review.coreboot.org/#/c/29959/1/src/soc/qualcomm/qcs405/flash_contr… PS1, Line 37: static int ram_read(const struct spi_flash *flash, u32 addr, size_t len, void *buf) line over 80 characters https://review.coreboot.org/#/c/29959/1/src/soc/qualcomm/qcs405/flash_contr… PS1, Line 68: { that open brace { should be on the previous line https://review.coreboot.org/#/c/29959/1/src/soc/qualcomm/qcs405/flash_contr… PS1, Line 78: static char name[] = "ram_flash"; static char array declaration should probably be static const char https://review.coreboot.org/#/c/29959/1/src/soc/qualcomm/qcs405/flash_contr… PS1, Line 80: printk(BIOS_INFO, "[%s]..CONFIG_QC_SOC_SIMULATE\n", __FUNCTION__); __func__ should be used instead of gcc specific __FUNCTION__ https://review.coreboot.org/#/c/29959/1/src/soc/qualcomm/qcs405/flash_contr… PS1, Line 82: printk(BIOS_INFO, "[%s]..ram_flash\n", __FUNCTION__); __func__ should be used instead of gcc specific __FUNCTION__ https://review.coreboot.org/#/c/29959/1/src/soc/qualcomm/qcs405/mmu.c File src/soc/qualcomm/qcs405/mmu.c: https://review.coreboot.org/#/c/29959/1/src/soc/qualcomm/qcs405/mmu.c@40 PS1, Line 40: mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_NS | MA_RW); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I895315a995cbbd5e6a7a305e48476f0d0f583cfe Gerrit-Change-Number: 29959 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:15:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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