coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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1699 discussions

Change in ...coreboot[master]: src: Remove not used variable
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

Hello Patrick Rudolph, Huang Jin, Julius Werner, Angel Pons, York Yang, Philipp Deppenwiese, build bot (Jenkins), Damien Zammit, David Guckian, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#8). Change subject: src: Remove not used variable ...................................................................... src: Remove not used variable Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm64/boot.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/device/dram/ddr3.c M src/drivers/spi/sst.c M src/lib/selfboot.c M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/via/vx900/raminit_ddr3.c M src/soc/cavium/common/bootblock.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/soc/intel/quark/i2c.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/i82371eb/fadt.c 19 files changed, 21 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 8 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: arch/x86/Kconfig: move MAX_REBOOT_CNT option
by Nico Huber (Code Review) 30 Nov '18

30 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29979 ) Change subject: arch/x86/Kconfig: move MAX_REBOOT_CNT option ...................................................................... Patch Set 1: (2 comments) The current per platform defaults should be enforced as minimum, it won't work reliable otherwise because some reboots triggered by coreboot itself are expected. https://review.coreboot.org/#/c/29979/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29979/1//COMMIT_MSG@11 PS1, Line 11: Use case? What does it fix? https://review.coreboot.org/#/c/29979/1/src/arch/x86/Kconfig File src/arch/x86/Kconfig: https://review.coreboot.org/#/c/29979/1/src/arch/x86/Kconfig@274 PS1, Line 274: 0 0 would mean every boot has failed? Never use the normal path? -- To view, visit https://review.coreboot.org/c/coreboot/+/29979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice26e2ef349f1172b564edc14f1012c33546a93c Gerrit-Change-Number: 29979 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 30 Nov 2018 15:03:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove not used variable
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove not used variable ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/#/c/29917/7/src/cpu/amd/family_10h-family_15h/i… File src/cpu/amd/family_10h-family_15h/init_cpus.c: https://review.coreboot.org/#/c/29917/7/src/cpu/amd/family_10h-family_15h/i… PS7, Line 1062: if (!!nvram) { suspect code indent for conditional statements (32, 32) -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 7 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 14:57:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/lynxpoint: Allow the flash chip to be write-protected
by Nico Huber (Code Review) 30 Nov '18

30 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29977 ) Change subject: sb/intel/lynxpoint: Allow the flash chip to be write-protected ...................................................................... Patch Set 1: > While technically correct I don't see why we need to duplicate code and > Kconfig options. Can you move the bd82x6x code to sb/intel/common and > just use that instead ? +1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2 Gerrit-Change-Number: 29977 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 14:56:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove not used variable
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

Hello Patrick Rudolph, Julius Werner, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#7). Change subject: src: Remove not used variable ...................................................................... src: Remove not used variable Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm64/boot.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/device/dram/ddr3.c M src/drivers/spi/sst.c M src/lib/selfboot.c M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/via/vx900/raminit_ddr3.c M src/soc/cavium/common/bootblock.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/soc/intel/quark/i2c.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/i82371eb/fadt.c 19 files changed, 22 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 7 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: Documentation: gerrit guidelines: Adopt the new topic syntax
by Jonathan Neuschäfer (Code Review) 30 Nov '18

30 Nov '18

Jonathan Neuschäfer has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/29983 ) Change subject: Documentation: gerrit guidelines: Adopt the new topic syntax ...................................................................... Documentation: gerrit guidelines: Adopt the new topic syntax When the old syntax is used, gerrit now respends with: remote: WARNING: deprecated topic syntax. Use %topic=TOPIC instead Change-Id: I002bfc3e9c4b348379337bc386d3bdefb307679d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M Documentation/getting_started/gerrit_guidelines.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/29983/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I002bfc3e9c4b348379337bc386d3bdefb307679d Gerrit-Change-Number: 29983 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: Documentation: gerrit guidelines: Adopt the new topic syntax
by Jonathan Neuschäfer (Code Review) 30 Nov '18

30 Nov '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29983 Change subject: Documentation: gerrit guidelines: Adopt the new topic syntax ...................................................................... Documentation: gerrit guidelines: Adopt the new topic syntax Change-Id: I002bfc3e9c4b348379337bc386d3bdefb307679d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M Documentation/getting_started/gerrit_guidelines.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/29983/1 diff --git a/Documentation/getting_started/gerrit_guidelines.md b/Documentation/getting_started/gerrit_guidelines.md index 9210c84..77edaf2 100644 --- a/Documentation/getting_started/gerrit_guidelines.md +++ b/Documentation/getting_started/gerrit_guidelines.md @@ -151,7 +151,7 @@ the patch and clicking on the icon next to the topic line. Topics can also be set when you push the patches into gerrit. For example, to push a set of commits with the the i915-kernel-x60 set, use the command: - git push origin HEAD:refs/for/master/i915-kernel-x60 + git push origin HEAD:refs/for/master%topic=i915-kernel-x60 * If one of your patches isn't ready to be merged, make sure it's obvious that you don't feel it's ready for merge yet. The preferred way to show -- To view, visit https://review.coreboot.org/c/coreboot/+/29983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I002bfc3e9c4b348379337bc386d3bdefb307679d Gerrit-Change-Number: 29983 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qcs405 [temp]: Combine BB with QC-Sec for ROM boot
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29973 ) Change subject: qcs405 [temp]: Combine BB with QC-Sec for ROM boot ...................................................................... Patch Set 2: (39 comments) https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py File util/qualcomm/createxbl.py: https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@25 PS2, Line 25: # 09/04/15 et Added -x and -d to embed xbl_sec ELF trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@68 PS2, Line 68: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@84 PS2, Line 84: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@103 PS2, Line 103: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@113 PS2, Line 113: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@121 PS2, Line 121: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@144 PS2, Line 144: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@164 PS2, Line 164: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@172 PS2, Line 172: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@192 PS2, Line 192: header_format = 'reg' trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@223 PS2, Line 223: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@231 PS2, Line 231: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@232 PS2, Line 232: # Create hash table trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@235 PS2, Line 235: target_hash, trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@237 PS2, Line 237: secure_type = image_header_secflag) trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@245 PS2, Line 245: target_hash_hd, trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@254 PS2, Line 254: # Add the hash segment into the ELF trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@272 PS2, Line 272: def merge_elfs(env, trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@284 PS2, Line 284: mbn_tools.preprocess_elf_file(elf_in_file_name1) trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@289 PS2, Line 289: mbn_tools.preprocess_elf_file(elf_in_file_name2) trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@290 PS2, Line 290: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@294 PS2, Line 294: mbn_tools.preprocess_elf_file(elf_in_file_xbl_sec) trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@325 PS2, Line 325: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@364 PS2, Line 364: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@400 PS2, Line 400: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@477 PS2, Line 477: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@512 PS2, Line 512: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@614 PS2, Line 614: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@618 PS2, Line 618: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@621 PS2, Line 621: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@640 PS2, Line 640: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@674 PS2, Line 674: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@675 PS2, Line 675: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@681 PS2, Line 681: inp_data_offset = 0 trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@682 PS2, Line 682: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@689 PS2, Line 689: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@706 PS2, Line 706: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@708 PS2, Line 708: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/mbn_tools.py File util/qualcomm/mbn_tools.py: https://review.coreboot.org/#/c/29973/2/util/qualcomm/mbn_tools.py@1167 PS2, Line 1167: # Check if a shifting is required to accomodate for the hash segment. 'accomodate' may be misspelled - perhaps 'accommodate'? -- To view, visit https://review.coreboot.org/c/coreboot/+/29973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief4d92214cdc7ec06e90b0c7e73c11b6d6deddb9 Gerrit-Change-Number: 29973 Gerrit-PatchSet: 2 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Fri, 30 Nov 2018 14:09:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add blsp spi driver and enable SPI-NOR
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29968 ) Change subject: qcs405: Add blsp spi driver and enable SPI-NOR ...................................................................... Patch Set 2: (95 comments) https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/clock.c File src/soc/qualcomm/qcs405/clock.c: https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/clock.c@206 PS2, Line 206: clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/clock.c@206 PS2, Line 206: clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/clock.c@207 PS2, Line 207: REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/clock.c@207 PS2, Line 207: REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/clock.c@208 PS2, Line 208: BLSP2_AHB_CLK_ENA); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/clock.c@208 PS2, Line 208: BLSP2_AHB_CLK_ENA); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/qup.h: https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 161: unsigned clk_frequency; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 162: unsigned src_frequency; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 164: unsigned initialized; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 173: unsigned data_len; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 178: unsigned size; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c: https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@63 PS2, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@63 PS2, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@63 PS2, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@64 PS2, Line 64: /* BLSP5 registers for SPI interface */ code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@65 PS2, Line 65: { code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@65 PS2, Line 65: { please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@66 PS2, Line 66: BLSP5_SPI_CONFIG_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@66 PS2, Line 66: BLSP5_SPI_CONFIG_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@67 PS2, Line 67: BLSP5_SPI_IO_CONTROL_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@67 PS2, Line 67: BLSP5_SPI_IO_CONTROL_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@68 PS2, Line 68: BLSP5_SPI_ERROR_FLAGS_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@68 PS2, Line 68: BLSP5_SPI_ERROR_FLAGS_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@69 PS2, Line 69: BLSP5_SPI_ERROR_FLAGS_EN_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@69 PS2, Line 69: BLSP5_SPI_ERROR_FLAGS_EN_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@70 PS2, Line 70: BLSP5_QUP_CONFIG_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@70 PS2, Line 70: BLSP5_QUP_CONFIG_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@71 PS2, Line 71: BLSP5_QUP_ERROR_FLAGS_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@71 PS2, Line 71: BLSP5_QUP_ERROR_FLAGS_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@72 PS2, Line 72: BLSP5_QUP_ERROR_FLAGS_EN_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@72 PS2, Line 72: BLSP5_QUP_ERROR_FLAGS_EN_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@73 PS2, Line 73: BLSP5_QUP_OPERATIONAL_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@73 PS2, Line 73: BLSP5_QUP_OPERATIONAL_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@74 PS2, Line 74: BLSP5_QUP_IO_MODES_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@74 PS2, Line 74: BLSP5_QUP_IO_MODES_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@75 PS2, Line 75: BLSP5_QUP_STATE_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@75 PS2, Line 75: BLSP5_QUP_STATE_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@76 PS2, Line 76: BLSP5_QUP_INPUT_FIFOc_REG(0), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@76 PS2, Line 76: BLSP5_QUP_INPUT_FIFOc_REG(0), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@77 PS2, Line 77: BLSP5_QUP_OUTPUT_FIFOc_REG(0), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@77 PS2, Line 77: BLSP5_QUP_OUTPUT_FIFOc_REG(0), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@78 PS2, Line 78: BLSP5_QUP_MX_INPUT_COUNT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@78 PS2, Line 78: BLSP5_QUP_MX_INPUT_COUNT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@79 PS2, Line 79: BLSP5_QUP_MX_OUTPUT_COUNT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@79 PS2, Line 79: BLSP5_QUP_MX_OUTPUT_COUNT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@80 PS2, Line 80: BLSP5_QUP_SW_RESET_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@80 PS2, Line 80: BLSP5_QUP_SW_RESET_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@81 PS2, Line 81: 0, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@81 PS2, Line 81: 0, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@82 PS2, Line 82: 0, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@82 PS2, Line 82: 0, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@83 PS2, Line 83: BLSP5_QUP_OPERATIONAL_MASK, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@83 PS2, Line 83: BLSP5_QUP_OPERATIONAL_MASK, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@84 PS2, Line 84: BLSP5_SPI_DEASSERT_WAIT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@84 PS2, Line 84: BLSP5_SPI_DEASSERT_WAIT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@85 PS2, Line 85: }, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@85 PS2, Line 85: }, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@273 PS2, Line 273: SPI_IO_CTRL_NO_TRI_STATE | SPI_IO_CTRL_MX_CS_MODE); line over 80 characters https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@310 PS2, Line 310: switch(slave->bus) { switch and case should be at the same indent https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@310 PS2, Line 310: switch(slave->bus) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@311 PS2, Line 311: case 5: code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@311 PS2, Line 311: case 5: please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@313 PS2, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@313 PS2, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@313 PS2, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@314 PS2, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@314 PS2, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@314 PS2, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@315 PS2, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@315 PS2, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@315 PS2, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@316 PS2, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@316 PS2, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@316 PS2, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@318 PS2, Line 318: break; code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@318 PS2, Line 318: break; please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@319 PS2, Line 319: default: code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@320 PS2, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); line over 80 characters https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@320 PS2, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@320 PS2, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@321 PS2, Line 321: break; code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@321 PS2, Line 321: break; please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@322 PS2, Line 322: } code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@322 PS2, Line 322: } please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@354 PS2, Line 354: } void function return statements are not generally useful https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@428 PS2, Line 428: } void function return statements are not generally useful https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@684 PS2, Line 684: "or chipselect\n", bus); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@684 PS2, Line 684: "or chipselect\n", bus); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@713 PS2, Line 713: static int xfer_vectors(const struct spi_slave *slave, open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@714 PS2, Line 714: struct spi_op vectors[], size_t count) code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@714 PS2, Line 714: struct spi_op vectors[], size_t count) please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@715 PS2, Line 715: { please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@716 PS2, Line 716: return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@716 PS2, Line 716: return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@717 PS2, Line 717: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Gerrit-Change-Number: 29968 Gerrit-PatchSet: 2 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Fri, 30 Nov 2018 14:08:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qclib: Add qclib support
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29967 ) Change subject: qclib: Add qclib support ...................................................................... Patch Set 2: (14 comments) https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… File src/soc/qualcomm/qcs405/qclib_execute.c: https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 35: int (*doit)(void *, void *); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 35: int (*doit)(void *, void *); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 43: struct prog pmic = code indent should use tabs where possible https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 43: struct prog pmic = please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 44: PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX PMIC_NAME); code indent should use tabs where possible https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 44: PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX PMIC_NAME); please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 52: if (prog_locate(&pmic)) code indent should use tabs where possible https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 52: if (prog_locate(&pmic)) please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 53: goto fail; code indent should use tabs where possible https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 53: goto fail; please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 55: if (cbfs_prog_stage_load(&pmic)) code indent should use tabs where possible https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 55: if (cbfs_prog_stage_load(&pmic)) please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 56: goto fail; code indent should use tabs where possible https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 56: goto fail; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 2 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Fri, 30 Nov 2018 14:08:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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