coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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1699 discussions

Change in ...coreboot[master]: src: Remove not used variable
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

Hello Patrick Rudolph, Julius Werner, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#6). Change subject: src: Remove not used variable ...................................................................... src: Remove not used variable Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm64/boot.c M src/device/dram/ddr3.c M src/drivers/spi/sst.c M src/lib/selfboot.c M src/northbridge/intel/haswell/raminit.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/intel/i82371eb/fadt.c 7 files changed, 6 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group
by Ren Kuo (Code Review) 30 Nov '18

30 Nov '18

Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29872 ) Change subject: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group ...................................................................... Patch Set 2: Code-Review+1 my test result is same as shelley now by correct the HW re-work Would you help to +2 ? We need it to build the EVT -- To view, visit https://review.coreboot.org/c/coreboot/+/29872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Gerrit-Change-Number: 29872 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Fri, 30 Nov 2018 13:05:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Crash Test
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

HAOUAS Elyes has restored this change. ( https://review.coreboot.org/c/coreboot/+/29926 ) Change subject: Crash Test ...................................................................... Restored for test -- To view, visit https://review.coreboot.org/c/coreboot/+/29926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Gerrit-Change-Number: 29926 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: restore

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Change in ...coreboot[master]: broadcom: Remove SoC and board support
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29905 ) Change subject: broadcom: Remove SoC and board support ...................................................................... Patch Set 4: maybe a missing file: payloads/libpayload/configs/config.purin ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a Gerrit-Change-Number: 29905 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 30 Nov 2018 12:34:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/braswell: Remove disabled LPE acpi code
by Frans Hendriks (Code Review) 30 Nov '18

30 Nov '18

Hello Patrick Rudolph, build bot (Jenkins), Hannah Williams, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29414 to look at the new patch set (#4). Change subject: src/soc/intel/braswell: Remove disabled LPE acpi code ...................................................................... src/soc/intel/braswell: Remove disabled LPE acpi code The ACPI code for LPE device was included regardless of the availability of the LPE controller. Move the LPE ACPI code to seperate SSDT and hide it when LPE is disabled. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/google/cyan/Makefile.inc M src/mainboard/google/cyan/acpi/codec_maxim.asl M src/mainboard/google/cyan/acpi/codec_realtek.asl A src/mainboard/google/cyan/acpi/jack_board.asl A src/mainboard/google/cyan/acpi/jack_detect.asl A src/mainboard/google/cyan/ssdtlpe.asl A src/mainboard/google/cyan/variants/banon/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/celes/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/cyan/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/edgar/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/kefka/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/reks/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/relm/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/setzer/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/terra/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/ultima/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/lpe.asl M src/mainboard/intel/strago/Makefile.inc M src/mainboard/intel/strago/acpi/mainboard.asl A src/mainboard/intel/strago/ssdtlpe.asl M src/soc/intel/braswell/acpi/southcluster.asl M src/soc/intel/braswell/include/soc/acpi.h M src/soc/intel/braswell/lpe.c 23 files changed, 393 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/29414/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Gerrit-Change-Number: 29414 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: arch/x86/Kconfig: move MAX_REBOOT_CNT option
by Marcello Sylvester Bauer (Code Review) 30 Nov '18

30 Nov '18

Marcello Sylvester Bauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29979 Change subject: arch/x86/Kconfig: move MAX_REBOOT_CNT option ...................................................................... arch/x86/Kconfig: move MAX_REBOOT_CNT option Move the MAX_REBOOT_CNT option to arch/x86/Kconfig, to make it in the menuconfig reachable. This simplifies the change of this option. Change-Id: Ice26e2ef349f1172b564edc14f1012c33546a93c Signed-off-by: Marcello Sylvester Bauer <info(a)marcellobauer.com> --- M src/Kconfig M src/arch/x86/Kconfig 2 files changed, 10 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/29979/1 diff --git a/src/Kconfig b/src/Kconfig index 62a7a92..812e83e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1085,14 +1085,6 @@ help Internal option that controls whether we compile in register scripts. -config MAX_REBOOT_CNT - int - default 3 - help - Internal option that sets the maximum number of bootblock executions allowed - with the normal image enabled before assuming the normal image is defective - and switching to the fallback image. - config CREATE_BOARD_CHECKLIST bool default n diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 7c8371e..0bbd0b0 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -268,6 +268,16 @@ default "bootblock_simple.c" if BOOTBLOCK_SIMPLE default "bootblock_normal.c" if BOOTBLOCK_NORMAL +config MAX_REBOOT_CNT + int "Max reboot count" + default 3 + range 0 15 + depends on BOOTBLOCK_NORMAL + help + Sets the maximum number of bootblock executions allowed with the + normal image enabled before assuming the normal image is defective + and switching to the fallback image. + config SKIP_MAX_REBOOT_CNT_CLEAR bool "Do not clear reboot count after successful boot" depends on BOOTBLOCK_NORMAL -- To view, visit https://review.coreboot.org/c/coreboot/+/29979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice26e2ef349f1172b564edc14f1012c33546a93c Gerrit-Change-Number: 29979 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cbmem: Enable AArch64 support
by Ádám Kallai (Code Review) 30 Nov '18

30 Nov '18

Ádám Kallai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29978 Change subject: cbmem: Enable AArch64 support ...................................................................... cbmem: Enable AArch64 support TEST=on Chromebook Kevin with 64bit userland, it works well. Change-Id: If16065000214c6cff9c14a14c5b5f44faca38153 Signed-off-by: Adam Kallai <kadam(a)inf.u-szeged.hu> --- M util/cbmem/cbmem.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/29978/1 diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 90ad55e..8e73d9c 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -1123,7 +1123,7 @@ exit(exit_code); } -#ifdef __arm__ +#if defined(__arm__) || defined(__aarch64__) static void dt_update_cells(const char *name, int *addr_cells_ptr, int *size_cells_ptr) { @@ -1236,7 +1236,7 @@ closedir(dir); return ret; } -#endif /* __arm__ */ +#endif /* defined(__arm__) || defined(__aarch64__) */ int main(int argc, char** argv) { @@ -1339,7 +1339,7 @@ return 1; } -#ifdef __arm__ +#if defined(__arm__) || defined(__aarch64__) int addr_cells, size_cells; char *coreboot_node = dt_find_compat("/proc/device-tree", "coreboot", &addr_cells, &size_cells); -- To view, visit https://review.coreboot.org/c/coreboot/+/29978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If16065000214c6cff9c14a14c5b5f44faca38153 Gerrit-Change-Number: 29978 Gerrit-PatchSet: 1 Gerrit-Owner: Ádám Kallai <kadam(a)inf.u-szeged.hu> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Enable melf touchscreen
by Chris Zhou (Code Review) 30 Nov '18

30 Nov '18

Chris Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29830 ) Change subject: mb/google/sarien/variants/sarien: Enable melf touchscreen ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29830/2/src/mainboard/google/sarien/variant… File src/mainboard/google/sarien/variants/sarien/devicetree.cb: https://review.coreboot.org/#/c/29830/2/src/mainboard/google/sarien/variant… PS2, Line 124: GPP_B13 > There does not seem to be a dedicated touchscreen reset pin, this is PLTRST and doesn't seem like wh […] According schematic, the reset_gpio is connected with PLTRST. Please see issue 119799550 #5(https://partnerissuetracker.corp.google.com/issues/119799550#comment5). -- To view, visit https://review.coreboot.org/c/coreboot/+/29830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926c988c141628ae2d98206f9eb615d06357a366 Gerrit-Change-Number: 29830 Gerrit-PatchSet: 2 Gerrit-Owner: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:43:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/vboot: Fix remaining measured boot issues
by Philipp Deppenwiese (Code Review) 30 Nov '18

30 Nov '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29840 ) Change subject: security/vboot: Fix remaining measured boot issues ...................................................................... security/vboot: Fix remaining measured boot issues Makes vboot measured boot mode available for all boards. * Increase Tegra210 and Rockchip3228 SRAM for romstage/verstage. * Add missing files for Intel apollolake and AMD stoneyridge as TPM driver target. Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/29840 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/soc/amd/stoneyridge/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld 4 files changed, 14 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Julius Werner: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index c54b652..a53984e 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -87,6 +87,7 @@ postcar-y += ramtop.c postcar-y += sb_util.c postcar-y += nb_util.c +postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c ramstage-y += BiosCallOuts.c ramstage-y += i2c.c diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 6168f86..19ebe7c 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -75,6 +75,7 @@ postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c postcar-$(CONFIG_UART_DEBUG) += uart.c +postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += gspi.c verstage-y += car.c verstage-y += i2c.c diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index c1c581b..d807c06 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -28,18 +28,18 @@ SECTIONS { SRAM_START(0x40000000) - PRERAM_CBMEM_CONSOLE(0x40000000, 8K) - PRERAM_CBFS_CACHE(0x40002000, 36K) - VBOOT2_WORK(0x4000B000, 12K) + PRERAM_CBMEM_CONSOLE(0x40000000, 4K) + PRERAM_CBFS_CACHE(0x40001000, 36K) + VBOOT2_WORK(0x4000A000, 12K) #if ENV_ARM64 - STACK(0x4000E000, 3K) + STACK(0x4000D000, 3K) #else /* AVP gets a separate stack to avoid any chance of handoff races. */ - STACK(0x4000EC00, 3K) + STACK(0x4000DC00, 3K) #endif - TIMESTAMP(0x4000F800, 2K) - BOOTBLOCK(0x40010000, 28K) - VERSTAGE(0x40017000, 64K) - ROMSTAGE(0x40027000, 100K) + TIMESTAMP(0x4000E800, 2K) + BOOTBLOCK(0x4000F000, 28K) + VERSTAGE(0x40016000, 64K) + ROMSTAGE(0x40026000, 104K) SRAM_END(0x40040000) DRAM_START(0x80000000) diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index fc3758b..6320fad 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -31,9 +31,9 @@ SRAM_START(0xFF700000) TTB(0xFF700000, 16K) BOOTBLOCK(0xFF704004, 20K - 4) - PRERAM_CBMEM_CONSOLE(0xFF709000, 3K) - VBOOT2_WORK(0xFF709C00, 12K) - OVERLAP_VERSTAGE_ROMSTAGE(0xFF70CC00, 41K) + PRERAM_CBMEM_CONSOLE(0xFF709000, 2K) + VBOOT2_WORK(0xFF709800, 12K) + OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 42K) PRERAM_CBFS_CACHE(0xFF717000, 1K) TIMESTAMP(0xFF717400, 0x180) STACK(0xFF717580, 3K - 0x180) -- To view, visit https://review.coreboot.org/c/coreboot/+/29840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Gerrit-Change-Number: 29840 Gerrit-PatchSet: 18 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: cpu/intel/fsp_model_406dx: Drop dead microcode reference
by David Guckian (Code Review) 30 Nov '18

30 Nov '18

David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29931 ) Change subject: cpu/intel/fsp_model_406dx: Drop dead microcode reference ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia724262a526fe960c17ae4b248acfa42fc342331 Gerrit-Change-Number: 29931 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:26:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2018