coreboot-gerrit November 2018

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Change in ...coreboot[master]: qcs405: memlayout: Make bootblock 64k aligned
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29969 Change subject: qcs405: memlayout: Make bootblock 64k aligned ...................................................................... qcs405: memlayout: Make bootblock 64k aligned The qc_sec in qcs405 excepts that bootblock to be 64k aligned. So adjust the memlayout accordingly. Change-Id: I1599242bb5158477318867508c72dc14f1244b00 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/arch/arm64/armv8/bootblock.S M src/soc/qualcomm/qcs405/include/soc/memlayout.ld 2 files changed, 15 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29969/1 diff --git a/src/arch/arm64/armv8/bootblock.S b/src/arch/arm64/armv8/bootblock.S index e5758bc..7dc8b0f 100644 --- a/src/arch/arm64/armv8/bootblock.S +++ b/src/arch/arm64/armv8/bootblock.S @@ -23,7 +23,9 @@ ENTRY(_start) /* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */ - bl arm64_init_cpu + ldr x15, =arm64_init_cpu + blr x15 - bl main + ldr x15, =main + blr x15 ENDPROC(_start) diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index dadbbe8..8566f9f 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -31,17 +31,17 @@ BSRAM_START(0x8C00000) REGION(fw_reserved2, 0x8C00000, 0x16000, 4096) - OVERLAP_VERSTAGE_ROMSTAGE(0x8C16000, 100K) - BOOTBLOCK(0x8C2F000, 40K) - TTB(0x8C39000, 56K) - VBOOT2_WORK(0x8C47000, 16K) - STACK(0x8C4B000, 16K) - TIMESTAMP(0x8C4F000, 1K) - PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K) - PRERAM_CBFS_CACHE(0x8C57400, 70K) - //REGION(bsram_unused, 0x8C68C00, 0xA2400, 0x100) - REGION(qclib, 0x8C69000, 0x80000, 4096) - REGION(dcb, 0x8CE9000, 0x4000, 4096) + OVERLAP_VERSTAGE_ROMSTAGE(0x8C16000, 104K) + BOOTBLOCK(0x8C30000, 40K) + TTB(0x8C3a000, 56K) + VBOOT2_WORK(0x8C48000, 16K) + STACK(0x8C4c000, 16K) + TIMESTAMP(0x8C50000, 1K) + PRERAM_CBMEM_CONSOLE(0x8C50400, 32K) + PRERAM_CBFS_CACHE(0x8C58400, 70K) + //REGION(bsram_unused, 0x8C69C00, 0xA2400, 0x100) + REGION(qclib, 0x8C6a000, 0x80000, 4096) + //REGION(dcb, 0x8CEa000, 0x4000, 4096) REGION(pmic, 0x8CED000, 0x10000, 4096) BSRAM_END(0x8D80000) -- To view, visit https://review.coreboot.org/c/coreboot/+/29969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1599242bb5158477318867508c72dc14f1244b00 Gerrit-Change-Number: 29969 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qclib: Add qclib support
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29967 Change subject: qclib: Add qclib support ...................................................................... qclib: Add qclib support Add qclib support to configure pmic, clocks, DDR Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/mainboard/google/mistral/mainboard.c M src/mainboard/google/mistral/romstage.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/include/soc/memlayout.ld A src/soc/qualcomm/qcs405/include/soc/qclib.h M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/qcs405/mmu.c A src/soc/qualcomm/qcs405/qclib_execute.c 8 files changed, 247 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29967/1 diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index 7201874..f4fc31e 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -18,12 +18,14 @@ #include <timestamp.h> #include <soc/usb.h> +#if 0 static struct usb_board_data usb0_board_data = { .parameter_override_x0 = 0x63, .parameter_override_x1 = 0x03, .parameter_override_x0 = 0x1d, .parameter_override_x1 = 0x03, }; +#endif static struct usb_board_data usb1_board_data = { .parameter_override_x0 = 0x63, @@ -35,7 +37,7 @@ static void setup_usb(void) { /* Setting Primarty usb controller */ - setup_usb_host(HSUSB_SS_PORT_0, &usb0_board_data); + //setup_usb_host(HSUSB_SS_PORT_0, &usb0_board_data); /* Setting secondary usb controller */ setup_usb_host(HSUSB_HS_PORT_1, &usb1_board_data); diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c index 31e5113..e53f485 100644 --- a/src/mainboard/google/mistral/romstage.c +++ b/src/mainboard/google/mistral/romstage.c @@ -21,19 +21,18 @@ #include <timestamp.h> #include <arch/stages.h> #include <soc/usb.h> +#include <soc/qclib.h> -#ifdef CONFIG_QC_SOC_SIMULATE extern void qcs405_mmu_dram_config_c(void); -#endif void platform_romstage_main(void) { + /* QCLib: DDR init & train */ + qclib_load_and_run(); + /* * Do DWC3 core and phy reset. Kick these resets off early * so they get atleast 1msec to settle. */ reset_usb(HSUSB_SS_PORT_0); reset_usb(HSUSB_HS_PORT_1); -#ifdef CONFIG_QC_SOC_SIMULATE - qcs405_mmu_dram_config_c(); -#endif } diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index c174cae..5e255e2 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -28,6 +28,7 @@ romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c romstage-y += usb.c +romstage-y += qclib_execute.c ################################################################################ ramstage-y += soc.c @@ -51,6 +52,28 @@ cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin ################################################################################ +QCLIB_FILE := $(QCS405_BLOB)/QcLib.elf +qclib_file := $(shell ls $(QCLIB_FILE)) +ifneq (,$(findstring $(QCLIB_FILE),$(qclib_file))) + QCLIB_CBFS := $(CONFIG_CBFS_PREFIX)/qclib + $(QCLIB_CBFS)-file := $(QCLIB_FILE) + $(QCLIB_CBFS)-type := stage + $(QCLIB_CBFS)-compression := none + cbfs-files-y += $(QCLIB_CBFS) +endif + +################################################################################ +PMIC_FILE := $(QCS405_BLOB)/pmic.elf +pmic_file := $(shell ls $(PMIC_FILE)) +ifneq (,$(findstring $(PMIC_FILE),$(pmic_file))) + PMIC_CBFS := $(CONFIG_CBFS_PREFIX)/pmiccfg + $(PMIC_CBFS)-file := $(PMIC_FILE) + $(PMIC_CBFS)-type := stage + $(PMIC_CBFS)-compression := none + cbfs-files-y += $(PMIC_CBFS) +endif + +################################################################################ QC_SEC_FILE := $(QCS405_BLOB)/qc_sec.mbn qc_sec_file := $(shell ls $(QC_SEC_FILE)) ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file))) diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index 03c6edb..dadbbe8 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -30,8 +30,8 @@ SSRAM_END(0x8608000) BSRAM_START(0x8C00000) - OVERLAP_VERSTAGE_ROMSTAGE(0x8C00000, 100K) - REGION(fw_reserved2, 0x8C19000, 0x16000, 4096) + REGION(fw_reserved2, 0x8C00000, 0x16000, 4096) + OVERLAP_VERSTAGE_ROMSTAGE(0x8C16000, 100K) BOOTBLOCK(0x8C2F000, 40K) TTB(0x8C39000, 56K) VBOOT2_WORK(0x8C47000, 16K) @@ -39,10 +39,10 @@ TIMESTAMP(0x8C4F000, 1K) PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K) PRERAM_CBFS_CACHE(0x8C57400, 70K) - REGION(bsram_unused, 0x8C68C00, 0xA2400, 0x100) -/* REGION(qclib, 0x8D0B000, 0x80000, 4096) - REGION(dcb, 0x8D8B000, 0x4000, 4096) - REGION(pmic, 0x8D8F000, 0xA000, 4096)*/ + //REGION(bsram_unused, 0x8C68C00, 0xA2400, 0x100) + REGION(qclib, 0x8C69000, 0x80000, 4096) + REGION(dcb, 0x8CE9000, 0x4000, 4096) + REGION(pmic, 0x8CED000, 0x10000, 4096) BSRAM_END(0x8D80000) DRAM_START(0x80000000) diff --git a/src/soc/qualcomm/qcs405/include/soc/qclib.h b/src/soc/qualcomm/qcs405/include/soc/qclib.h new file mode 100644 index 0000000..b6a681e --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/qclib.h @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_QCS405_QCLIB_H__ +#define _SOC_QUALCOMM_QCS405_QCLIB_H__ + +#include <fmap.h> + +/* coreboot & QCLib I/F definitions */ + +/* TE_NAME (table entry name) */ +#define TE_NAME_LENGTH 24 /* length (bytes) of name field */ +#define TE_DDR_INFORMATION "ddr_information" +#define TE_DCB_SETTINGS "dcb_settings" +#define TE_PMIC_SETTINGS "pmic_settings" +#define TE_DDR_TRAINING_DATA "ddr_training_data" +#define TE_LIMITS_CFG_DATA "limits_cfg_data" +#define TE_QCLIB_LOG_BUFFER "qclib_log_buffer" + +#if IS_ENABLED(CONFIG_QC_SDI_ENABLE) +#define TE_QCSDI "qcsdi" +#endif + +/* TE_INDEX (table entry index) */ +/* te_index_ddr_information must be first index + This allows DDR mmu configuration to occcur first + in case other write operations require DDR access */ +enum te_index { + te_index_ddr_information, /* 00 */ + te_index_dcb, /* 01 */ + te_index_pmic, /* 02 */ + te_index_ddr_training, /* 03 */ + te_index_limits_cfg, /* 04 */ + te_index_qclib_log_buffer, /* 05 */ + + /* add new entries above */ +#if IS_ENABLED(CONFIG_QC_SDI_ENABLE) + te_index_qcsdi, /* ALWAYS LAST */ +#endif + te_index_last +}; + +/* BA_BMASK_VALUES (blob_attributes bit mask values) */ +#define BA_BMASK_SAVE_TO_STORAGE 0x00000001 + +struct qclib_cb_if_table_entry { + const char name[TE_NAME_LENGTH]; /* 0x00 TE_NAME */ + uint64_t blob_address; /* 0x18 blob addr in SRAM */ + uint32_t size; /* 0x20 blob size in SRAM */ + uint32_t blob_attributes; /* 0x24 BA_BMASK_VALUES */ +}; + +/* GA_BMASK_VALUES (global_attributes bit mask values) */ +#define GA_BMASK_ENABLE_SOC_DEBUG_FLOW 0x00000001 +#define GA_BMASK_ENABLE_UART_LOGGING 0x00000002 + +#define INTERFACE_VERSION 0x00000001 +#define MAX_NUMBER_OF_ENTRIES 16 + +#define QCLIB_MAGIC_NUMBER 0x51434C49425F4342 /* QCLIB_CB */ + +struct qclib_cb_if_table_header { + uint64_t magic; /* 0x00 */ + uint32_t version; /* 0x08 */ + uint32_t num_entries; /* 0x0C */ + uint32_t max_entries; /* 0x10 */ + uint32_t global_attributes; /* 0x14 */ + uint64_t reserved; /* 0x18 */ + struct qclib_cb_if_table_entry te[MAX_NUMBER_OF_ENTRIES]; /* 0x20 */ +}; + +/* fmap_region[] table index */ +enum fmap_region_index { + fmap_ddr_region, + fmap_limits_cfg, + fmap_region_max +}; + +/* Region Device for Data in Flash */ +struct fmap_region { + struct region_device dev; + size_t size; + bool dev_valid; + enum te_index index; + char fmap_name[TE_NAME_LENGTH]; +}; + +void qclib_load_and_run(void); + +#endif // _SOC_QUALCOMM_QCS405_QCLIB_H_ diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h index f7cdc8d..447b7ae 100644 --- a/src/soc/qualcomm/qcs405/include/soc/symbols.h +++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h @@ -30,4 +30,12 @@ extern u8 _edram_reserved[]; #define _dram_reserved_size (_edram_reserved - _dram_reserved) +extern u8 _dcb[]; +extern u8 _edcb[]; +#define _dcb_size (_edcb - _dcb) + +extern u8 _pmic[]; +extern u8 _epmic[]; +#define _pmic_size (_epmic - _pmic) + #endif // _SOC_QUALCOMM_QCS405_SYMBOLS_H_ diff --git a/src/soc/qualcomm/qcs405/mmu.c b/src/soc/qualcomm/qcs405/mmu.c index bebca24..ecae39f 100644 --- a/src/soc/qualcomm/qcs405/mmu.c +++ b/src/soc/qualcomm/qcs405/mmu.c @@ -27,16 +27,12 @@ MA_DEV | MA_S | MA_RW); mmu_config_range((void *)_ssram, _ssram_size, MA_MEM | MA_S | MA_RW); mmu_config_range((void *)_bsram, _bsram_size, MA_MEM | MA_S | MA_RW); -#ifdef CONFIG_QC_SOC_SIMULATE mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_S | MA_RW); -#endif mmu_enable(); } -#ifdef CONFIG_QC_SOC_SIMULATE void qcs405_mmu_dram_config_c(void) { mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_NS | MA_RW); } -#endif diff --git a/src/soc/qualcomm/qcs405/qclib_execute.c b/src/soc/qualcomm/qcs405/qclib_execute.c new file mode 100644 index 0000000..917a04c --- /dev/null +++ b/src/soc/qualcomm/qcs405/qclib_execute.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <arch/cache.h> +#include <arch/mmu.h> +#include <cbfs.h> +#include <halt.h> +#include <console/console.h> +#include <timestamp.h> +#include <soc/mmu.h> +#include <soc/qclib.h> +#include <soc/symbols.h> + +#define PMIC_NAME "/pmiccfg" +#define DCB_NAME "/dcb" +#define QCLIB_NAME "/qclib" + +#define PBL_DATA_PTR 0x8c101a0 //0x14810188 + +void qclib_load_and_run(void) +{ + int (*doit)(void *, void *); + void *arg; + int ret_code; + struct mmu_context pre_qclib_mmu_context; + + struct prog qclib = + PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX QCLIB_NAME); + + struct prog pmic = + PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX PMIC_NAME); + + /* Attempt to load PMICCFG Blob */ +#if 0 + if (!cbfs_boot_load_file(CONFIG_CBFS_PREFIX PMIC_NAME, + _pmic, _pmic_size, CBFS_TYPE_RAW)) + goto fail; +#else + if (prog_locate(&pmic)) + goto fail; + + if (cbfs_prog_stage_load(&pmic)) + goto fail; +#endif + /* Attempt to load DCB Blob */ +// if (!cbfs_boot_load_file(CONFIG_CBFS_PREFIX DCB_NAME, +// _dcb, _dcb_size, CBFS_TYPE_RAW)) +// goto fail; + + /* Attempt to load QCLib elf */ + if (prog_locate(&qclib)) + goto fail; + + if (cbfs_prog_stage_load(&qclib)) + goto fail; + + prog_set_entry(&qclib, qclib.entry, (void *)PBL_DATA_PTR); + + printk(BIOS_DEBUG, "\n\n\nQCLib is about to Initialize PMIC and DDR\n"); + printk(BIOS_DEBUG, "Jumping to QCLib code at %p(%p)\n", + prog_entry(&qclib), prog_entry_arg(&qclib)); + + doit = prog_entry(&qclib); + arg = prog_entry_arg(&qclib); + + /* back-up mmu context before disabling mmu and executing qclib */ + mmu_save_context(&pre_qclib_mmu_context); + /* disable mmu before jumping to qclib. mmu_disable also + flushes and invalidates caches before disabling mmu. */ + mmu_disable(); + + ret_code = doit(arg, NULL); + printk(BIOS_DEBUG, "QCLib completed\n\n\n"); + + /* Before returning, QCLib flushes cache and disables mmu. + Explicitly disable mmu (flush, invalidate and disable mmu) + before re-enabling mmu with backed-up mmu context */ + mmu_disable(); + mmu_restore_context(&pre_qclib_mmu_context); + mmu_enable(); + + qcs405_mmu_dram_config_c(); + return; + +fail: + die("Couldn't run QCLib.\n"); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: Add blsp spi driver and enable SPI-NOR
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29968 Change subject: qcs405: Add blsp spi driver and enable SPI-NOR ...................................................................... qcs405: Add blsp spi driver and enable SPI-NOR Add the blsp spi driver required for qcs405 and also enable the support for WINBOND spi-nor flash Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/mainboard/google/mistral/Kconfig M src/soc/qualcomm/qcs405/Kconfig M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/mmu.h A src/soc/qualcomm/qcs405/include/soc/qup.h A src/soc/qualcomm/qcs405/include/soc/spi.h M src/soc/qualcomm/qcs405/spi.c 8 files changed, 1,138 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/29968/1 diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index f8e8ac7..b614a37 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -10,6 +10,8 @@ select COMMON_CBFS_SPI_WRAPPER select SOC_QUALCOMM_QCS405 select SPI_FLASH + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND select MAINBOARD_HAS_CHROMEOS select MISSING_BOARD_RESET diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index b24dc9e..29960d4 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -21,9 +21,13 @@ select VBOOT_OPROM_MATTERS select VBOOT_STARTS_IN_BOOTBLOCK -config QC_SOC_SIMULATE - bool - prompt "Build for Early Simulation Environment" - default y +config QCS405_BLSP_SPI + bool + default y + prompt "Build Flash Using SPI-NOR" + +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 5 endif diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 5e255e2..ee68751 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -9,14 +9,14 @@ bootblock-y += gpio.c bootblock-y += clock.c bootblock-$(CONFIG_DRIVERS_UART) += uart.c -bootblock-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c +bootblock-y += flash_controller.c ################################################################################ verstage-y += spi.c verstage-y += timer.c verstage-y += gpio.c verstage-$(CONFIG_DRIVERS_UART) += uart.c -verstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c +verstage-y += flash_controller.c ################################################################################ romstage-y += spi.c @@ -26,9 +26,9 @@ romstage-y += clock.c romstage-y += mmu.c romstage-$(CONFIG_DRIVERS_UART) += uart.c -romstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c romstage-y += usb.c romstage-y += qclib_execute.c +romstage-y+= flash_controller.c ################################################################################ ramstage-y += soc.c @@ -38,8 +38,8 @@ ramstage-y += gpio.c ramstage-y += clock.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c -ramstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ramstage-y += usb.c +ramstage-y += flash_controller.c ################################################################################ diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 6307259..f26face 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -203,6 +203,8 @@ clock_configure(blsp2_qup0_spi_clk, spi_cfg, 50000000, ARRAY_SIZE(spi_cfg)); clock_enable(REG(GCC_BLSP2_QUP0_SPI_APPS_CBCR)); - + clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), + REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), + BLSP2_AHB_CLK_ENA); } diff --git a/src/soc/qualcomm/qcs405/include/soc/mmu.h b/src/soc/qualcomm/qcs405/include/soc/mmu.h index 7bf024f..bb8aa30 100644 --- a/src/soc/qualcomm/qcs405/include/soc/mmu.h +++ b/src/soc/qualcomm/qcs405/include/soc/mmu.h @@ -19,8 +19,8 @@ #define DRAMSIZE1GB 0x40000000 void qcs405_mmu_init(void); -#ifdef CONFIG_QC_SOC_SIMULATE +//#ifdef CONFIG_QC_SOC_SIMULATE void qcs405_mmu_dram_config_c(void); -#endif +//#endif #endif // _SOC_QUALCOMM_QCS405_MMU_H_ diff --git a/src/soc/qualcomm/qcs405/include/soc/qup.h b/src/soc/qualcomm/qcs405/include/soc/qup.h new file mode 100644 index 0000000..211b44e --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/qup.h @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 - 2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __QUP_H__ +#define __QUP_H__ + + +/* QUP block registers */ +#define QUP_CONFIG 0x000 +#define QUP_STATE 0x004 +#define QUP_IO_MODES 0x008 +#define QUP_SW_RESET 0x00C +#define QUP_TRANSFER_CANCEL 0x014 +#define QUP_OPERATIONAL 0x018 +#define QUP_ERROR_FLAGS 0x01C +#define QUP_ERROR_FLAGS_EN 0x020 +#define QUP_TEST_CTRL 0x024 +#define QUP_OPERATIONAL_MASK 0x028 +#define QUP_HW_VERSION 0x030 +#define QUP_MX_OUTPUT_COUNT 0x100 +#define QUP_MX_OUTPUT_CNT_CURRENT 0x104 +#define QUP_OUTPUT_DEBUG 0x108 +#define QUP_OUTPUT_FIFO_WORD_CNT 0x10C +#define QUP_OUTPUT_FIFO 0x110 +#define QUP_OUTPUT_FIFO_SIZE 64 /* bytes */ +#define QUP_MX_WRITE_COUNT 0x150 +#define QUP_MX_WRITE_CNT_CURRENT 0x154 +#define QUP_MX_INPUT_COUNT 0x200 +#define QUP_MX_INPUT_CNT_CURRENT 0x204 +#define QUP_MX_READ_COUNT 0x208 +#define QUP_MX_READ_CNT_CURRENT 0x20C +#define QUP_INPUT_DEBUG 0x210 +#define QUP_INPUT_FIFO_WORD_CNT 0x214 +#define QUP_INPUT_FIFO 0x218 +#define QUP_INPUT_FIFO_SIZE 64 /* bytes */ +#define QUP_I2C_MASTER_CLK_CTL 0x400 +#define QUP_I2C_MASTER_STATUS 0x404 +#define QUP_I2C_MASTER_CONFIG 0x408 +#define QUP_I2C_MASTER_BUS_CLEAR 0x40C +#define QUP_I2C_MASTER_LOCAL_ID 0x410 +#define QUP_I2C_MASTER_COMMAND 0x414 + +#define OUTPUT_FIFO_FULL (1<<6) +#define INPUT_FIFO_NOT_EMPTY (1<<5) +#define OUTPUT_FIFO_NOT_EMPTY (1<<4) +#define INPUT_SERVICE_FLAG (1<<9) +#define OUTPUT_SERVICE_FLAG (1<<8) +#define QUP_UNPACK_EN (1<<14) +#define QUP_PACK_EN (1<<15) +#define QUP_OUTPUT_BIT_SHIFT_EN (1<<16) + +#define QUP_MODE_MASK (0x03) +#define QUP_OUTPUT_MODE_SHFT (10) +#define QUP_INPUT_MODE_SHFT (12) + +#define QUP_FS_DIVIDER_MASK (0xFF) + +#define QUP_APP_CLK_ON_EN (1 << 12) +#define QUP_CORE_CLK_ON_EN (1 << 13) +#define QUP_MINI_CORE_PROTO_SHFT (8) +#define QUP_MINI_CORE_PROTO_MASK (0x0F) + +/* Mini-core states */ +#define QUP_STATE_RESET 0x0 +#define QUP_STATE_RUN 0x1 +#define QUP_STATE_PAUSE 0x3 +#define QUP_STATE_VALID (1<<2) +#define QUP_STATE_MASK 0x3 +#define QUP_STATE_VALID_MASK (1<<2) + +/* Tags for output FIFO */ +#define QUP_I2C_1CLK_NOOP_SEQ 0x1 /*MSB 8-bit NOP, LSB 8-bits 1 clk.*/ +#define QUP_I2C_START_SEQ (0x1 << 8) +#define QUP_I2C_DATA_SEQ (0x2 << 8) +#define QUP_I2C_STOP_SEQ (0x3 << 8) +#define QUP_I2C_RECV_SEQ (0x4 << 8) + +/* Tags for input FIFO */ +#define QUP_I2C_MIDATA_SEQ (0x5 << 8) +#define QUP_I2C_MISTOP_SEQ (0x6 << 8) +#define QUP_I2C_MINACK_SEQ (0x7 << 8) + +#define QUP_I2C_ADDR(x) ((x & 0xFF) << 1) +#define QUP_I2C_DATA(x) (x & 0xFF) +#define QUP_I2C_MI_TAG(x) (x & 0xFF00) +#define QUP_I2C_SLAVE_READ (0x1) + +/*Bit vals for I2C_MASTER_CLK_CTL register */ +#define QUP_HS_DIVIDER_SHFT (8) +#define QUP_DIVIDER_MIN_VAL (0x3) + +/* Bit masks for I2C_MASTER_STATUS register */ +#define QUP_I2C_INVALID_READ_SEQ (1 << 25) +#define QUP_I2C_INVALID_READ_ADDR (1 << 24) +#define QUP_I2C_INVALID_TAG (1 << 23) +#define QUP_I2C_FAILED_MASK (0x3 << 6) +#define QUP_I2C_INVALID_WRITE (1 << 5) +#define QUP_I2C_ARB_LOST (1 << 4) +#define QUP_I2C_PACKET_NACK (1 << 3) +#define QUP_I2C_BUS_ERROR (1 << 2) + +typedef enum { + QUP_SUCCESS = 0, + QUP_ERR_BAD_PARAM, + QUP_ERR_STATE_SET, + QUP_ERR_TIMEOUT, + QUP_ERR_UNSUPPORTED, + QUP_ERR_I2C_FAILED, + QUP_ERR_I2C_ARB_LOST, + QUP_ERR_I2C_BUS_ERROR, + QUP_ERR_I2C_INVALID_SLAVE_ADDR, + QUP_ERR_XFER_FAIL, + QUP_ERR_I2C_NACK, + QUP_ERR_I2C_INVALID_WRITE, + QUP_ERR_I2C_INVALID_TAG, + QUP_ERR_UNDEFINED, +} qup_return_t; + +typedef enum { + QUP_MINICORE_SPI = 1, + QUP_MINICORE_I2C_MASTER, + QUP_MINICORE_I2C_SLAVE +} qup_protocol_t; + +typedef enum { + QUP_MODE_FIFO = 0, + QUP_MODE_BLOCK, + QUP_MODE_DATAMOVER, +} qup_mode_t; + +typedef struct { + qup_protocol_t protocol; + unsigned clk_frequency; + unsigned src_frequency; + qup_mode_t mode; + unsigned initialized; +} qup_config_t; + +typedef struct { + qup_protocol_t protocol; + union { + struct { + uint8_t addr; + uint8_t *data; + unsigned data_len; + } iic; + struct { + void *in; + void *out; + unsigned size; + } spi; + } p; +} qup_data_t; + +/* + * Initialize BLSP QUP block for FIFO I2C transfers. + * id[IN]: BLSP for which QUP is to be initialized. + * config_ptr[IN]: configurations parameters for the QUP. + * + * return: QUP_SUCCESS, if initialization succeeds. + */ +qup_return_t qup_init(blsp_qup_id_t id, const qup_config_t *config_ptr); + +/* + * Set QUP state to run, pause, reset. + * id[IN]: BLSP block for which QUP state is to be set. + * state[IN]: New state to transition to. + * + * return: QUP_SUCCESS, if state transition succeeds. + */ +qup_return_t qup_set_state(blsp_qup_id_t id, uint32_t state); + +/* + * Reset the status bits set during an i2c transfer. + * id[IN]: BLSP block for which i2c status bits are to be cleared. + * + * return: QUP_SUCCESS, if status bits are cleared successfully. + */ +qup_return_t qup_reset_i2c_master_status(blsp_qup_id_t id); + +/* + * Send data to the peripheral on the bus. + * id[IN]: BLSP block for which data is to be sent. + * p_tx_obj[IN]: Data to be sent to the slave on the bus. + * stop_seq[IN]: When set to non-zero QUP engine sends i2c stop sequnce. + * + * return: QUP_SUCCESS, when data is sent successfully to the peripheral. + */ +qup_return_t qup_send_data(blsp_qup_id_t id, qup_data_t *p_tx_obj, + uint8_t stop_seq); + +/* + * Receive data from peripheral on the bus. + * id[IN]: BLSP block from which data is to be received. + * p_tx_obj[IN]: length of data to be received, slave address. + * [OUT]: buffer filled with data from slave. + * + * return: QUP_SUCCESS, when data is received successfully. + */ +qup_return_t qup_recv_data(blsp_qup_id_t id, qup_data_t *p_tx_obj); + +#endif //__QUP_H__ diff --git a/src/soc/qualcomm/qcs405/include/soc/spi.h b/src/soc/qualcomm/qcs405/include/soc/spi.h new file mode 100644 index 0000000..5da709f --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/spi.h @@ -0,0 +1,189 @@ +/* + * Register definitions for the IPQ BLSP SPI Controller + * + * Copyright (c) 2012 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _IPQ40XX_SPI_H_ +#define _IPQ40XX_SPI_H_ + +#include <soc/iomap.h> +#include <soc/qup.h> +#include <spi-generic.h> + +#define BLSP0_QUP_REG_BASE ((void *)0x78b5000u) +#define BLSP5_QUP_REG_BASE ((void *)0x7af5000u) + +#define BLSP0_SPI_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000300) +#define BLSP5_SPI_CONFIG_REG (BLSP5_QUP_REG_BASE + 0x00000300) + +#define BLSP0_SPI_IO_CONTROL_REG (BLSP0_QUP_REG_BASE + 0x00000304) +#define BLSP5_SPI_IO_CONTROL_REG (BLSP5_QUP_REG_BASE + 0x00000304) + +#define BLSP0_SPI_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x00000308) +#define BLSP5_SPI_ERROR_FLAGS_REG (BLSP5_QUP_REG_BASE + 0x00000308) + +#define BLSP0_SPI_DEASSERT_WAIT_REG (BLSP0_QUP_REG_BASE + 0x00000310) +#define BLSP5_SPI_DEASSERT_WAIT_REG (BLSP5_QUP_REG_BASE + 0x00000310) +#define BLSP0_SPI_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x0000030c) +#define BLSP5_SPI_ERROR_FLAGS_EN_REG (BLSP5_QUP_REG_BASE + 0x0000030c) + +#define BLSP0_QUP_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000000) +#define BLSP5_QUP_CONFIG_REG (BLSP5_QUP_REG_BASE + 0x00000000) + +#define BLSP0_QUP_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x0000001c) +#define BLSP5_QUP_ERROR_FLAGS_REG (BLSP5_QUP_REG_BASE + 0x0000001c) + +#define BLSP0_QUP_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x00000020) +#define BLSP5_QUP_ERROR_FLAGS_EN_REG (BLSP5_QUP_REG_BASE + 0x00000020) + +#define BLSP0_QUP_OPERATIONAL_MASK (BLSP0_QUP_REG_BASE + 0x00000028) +#define BLSP5_QUP_OPERATIONAL_MASK (BLSP5_QUP_REG_BASE + 0x00000028) + +#define BLSP0_QUP_OPERATIONAL_REG (BLSP0_QUP_REG_BASE + 0x00000018) +#define BLSP5_QUP_OPERATIONAL_REG (BLSP5_QUP_REG_BASE + 0x00000018) + +#define BLSP0_QUP_IO_MODES_REG (BLSP0_QUP_REG_BASE + 0x00000008) +#define BLSP5_QUP_IO_MODES_REG (BLSP5_QUP_REG_BASE + 0x00000008) + +#define BLSP0_QUP_STATE_REG (BLSP0_QUP_REG_BASE + 0x00000004) +#define BLSP5_QUP_STATE_REG (BLSP5_QUP_REG_BASE + 0x00000004) + +#define BLSP0_QUP_INPUT_FIFOc_REG(c) \ + (BLSP0_QUP_REG_BASE + 0x00000218 + 4 * (c)) +#define BLSP5_QUP_INPUT_FIFOc_REG(c) \ + (BLSP5_QUP_REG_BASE + 0x00000218 + 4 * (c)) + +#define BLSP0_QUP_OUTPUT_FIFOc_REG(c) \ + (BLSP0_QUP_REG_BASE + 0x00000110 + 4 * (c)) +#define BLSP5_QUP_OUTPUT_FIFOc_REG(c) \ + (BLSP5_QUP_REG_BASE + 0x00000110 + 4 * (c)) + +#define BLSP0_QUP_MX_INPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000200) +#define BLSP5_QUP_MX_INPUT_COUNT_REG (BLSP5_QUP_REG_BASE + 0x00000200) + +#define BLSP0_QUP_MX_OUTPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000100) +#define BLSP5_QUP_MX_OUTPUT_COUNT_REG (BLSP5_QUP_REG_BASE + 0x00000100) + +#define BLSP0_QUP_SW_RESET_REG (BLSP0_QUP_REG_BASE + 0x0000000c) +#define BLSP5_QUP_SW_RESET_REG (BLSP5_QUP_REG_BASE + 0x0000000c) + +#define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8) +#define QUP_CONFIG_MINI_CORE_SPI (1 << 8) +#define QUP_CONF_INPUT_MSK (1 << 7) +#define QUP_CONF_INPUT_ENA (0 << 7) +#define QUP_CONF_NO_INPUT (1 << 7) +#define QUP_CONF_OUTPUT_MSK (1 << 6) +#define QUP_CONF_OUTPUT_ENA (0 << 6) +#define QUP_CONF_NO_OUTPUT (1 << 6) +#define QUP_CONF_N_MASK 0x1F +#define QUP_CONF_N_SPI_8_BIT_WORD 0x07 + +#define SPI_CONFIG_INPUT_FIRST (1 << 9) +#define SPI_CONFIG_INPUT_FIRST_BACK (0 << 9) +#define SPI_CONFIG_LOOP_BACK_MSK (1 << 8) +#define SPI_CONFIG_NO_LOOP_BACK (0 << 8) +#define SPI_CONFIG_NO_SLAVE_OPER_MSK (1 << 5) +#define SPI_CONFIG_NO_SLAVE_OPER (0 << 5) + +#define SPI_IO_CTRL_CLK_ALWAYS_ON (0 << 9) +#define SPI_IO_CTRL_MX_CS_MODE (1 << 8) +#define SPI_IO_CTRL_NO_TRI_STATE (1 << 0) +#define SPI_IO_CTRL_FORCE_CS_MSK (1 << 11) +#define SPI_IO_CTRL_FORCE_CS_EN (1 << 11) +#define SPI_IO_CTRL_FORCE_CS_DIS (0 << 11) +#define SPI_IO_CTRL_CLOCK_IDLE_HIGH (1 << 10) + +#define QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK (1 << 16) +#define QUP_IO_MODES_OUTPUT_BIT_SHIFT_EN (1 << 16) +#define QUP_IO_MODES_INPUT_MODE_MSK (0x03 << 12) +#define QUP_IO_MODES_INPUT_BLOCK_MODE (0x01 << 12) +#define QUP_IO_MODES_OUTPUT_MODE_MSK (0x03 << 10) +#define QUP_IO_MODES_OUTPUT_BLOCK_MODE (0x01 << 10) + +#define SPI_INPUT_BLOCK_SIZE 4 +#define SPI_OUTPUT_BLOCK_SIZE 4 + +#define MAX_COUNT_SIZE 0xffff + +#define SPI_CORE_RESET 0 +#define SPI_CORE_RUNNING 1 +#define SPI_MODE0 0 +#define SPI_MODE1 1 +#define SPI_MODE2 2 +#define SPI_MODE3 3 +#define BLSP0_SPI 0 +#define BLSP5_SPI 5 + +struct blsp_spi { + void *spi_config; + void *io_control; + void *error_flags; + void *error_flags_en; + void *qup_config; + void *qup_error_flags; + void *qup_error_flags_en; + void *qup_operational; + void *qup_io_modes; + void *qup_state; + void *qup_input_fifo; + void *qup_output_fifo; + void *qup_mx_input_count; + void *qup_mx_output_count; + void *qup_sw_reset; + void *qup_ns_reg; + void *qup_md_reg; + void *qup_op_mask; + void *qup_deassert_wait; +}; + + +#define SUCCESS 0 + +#define DUMMY_DATA_VAL 0 +#define TIMEOUT_CNT 100 + +#define ETIMEDOUT -10 +#define EINVAL -11 +#define EIO -12 + +/* MX_INPUT_COUNT and MX_OUTPUT_COUNT are 16-bits. Zero has a special meaning + * (count function disabled) and does not hold significance in the count. */ +#define MAX_PACKET_COUNT ((64 * KiB) - 1) + + +struct ipq_spi_slave { + struct spi_slave slave; + const struct blsp_spi *regs; + unsigned int mode; + unsigned int initialized; + unsigned long freq; + int allocated; +}; + +#endif /* _IPQ40XX_SPI_H_ */ diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index 73e538e..7801be8 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -1,71 +1,736 @@ /* - * This file is part of the coreboot project. + * Copyright (c) 2012 The Linux Foundation. All rights reserved. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include <spi-generic.h> +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <gpio.h> +#include <soc/iomap.h> +#include <soc/spi.h> +#include <stdlib.h> +#include <string.h> #include <spi_flash.h> -#if IS_ENABLED(CONFIG_QC_SOC_SIMULATE) - -extern int spi_simulate_ram_flash_probe(const struct spi_slave *spi, - struct spi_flash *flash); - -static const struct spi_ctrlr spi_ctrlr = { - .flash_probe = spi_simulate_ram_flash_probe, -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { +static const struct blsp_spi spi_reg[] = { + /* BLSP0 registers for SPI interface */ { - .ctrlr = &spi_ctrlr, - .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, - .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, - } + BLSP0_SPI_CONFIG_REG, + BLSP0_SPI_IO_CONTROL_REG, + BLSP0_SPI_ERROR_FLAGS_REG, + BLSP0_SPI_ERROR_FLAGS_EN_REG, + BLSP0_QUP_CONFIG_REG, + BLSP0_QUP_ERROR_FLAGS_REG, + BLSP0_QUP_ERROR_FLAGS_EN_REG, + BLSP0_QUP_OPERATIONAL_REG, + BLSP0_QUP_IO_MODES_REG, + BLSP0_QUP_STATE_REG, + BLSP0_QUP_INPUT_FIFOc_REG(0), + BLSP0_QUP_OUTPUT_FIFOc_REG(0), + BLSP0_QUP_MX_INPUT_COUNT_REG, + BLSP0_QUP_MX_OUTPUT_COUNT_REG, + BLSP0_QUP_SW_RESET_REG, + 0, + 0, + BLSP0_QUP_OPERATIONAL_MASK, + BLSP0_SPI_DEASSERT_WAIT_REG, + }, + {0},{0},{0},{0}, + /* BLSP5 registers for SPI interface */ + { + BLSP5_SPI_CONFIG_REG, + BLSP5_SPI_IO_CONTROL_REG, + BLSP5_SPI_ERROR_FLAGS_REG, + BLSP5_SPI_ERROR_FLAGS_EN_REG, + BLSP5_QUP_CONFIG_REG, + BLSP5_QUP_ERROR_FLAGS_REG, + BLSP5_QUP_ERROR_FLAGS_EN_REG, + BLSP5_QUP_OPERATIONAL_REG, + BLSP5_QUP_IO_MODES_REG, + BLSP5_QUP_STATE_REG, + BLSP5_QUP_INPUT_FIFOc_REG(0), + BLSP5_QUP_OUTPUT_FIFOc_REG(0), + BLSP5_QUP_MX_INPUT_COUNT_REG, + BLSP5_QUP_MX_OUTPUT_COUNT_REG, + BLSP5_QUP_SW_RESET_REG, + 0, + 0, + BLSP5_QUP_OPERATIONAL_MASK, + BLSP5_SPI_DEASSERT_WAIT_REG, + }, + }; -#else +static int check_bit_state(void *reg_addr, int mask, + int val, int us_delay) +{ + unsigned int count = TIMEOUT_CNT; + + while ((read32(reg_addr) & mask) != val) { + count--; + if (count == 0) + return -ETIMEDOUT; + udelay(us_delay); + } + + return SUCCESS; +} + +/* + * Check whether QUPn State is valid + */ +static int check_qup_state_valid(struct ipq_spi_slave *ds) +{ + + return check_bit_state(ds->regs->qup_state, QUP_STATE_VALID_MASK, + QUP_STATE_VALID, 1); + +} + +/* + * Configure QUPn Core state + */ +static int config_spi_state(struct ipq_spi_slave *ds, unsigned int state) +{ + uint32_t val; + int ret = SUCCESS; + + ret = check_qup_state_valid(ds); + if (ret != SUCCESS) + return ret; + + switch (state) { + case QUP_STATE_RUN: + /* Set the state to RUN */ + val = ((read32(ds->regs->qup_state) & ~QUP_STATE_MASK) + | QUP_STATE_RUN); + write32(ds->regs->qup_state, val); + ret = check_qup_state_valid(ds); + break; + case QUP_STATE_RESET: + /* Set the state to RESET */ + val = ((read32(ds->regs->qup_state) & ~QUP_STATE_MASK) + | QUP_STATE_RESET); + write32(ds->regs->qup_state, val); + ret = check_qup_state_valid(ds); + break; + default: + printk(BIOS_ERR, "unsupported QUP SPI state : %d\n", state); + ret = -EINVAL; + break; + } + + return ret; +} + +/* + * Set QUPn SPI Mode + */ +static void spi_set_mode(struct ipq_spi_slave *ds, unsigned int mode) +{ + unsigned int clk_idle_state; + unsigned int input_first_mode; + uint32_t val; + + switch (mode) { + case SPI_MODE0: + clk_idle_state = 0; + input_first_mode = SPI_CONFIG_INPUT_FIRST; + break; + case SPI_MODE1: + clk_idle_state = 0; + input_first_mode = 0; + break; + case SPI_MODE2: + clk_idle_state = 1; + input_first_mode = SPI_CONFIG_INPUT_FIRST; + break; + case SPI_MODE3: + clk_idle_state = 1; + input_first_mode = 0; + break; + default: + printk(BIOS_ERR, "unsupported spi mode : %d\n", mode); + return; + } + + + val = read32(ds->regs->spi_config); + val |= input_first_mode; + write32(ds->regs->spi_config, val); + + val = read32(ds->regs->io_control); + if (clk_idle_state) + val |= SPI_IO_CTRL_CLOCK_IDLE_HIGH; + else + val &= ~SPI_IO_CTRL_CLOCK_IDLE_HIGH; + + write32(ds->regs->io_control, val); +} + +/* + * Reset entire QUP and all mini cores + */ +static void spi_reset(struct ipq_spi_slave *ds) +{ + write32(ds->regs->qup_sw_reset, 0x1); + udelay(5); + check_qup_state_valid(ds); +} + +static struct ipq_spi_slave spi_slave_pool[2]; + +static struct ipq_spi_slave *to_ipq_spi(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds; + size_t i; + + for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) { + ds = spi_slave_pool + i; + + if (!ds->allocated) + continue; + + if ((ds->slave.bus == slave->bus) && + (ds->slave.cs == slave->cs)) + return ds; + } + + return NULL; +} + +/* + * BLSP QUPn SPI Hardware Initialisation + */ +static int spi_hw_init(struct ipq_spi_slave *ds) +{ + int ret; + + ds->initialized = 0; + + /* QUPn module configuration */ + spi_reset(ds); + + /* Set the QUPn state */ + ret = config_spi_state(ds, QUP_STATE_RESET); + if (ret) + return ret; + + /* + * Configure Mini core to SPI core with Input Output enabled, + * SPI master, N = 8 bits + */ + clrsetbits_le32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK | + QUP_CONF_INPUT_MSK | + QUP_CONF_OUTPUT_MSK | + QUP_CONF_N_MASK, + QUP_CONFIG_MINI_CORE_SPI | + QUP_CONF_INPUT_ENA | + QUP_CONF_OUTPUT_ENA | + QUP_CONF_N_SPI_8_BIT_WORD); + + /* + * Configure Input first SPI protocol, + * SPI master mode and no loopback + */ + clrsetbits_le32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK | + SPI_CONFIG_NO_SLAVE_OPER_MSK, + SPI_CONFIG_NO_LOOP_BACK | + SPI_CONFIG_NO_SLAVE_OPER); + + /* + * Configure SPI IO Control Register + * CLK_ALWAYS_ON = 0 + * MX_CS_MODE = 0 + * NO_TRI_STATE = 1 + */ + write32(ds->regs->io_control, SPI_IO_CTRL_CLK_ALWAYS_ON | + SPI_IO_CTRL_NO_TRI_STATE | SPI_IO_CTRL_MX_CS_MODE); + + /* + * Configure SPI IO Modes. + * OUTPUT_BIT_SHIFT_EN = 1 + * INPUT_MODE = Block Mode + * OUTPUT MODE = Block Mode + */ + clrsetbits_le32(ds->regs->qup_io_modes, + QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK | + QUP_IO_MODES_INPUT_MODE_MSK | + QUP_IO_MODES_OUTPUT_MODE_MSK, + QUP_IO_MODES_OUTPUT_BIT_SHIFT_EN | + QUP_IO_MODES_INPUT_BLOCK_MODE | + QUP_IO_MODES_OUTPUT_BLOCK_MODE); + + spi_set_mode(ds, ds->mode); + + /* Disable Error mask */ + write32(ds->regs->error_flags_en, 0); + write32(ds->regs->qup_error_flags_en, 0); + + write32(ds->regs->qup_deassert_wait, 0); + + ds->initialized = 1; + + return SUCCESS; +} static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { - return 0; + struct ipq_spi_slave *ds = to_ipq_spi(slave); + unsigned int ret; + + ret = spi_hw_init(ds); + if (ret) + return -EIO; + switch(slave->bus) { + case 5: + + gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + + break; + default: + printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); + break; + } + + + return SUCCESS; } static void spi_ctrlr_release_bus(const struct spi_slave *slave) { + struct ipq_spi_slave *ds = to_ipq_spi(slave); + /* Reset the SPI hardware */ + spi_reset(ds); + ds->initialized = 0; } -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytes_out, void *din, size_t bytes_in) +static void write_force_cs(const struct spi_slave *slave, int assert) { + struct ipq_spi_slave *ds = to_ipq_spi(slave); +#if 0 + io = read32(ds->regs->io_control); + + io &= ~(3 << 2); + write32(ds->regs->io_control, io); +#else + if (assert) + clrsetbits_le32(ds->regs->io_control, + SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_EN); + else + clrsetbits_le32(ds->regs->io_control, + SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_DIS); +#endif + return; +} + +/* + * Function to write data to OUTPUT FIFO + */ +static void spi_write_byte(struct ipq_spi_slave *ds, unsigned char data) +{ + /* Wait for space in the FIFO */ + while ((read32(ds->regs->qup_operational) & OUTPUT_FIFO_FULL)) + udelay(1); + + /* Write the byte of data */ + write32(ds->regs->qup_output_fifo, data); +} + +/* + * Function to read data from Input FIFO + */ +static unsigned char spi_read_byte(struct ipq_spi_slave *ds) +{ + /* Wait for Data in FIFO */ + while (!(read32(ds->regs->qup_operational) & INPUT_FIFO_NOT_EMPTY)) + udelay(1); + + /* Read a byte of data */ + return read32(ds->regs->qup_input_fifo) & 0xff; +} + +/* + * Function to check wheather Input or Output FIFO + * has data to be serviced + */ +static int check_fifo_status(void *reg_addr) +{ + unsigned int count = TIMEOUT_CNT; + unsigned int status_flag; + unsigned int val; + + do { + val = read32(reg_addr); + count--; + if (count == 0) + return -ETIMEDOUT; + status_flag = ((val & OUTPUT_SERVICE_FLAG) | + (val & INPUT_SERVICE_FLAG)); + } while (!status_flag); + + return SUCCESS; +} + +/* + * Function to configure Input and Output enable/disable + */ +static void enable_io_config(struct ipq_spi_slave *ds, + uint32_t write_cnt, uint32_t read_cnt) +{ + + if (write_cnt) { + clrsetbits_le32(ds->regs->qup_config, + QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA); + } else { + clrsetbits_le32(ds->regs->qup_config, + QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT); + } + + if (read_cnt) { + clrsetbits_le32(ds->regs->qup_config, + QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA); + } else { + clrsetbits_le32(ds->regs->qup_config, + QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT); + } + + return; +} + +/* + * Function to read bytes number of data from the Input FIFO + */ +static int __blsp_spi_read(struct ipq_spi_slave *ds, u8 *data_buffer, + unsigned int bytes) +{ + uint32_t val; + unsigned int i; + unsigned int fifo_count; + int ret = SUCCESS; + int state_config; + + /* Configure no of bytes to read */ + state_config = config_spi_state(ds, QUP_STATE_RESET); + if (state_config) + return state_config; + + /* Configure input and output enable */ + enable_io_config(ds, 0, bytes); + + write32(ds->regs->qup_mx_input_count, bytes); + + state_config = config_spi_state(ds, QUP_STATE_RUN); + if (state_config) + return state_config; + + while (bytes) { + ret = check_fifo_status(ds->regs->qup_operational); + if (ret != SUCCESS) + goto out; + + val = read32(ds->regs->qup_operational); + if (val & INPUT_SERVICE_FLAG) { + /* + * acknowledge to hw that software will + * read input data + */ + val &= INPUT_SERVICE_FLAG; + write32(ds->regs->qup_operational, val); + + fifo_count = ((bytes > SPI_INPUT_BLOCK_SIZE) ? + SPI_INPUT_BLOCK_SIZE : bytes); + + for (i = 0; i < fifo_count; i++) { + *data_buffer = spi_read_byte(ds); + data_buffer++; + bytes--; + } + } + } + +out: + /* + * Put the SPI Core back in the Reset State + * to end the transfer + */ + (void)config_spi_state(ds, QUP_STATE_RESET); + return ret; +} + +static int blsp_spi_read(struct ipq_spi_slave *ds, u8 *data_buffer, + unsigned int bytes) +{ + int length, ret; + + while (bytes) { + length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE; + + ret = __blsp_spi_read(ds, data_buffer, length); + if (ret != SUCCESS) + return ret; + + data_buffer += length; + bytes -= length; + } + return 0; } +/* + * Function to write data to the Output FIFO + */ +static int __blsp_spi_write(struct ipq_spi_slave *ds, const u8 *cmd_buffer, + unsigned int bytes) +{ + uint32_t val; + unsigned int i; + unsigned int write_len = bytes; + unsigned int read_len = 3; //bytes; hack for now + unsigned int fifo_count; + int ret = SUCCESS; + int state_config; + + state_config = config_spi_state(ds, QUP_STATE_RESET); + if (state_config) + return state_config; + + /* No of bytes to be written in Output FIFO */ + write32(ds->regs->qup_mx_output_count, bytes); + write32(ds->regs->qup_mx_input_count, bytes); + state_config = config_spi_state(ds, QUP_STATE_RUN); + if (state_config) + return state_config; + + /* Configure input and output enable */ + enable_io_config(ds, write_len, read_len); + + /* + * read_len considered to ensure that we read the dummy data for the + * write we performed. This is needed to ensure with WR-RD transaction + * to get the actual data on the subsequent read cycle that happens + */ + while (write_len || read_len) { + + ret = check_fifo_status(ds->regs->qup_operational); + if (ret != SUCCESS) + goto out; + + val = read32(ds->regs->qup_operational); + if (val & OUTPUT_SERVICE_FLAG) { + /* + * acknowledge to hw that software will write + * expected output data + */ + val &= OUTPUT_SERVICE_FLAG; + write32(ds->regs->qup_operational, val); + + if (write_len > SPI_OUTPUT_BLOCK_SIZE) + fifo_count = SPI_OUTPUT_BLOCK_SIZE; + else + fifo_count = write_len; + + for (i = 0; i < fifo_count; i++) { + /* Write actual data to output FIFO */ + spi_write_byte(ds, *cmd_buffer); + cmd_buffer++; + write_len--; + } + } + if (val & INPUT_SERVICE_FLAG) { + /* + * acknowledge to hw that software + * will read input data + */ + val &= INPUT_SERVICE_FLAG; + write32(ds->regs->qup_operational, val); + + if (read_len > SPI_INPUT_BLOCK_SIZE) + fifo_count = SPI_INPUT_BLOCK_SIZE; + else + fifo_count = read_len; + + for (i = 0; i < fifo_count; i++) { + /* Read dummy data for the data written */ + (void)spi_read_byte(ds); + + /* Decrement the read count after reading the + * dummy data from the device. This is to make + * sure we read dummy data before we write the + * data to fifo + */ + read_len--; + } + } + } + +out: + /* + * Put the SPI Core back in the Reset State + * to end the transfer + */ + (void)config_spi_state(ds, QUP_STATE_RESET); + + return ret; +} + +static int blsp_spi_write(struct ipq_spi_slave *ds, u8 *cmd_buffer, + unsigned int bytes) +{ + int length, ret; + + while (bytes) { + length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE; + + ret = __blsp_spi_write(ds, cmd_buffer, length); + if (ret != SUCCESS) + return ret; + + cmd_buffer += length; + bytes -= length; + } + + return 0; +} + +/* + * This function is invoked with either tx_buf or rx_buf. + * Calling this function with both null does a chip select change. + */ +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + u8 *txp = (u8 *)dout; + u8 *rxp = (u8 *)din; + int ret; + +#if 0 + /* Driver implementation does not support full duplex. */ + if (dout && din) + return -1; +#endif + ret = config_spi_state(ds, QUP_STATE_RESET); + if (ret != SUCCESS) + return ret; + + write_force_cs(slave, 1); + + if (dout != NULL) { + ret = blsp_spi_write(ds, txp, (unsigned int) out_bytes); + if (ret != SUCCESS) + goto out; + } + + if (din != NULL) { + ret = blsp_spi_read(ds, rxp, in_bytes); + if (ret != SUCCESS) + goto out; + } + +out: + write_force_cs(slave, 0); + + /* + * Put the SPI Core back in the Reset State + * to end the transfer + */ + (void)config_spi_state(ds, QUP_STATE_RESET); + + return ret; +} + +static int spi_ctrlr_setup(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = NULL; + int i; + unsigned int bus = slave->bus; + unsigned int cs = slave->cs; + + if ((bus < BLSP0_SPI) || (bus > BLSP5_SPI) + || ((bus == BLSP0_SPI) && (cs > 2)) + || ((bus == BLSP5_SPI) && (cs > 0))) { + printk(BIOS_ERR, + "SPI error: unsupported bus %d (Supported busses 0, 1 and 2) " + "or chipselect\n", bus); + return -1; + } + + for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) { + if (spi_slave_pool[i].allocated) + continue; + ds = spi_slave_pool + i; + + ds->slave.bus = bus; + ds->slave.cs = cs; + ds->regs = &spi_reg[bus]; + + /* + * TODO(vbendeb): + * hardcoded frequency and mode - we might need to find a way + * to configure this + */ + ds->freq = 10000000; + ds->mode = SPI_MODE0; + ds->allocated = 1; + + return 0; + } + + printk(BIOS_ERR, "SPI error: all %d pools busy\n", i); + return -1; +} + +static int xfer_vectors(const struct spi_slave *slave, + struct spi_op vectors[], size_t count) + { + return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); + } + static const struct spi_ctrlr spi_ctrlr = { + .setup = spi_ctrlr_setup, .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, - .max_xfer_size = 65535, + //.xfer = spi_ctrlr_xfer, + .xfer_vector = xfer_vectors, + .max_xfer_size = MAX_PACKET_COUNT, }; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, + .bus_start = BLSP5_SPI, + .bus_end = BLSP5_SPI, }, }; -#endif - const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/29968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Gerrit-Change-Number: 29968 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: libpayload: Fix uart driver for qcs405 support
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29965 Change subject: libpayload: Fix uart driver for qcs405 support ...................................................................... libpayload: Fix uart driver for qcs405 support Change-Id: Ied54cf5dd13e9ab752533ad07e9ea906f41060b8 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M payloads/libpayload/drivers/serial/ipq40xx.c 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/29965/1 diff --git a/payloads/libpayload/drivers/serial/ipq40xx.c b/payloads/libpayload/drivers/serial/ipq40xx.c index 52d71b8..6ffa3f9 100644 --- a/payloads/libpayload/drivers/serial/ipq40xx.c +++ b/payloads/libpayload/drivers/serial/ipq40xx.c @@ -269,7 +269,7 @@ #define MSM_BOOT_UART_DM_E_RX_NOT_READY 5 #define UART1_DM_BASE ((void *)0x078af000) -#define UART2_DM_BASE ((void *)0x078b0000) +#define UART2_DM_BASE ((void *)0x078b1000) enum { BLSP1_UART1, @@ -288,8 +288,8 @@ * board/qcom/ipq40xx_cdp/ipq40xx_board_param.h */ static const uart_params_t uart_board_param = { - .uart_dm_base = UART1_DM_BASE, - .blsp_uart = BLSP1_UART1, + .uart_dm_base = UART2_DM_BASE, + .blsp_uart = BLSP1_UART2, }; #define write32(addr, val) writel(val, addr) @@ -558,6 +558,8 @@ if (!sc_ptr) return; + msm_boot_uart_dm_init(uart_board_param.uart_dm_base); + consin.havekey = serial_havechar; consin.getchar = serial_getchar; -- To view, visit https://review.coreboot.org/c/coreboot/+/29965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied54cf5dd13e9ab752533ad07e9ea906f41060b8 Gerrit-Change-Number: 29965 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: Coreboot: Add support for USB host mode for mistral platform
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29966 Change subject: Coreboot: Add support for USB host mode for mistral platform ...................................................................... Coreboot: Add support for USB host mode for mistral platform Add required changes for USB host mode working on mistral platform for USB disk enumeration. Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Vijayavardhan Vennapusa <vvreddy(a)partner-android.googlesource.com> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/mainboard/google/mistral/mainboard.c M src/mainboard/google/mistral/romstage.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/include/soc/addressmap.h M src/soc/qualcomm/qcs405/include/soc/clock.h M src/soc/qualcomm/qcs405/include/soc/iomap.h A src/soc/qualcomm/qcs405/include/soc/usb.h A src/soc/qualcomm/qcs405/usb.c 8 files changed, 370 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/29966/1 diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index c249a32..7201874 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -16,10 +16,34 @@ #include <device/device.h> #include <bootblock_common.h> #include <timestamp.h> +#include <soc/usb.h> + +static struct usb_board_data usb0_board_data = { + .parameter_override_x0 = 0x63, + .parameter_override_x1 = 0x03, + .parameter_override_x0 = 0x1d, + .parameter_override_x1 = 0x03, +}; + +static struct usb_board_data usb1_board_data = { + .parameter_override_x0 = 0x63, + .parameter_override_x1 = 0x03, + .parameter_override_x0 = 0x1d, + .parameter_override_x1 = 0x03, +}; + +static void setup_usb(void) +{ + /* Setting Primarty usb controller */ + setup_usb_host(HSUSB_SS_PORT_0, &usb0_board_data); + + /* Setting secondary usb controller */ + setup_usb_host(HSUSB_HS_PORT_1, &usb1_board_data); +} static void mainboard_init(device_t dev) { - + setup_usb(); } static void mainboard_enable(device_t dev) diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c index 71968fc..31e5113 100644 --- a/src/mainboard/google/mistral/romstage.c +++ b/src/mainboard/google/mistral/romstage.c @@ -20,12 +20,19 @@ #include <console/console.h> #include <timestamp.h> #include <arch/stages.h> +#include <soc/usb.h> #ifdef CONFIG_QC_SOC_SIMULATE extern void qcs405_mmu_dram_config_c(void); #endif void platform_romstage_main(void) { + /* + * Do DWC3 core and phy reset. Kick these resets off early + * so they get atleast 1msec to settle. + */ + reset_usb(HSUSB_SS_PORT_0); + reset_usb(HSUSB_HS_PORT_1); #ifdef CONFIG_QC_SOC_SIMULATE qcs405_mmu_dram_config_c(); #endif diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 57d59f8..c174cae 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -27,6 +27,7 @@ romstage-y += mmu.c romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c +romstage-y += usb.c ################################################################################ ramstage-y += soc.c @@ -37,6 +38,7 @@ ramstage-y += clock.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c +ramstage-y += usb.c ################################################################################ diff --git a/src/soc/qualcomm/qcs405/include/soc/addressmap.h b/src/soc/qualcomm/qcs405/include/soc/addressmap.h index 435b680..696bc42 100644 --- a/src/soc/qualcomm/qcs405/include/soc/addressmap.h +++ b/src/soc/qualcomm/qcs405/include/soc/addressmap.h @@ -23,4 +23,12 @@ #define TLMM_NORTH_TILE_BASE 0x1300000 #define TLMM_SOUTH_TILE_BASE 0x1000000 +/* USB BASE ADDRESS */ +#define USB_HOST0_DWC3_BASE 0x758C100 +#define USB3_USB30_QSCRATCH_BASE 0x7678800 +#define USB2_FEMTO_PHY_PRI_BASE 0x007A000 + +#define USB_HOST1_DWC3_BASE 0x78CC100 +#define USB2_USB30_QSCRATCH_BASE 0x79B8800 +#define USB2_FEMTO_PHY_SEC_BASE 0x007C000 #endif /* __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h index aa8bbe5..d02ecd7 100644 --- a/src/soc/qualcomm/qcs405/include/soc/clock.h +++ b/src/soc/qualcomm/qcs405/include/soc/clock.h @@ -65,10 +65,10 @@ /** * USB BCR registers */ -#define GCC_USB_HS_PHY_CFG_AHB_BCR 0x1841038 +#define GCC_USB_HS_PHY_CFG_AHB_BCR 0x180000C #define GCC_USB_HS_BCR 0x1841000 #define GCC_USB_30_BCR 0x1839000 -#define GCC_USB2A_PHY_BCR 0x1841028 +#define GCC_USB2A_PHY_BCR 0x180000C #define GCC_USB2_HS_PHY_ONLY_BCR 0x1841034 #define GCC_QUSB2_PHY_BCR 0x184103C diff --git a/src/soc/qualcomm/qcs405/include/soc/iomap.h b/src/soc/qualcomm/qcs405/include/soc/iomap.h index 2a7a148..571c62f 100644 --- a/src/soc/qualcomm/qcs405/include/soc/iomap.h +++ b/src/soc/qualcomm/qcs405/include/soc/iomap.h @@ -99,14 +99,6 @@ #define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 * (x)) #define GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4) -/* Yes, this is not a typo... host2 is actually mapped before host1. */ -#define USB_HOST2_XHCI_BASE 0x10000000 -#define USB_HOST2_DWC3_BASE 0x1000C100 -#define USB_HOST2_PHY_BASE 0x100F8800 -#define USB_HOST1_XHCI_BASE 0x11000000 -#define USB_HOST1_DWC3_BASE 0x1100C100 -#define USB_HOST1_PHY_BASE 0x110F8800 - #define UART1_DM_BASE ((void *)0x078af000) #define UART2_DM_BASE ((void *)0x078B1000) diff --git a/src/soc/qualcomm/qcs405/include/soc/usb.h b/src/soc/qualcomm/qcs405/include/soc/usb.h new file mode 100644 index 0000000..80674bb --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/usb.h @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <types.h> + +#ifndef _QCS405_USB_H_ +#define _QCS405_USB_H_ + +/* QSCRATCH_GENERAL_CFG register bit offset */ +#define PIPE_UTMI_CLK_SEL BIT(0) +#define PIPE3_PHYSTATUS_SW BIT(3) +#define PIPE_UTMI_CLK_DIS BIT(8) + +/* Global USB3 Control Registers */ +#define DWC3_GUSB3PIPECTL_DELAYP1TRANS BIT(18) +#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX BIT(27) +#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) +#define DWC3_GCTL_PRTCAP_OTG 3 +#define DWC3_GCTL_PRTCAP_HOST 1 + +/* Global USB2 PHY Configuration Register */ +#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) +#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) +#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) +#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) +#define USBTRDTIM_UTMI_8_BIT 9 +#define UTMI_PHYIF_8_BIT 0 + +#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) +#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) +#define DWC3_GCTL_DISSCRAMBLE (1 << 3) +#define DWC3_GCTL_U2EXIT_LFPS (1 << 2) +#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) + +/* USB2 PHY register values */ +#define USB2PHY_TCSR_CTRL 0x01 +#define USB2PHY_REFCLK_CTRL 0x0d +#define USB2PHY_UTMI_CTRL5 0x12 +#define USB2PHY_PARAMETER_OVERRIDE_X0 0x63 +#define USB2PHY_PARAMETER_OVERRIDE_X1 0x03 +#define USB2PHY_PARAMETER_OVERRIDE_X2 0x1d +#define USB2PHY_PARAMETER_OVERRIDE_X3 0x03 +#define USB2PHY_HS_PHY_CTRL1 0x23 +#define QUSB2PHY_HS_PHY_CTRL_COMMON0 0x08 +#define QUSB2PHY_HS_PHY_CTRL_COMMON1 0xdc +#define USB2PHY_HS_PHY_CTRL2 0xe0 + +struct usb_board_data { + /* Register values going to override from the boardfile */ + u8 parameter_override_x0; + u8 parameter_override_x1; + u8 parameter_override_x2; + u8 parameter_override_x3; +}; + +enum usb_port { + HSUSB_SS_PORT_0, + HSUSB_HS_PORT_1, +}; + +void setup_usb_host(enum usb_port port, struct usb_board_data *data); +/* Call reset_ before setup_ */ +void reset_usb(enum usb_port port); + +#endif /* _QCS405_USB_H_ */ diff --git a/src/soc/qualcomm/qcs405/usb.c b/src/soc/qualcomm/qcs405/usb.c new file mode 100644 index 0000000..67574cf --- /dev/null +++ b/src/soc/qualcomm/qcs405/usb.c @@ -0,0 +1,250 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <lib.h> +#include <stdlib.h> +#include <console/console.h> +#include <delay.h> +#include <soc/usb.h> +#include <soc/clock.h> +#include <soc/addressmap.h> +#include <timer.h> + +struct usb_qscratch { + u8 rsvd0[8]; + u32 *qscratch_cfg_reg; + +}; +check_member(usb_qscratch, qscratch_cfg_reg, 0x08); + +struct usb_usb2_phy_dig { + u8 rsvd1[116]; + u32 utmi_ctrl5; + u32 ctrl_common0; + u32 ctrl_common1; + u8 rsvd2[12]; + u32 phy_ctrl1; + u32 phy_ctrl2; + u8 rsvd3; + u32 override_x0; + u32 override_x1; + u32 override_x2; + u32 override_x3; + u8 rsvd4[24]; + u32 tcsr_ctrl; + u8 rsvd5[36]; + u32 refclk_ctrl; +}; +check_member(usb_usb2_phy_dig, utmi_ctrl5, 0x74); +check_member(usb_usb2_phy_dig, phy_ctrl1, 0x8C); +check_member(usb_usb2_phy_dig, override_x0, 0x98); +check_member(usb_usb2_phy_dig, tcsr_ctrl, 0xC0); +check_member(usb_usb2_phy_dig, refclk_ctrl, 0xE8); + +struct usb_dwc3 { + u32 sbuscfg0; + u32 sbuscfg1; + u32 txthrcfg; + u32 rxthrcfg; + u32 ctl; + u32 pmsts; + u32 sts; + u32 uctl1; + u32 snpsid; + u32 gpio; + u32 uid; + u32 uctl; + u64 buserraddr; + u64 prtbimap; + u8 reserved1[32]; + u32 dbgfifospace; + u32 dbgltssm; + u32 dbglnmcc; + u32 dbgbmu; + u32 dbglspmux; + u32 dbglsp; + u32 dbgepinfo0; + u32 dbgepinfo1; + u64 prtbimap_hs; + u64 prtbimap_fs; + u8 reserved2[112]; + u32 usb2phycfg; + u8 reserved3[60]; + u32 usb2i2cctl; + u8 reserved4[60]; + u32 usb2phyacc; + u8 reserved5[60]; + u32 usb3pipectl; + u8 reserved6[60]; +}; +check_member(usb_dwc3, usb3pipectl, 0x1c0); + +struct usb_dwc3_cfg { + struct usb_dwc3 *usb_host_dwc3; + struct usb_usb2_phy_dig *usb2_phy_dig; + struct usb_qscratch *usb_qscratch_reg; + u32 *usb2_phy_bcr; + u32 *usb2_phy_por_bcr; + u32 *usb3_bcr; + struct usb_board_data *board_data; +}; + +static struct usb_dwc3_cfg usb_host_base[2] = { + [HSUSB_SS_PORT_0] = { + .usb_host_dwc3 = (void *)USB_HOST0_DWC3_BASE, + .usb2_phy_dig = (void *)USB2_FEMTO_PHY_PRI_BASE, + .usb2_phy_bcr = (void *)GCC_USB_HS_PHY_CFG_AHB_BCR, + .usb2_phy_por_bcr = (void *)GCC_USB2A_PHY_BCR, + .usb3_bcr = (void *)GCC_USB_30_BCR, + .usb_qscratch_reg = (void *)USB3_USB30_QSCRATCH_BASE, + }, + [HSUSB_HS_PORT_1] = { + .usb_host_dwc3 = (void *)USB_HOST1_DWC3_BASE, + .usb2_phy_dig = (void *)USB2_FEMTO_PHY_SEC_BASE, + .usb2_phy_bcr = (void *)GCC_QUSB2_PHY_BCR, + .usb2_phy_por_bcr = (void *)GCC_USB2_HS_PHY_ONLY_BCR, + .usb3_bcr = (void *)GCC_USB_HS_BCR, + .usb_qscratch_reg = (void *)USB2_USB30_QSCRATCH_BASE, + }, +}; + +void reset_usb(enum usb_port port) +{ + struct usb_dwc3_cfg *dwc3 = &usb_host_base[port]; + + /* Put Core in Reset */ + printk(BIOS_INFO, "Starting DWC3 reset for USB%d\n", port); + + /* Assert Core reset */ + clock_reset_bcr(dwc3->usb3_bcr, 1); +} + +static void usb2_phy_override_phy_params(struct usb_dwc3_cfg *dwc3) +{ + write8(&dwc3->usb2_phy_dig->override_x0, dwc3->board_data->parameter_override_x0); + write8(&dwc3->usb2_phy_dig->override_x1, dwc3->board_data->parameter_override_x1); + write8(&dwc3->usb2_phy_dig->override_x2, dwc3->board_data->parameter_override_x2); + write8(&dwc3->usb2_phy_dig->override_x3, dwc3->board_data->parameter_override_x3); +} + +static void hs_usb_phy_init(struct usb_dwc3_cfg *dwc3) +{ + write8(&dwc3->usb2_phy_dig->tcsr_ctrl, USB2PHY_TCSR_CTRL); + write8(&dwc3->usb2_phy_dig->refclk_ctrl, USB2PHY_REFCLK_CTRL); + write8(&dwc3->usb2_phy_dig->utmi_ctrl5, USB2PHY_UTMI_CTRL5); + write8(&dwc3->usb2_phy_dig->override_x0, USB2PHY_PARAMETER_OVERRIDE_X0); + write8(&dwc3->usb2_phy_dig->override_x1, USB2PHY_PARAMETER_OVERRIDE_X1); + write8(&dwc3->usb2_phy_dig->override_x2, USB2PHY_PARAMETER_OVERRIDE_X2); + write8(&dwc3->usb2_phy_dig->override_x3, USB2PHY_PARAMETER_OVERRIDE_X3); + + if (dwc3->board_data) + /* Overridw board specific PHY tuning values */ + usb2_phy_override_phy_params(dwc3); + + write8(&dwc3->usb2_phy_dig->phy_ctrl1, USB2PHY_HS_PHY_CTRL1); + write8(&dwc3->usb2_phy_dig->ctrl_common0, QUSB2PHY_HS_PHY_CTRL_COMMON0); + write8(&dwc3->usb2_phy_dig->ctrl_common1, QUSB2PHY_HS_PHY_CTRL_COMMON1); + write8(&dwc3->usb2_phy_dig->phy_ctrl2, USB2PHY_HS_PHY_CTRL2); + udelay(20); + write8(&dwc3->usb2_phy_dig->utmi_ctrl5, 0x10); + write8(&dwc3->usb2_phy_dig->phy_ctrl2, 0x60); +} + +static void setup_dwc3(struct usb_dwc3 *dwc3) +{ + /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ + clrsetbits_le32(&dwc3->usb3pipectl, + DWC3_GUSB3PIPECTL_DELAYP1TRANS, + DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); + + clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | + DWC3_GCTL_DISSCRAMBLE), + DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); + + /* configure controller in Host mode */ + clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), + DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); + printk(BIOS_INFO, "Configure USB in Host mode\n"); +} + +/* Initialization of DWC3 Core and PHY */ +void setup_usb_host(enum usb_port port, struct usb_board_data *board_data) +{ + struct usb_dwc3_cfg *dwc3 = &usb_host_base[port]; + u32 val; + + printk(BIOS_INFO, "Setting up USB HOST%d controller.\n", port); + + dwc3->board_data = board_data; + + /* Clear core reset. */ + clock_reset_bcr(dwc3->usb3_bcr, 0); + + + if (port == HSUSB_SS_PORT_0) { + /* Set PHY reset. */ + setbits_le32(&dwc3->usb2_phy_bcr, BIT(1)); + udelay(15); + /* Clear PHY reset. */ + clrbits_le32(&dwc3->usb2_phy_bcr, BIT(1)); + } else { + clock_reset_bcr(dwc3->usb2_phy_bcr, 1); + udelay(15); + clock_reset_bcr(dwc3->usb2_phy_bcr, 0); + } + udelay(100); + + /* Initialize PHYs */ + hs_usb_phy_init(dwc3); + + if (port == HSUSB_SS_PORT_0) { + /* Set PHY POR reset. */ + setbits_le32(&dwc3->usb2_phy_por_bcr, BIT(0)); + val = read8(&dwc3->usb2_phy_dig->ctrl_common0); + val &= ~(0x4); + write8(&dwc3->usb2_phy_dig->ctrl_common0, val); + udelay(20); + /* Clear PHY POR reset. */ + clrbits_le32(&dwc3->usb2_phy_por_bcr, BIT(0)); + } else { + clock_reset_bcr(dwc3->usb2_phy_por_bcr, 1); + val = read8(&dwc3->usb2_phy_dig->ctrl_common0); + val &= ~(0x4); + write8(&dwc3->usb2_phy_dig->ctrl_common0, val); + udelay(20); + clock_reset_bcr(dwc3->usb2_phy_por_bcr, 0); + } + udelay(100); + + setup_dwc3(dwc3->usb_host_dwc3); + + /* + * Below sequence is used when dwc3 operates without + * SSPHY and only HS/FS/LS modes are supported. + */ + + /* Configure dwc3 to use UTMI clock as PIPE clock not present */ + setbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, + PIPE_UTMI_CLK_DIS); + udelay(2); + setbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, + PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW); + udelay(3); + clrbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, + PIPE_UTMI_CLK_DIS); + + printk(BIOS_INFO, "DWC3 and PHY setup finished\n"); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Gerrit-Change-Number: 29966 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: Add blsp uart driver
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29964 Change subject: qcs405: Add blsp uart driver ...................................................................... qcs405: Add blsp uart driver Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Prudhvi Yarlagadda<pyarlaga(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/include/soc/blsp.h A src/soc/qualcomm/qcs405/include/soc/cdp.h A src/soc/qualcomm/qcs405/include/soc/iomap.h A src/soc/qualcomm/qcs405/include/soc/ipq_uart.h A src/soc/qualcomm/qcs405/uart.c 6 files changed, 976 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/29964/1 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 58a62fa..57d59f8 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -8,14 +8,14 @@ bootblock-y += timer.c bootblock-y += gpio.c bootblock-y += clock.c -bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +bootblock-$(CONFIG_DRIVERS_UART) += uart.c bootblock-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ verstage-y += spi.c verstage-y += timer.c verstage-y += gpio.c -verstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +verstage-$(CONFIG_DRIVERS_UART) += uart.c verstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ @@ -25,7 +25,7 @@ romstage-y += gpio.c romstage-y += clock.c romstage-y += mmu.c -romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ @@ -35,7 +35,7 @@ ramstage-y += timer.c ramstage-y += gpio.c ramstage-y += clock.c -ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ diff --git a/src/soc/qualcomm/qcs405/include/soc/blsp.h b/src/soc/qualcomm/qcs405/include/soc/blsp.h new file mode 100644 index 0000000..ce74e56 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/blsp.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2011-2012 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef __BLSP_H_ +#define __BLSP_H_ + +typedef enum { + BLSP_QUP_ID_0, + BLSP_QUP_ID_1, + BLSP_QUP_ID_2, + BLSP_QUP_ID_3, +} blsp_qup_id_t; + +typedef enum { + BLSP_SUCCESS = 0, + BLSP_ID_ERROR, + BLSP_ERROR, + BLSP_UNSUPPORTED +} blsp_return_t; + +typedef enum { + BLSP_PROTO_I2C_UIM = 1, + BLSP_PROTO_I2C_ONLY, + BLSP_PROTO_SPI_ONLY, + BLSP_PROTO_UART_FLOW_CTL, + BLSP_PROTO_UIM, + BLSP_PROTO_I2C_UART, +} blsp_protocol_t; + +blsp_return_t blsp_i2c_init(blsp_qup_id_t id); +int blsp_i2c_init_board(blsp_qup_id_t id); + +#endif diff --git a/src/soc/qualcomm/qcs405/include/soc/cdp.h b/src/soc/qualcomm/qcs405/include/soc/cdp.h new file mode 100644 index 0000000..ca9e996 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/cdp.h @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2012 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _IPQ40XX_CDP_H_ +#define _IPQ40XX_CDP_H_ + +#include <types.h> + +unsigned smem_get_board_machtype(void); + +typedef enum { + PHY_INTERFACE_MODE_MII, + PHY_INTERFACE_MODE_GMII, + PHY_INTERFACE_MODE_SGMII, + PHY_INTERFACE_MODE_QSGMII, + PHY_INTERFACE_MODE_TBI, + PHY_INTERFACE_MODE_RMII, + PHY_INTERFACE_MODE_RGMII, + PHY_INTERFACE_MODE_RGMII_ID, + PHY_INTERFACE_MODE_RGMII_RXID, + PHY_INTERFACE_MODE_RGMII_TXID, + PHY_INTERFACE_MODE_RTBI, + PHY_INTERFACE_MODE_XGMII, + PHY_INTERFACE_MODE_NONE /* Must be last */ +} phy_interface_t; + +typedef struct { + gpio_t gpio; + unsigned int func; + unsigned int dir; + unsigned int pull; + unsigned int drvstr; + unsigned int enable; +} gpio_func_data_t; + +typedef struct { + unsigned int m_value; + unsigned int n_value; + unsigned int d_value; +} uart_clk_mnd_t; + +/* SPI Mode */ + +typedef enum { + NOR_SPI_MODE_0, + NOR_SPI_MODE_1, + NOR_SPI_MODE_2, + NOR_SPI_MODE_3, +} spi_mode; + +/* SPI GSBI Bus number */ + +typedef enum { + GSBI_BUS_5 = 0, + GSBI_BUS_6, + GSBI_BUS_7, +} spi_gsbi_bus_num; + +/* SPI Chip selects */ + +typedef enum { + SPI_CS_0 , + SPI_CS_1, + SPI_CS_2, + SPI_CS_3, +} spi_cs; + +/* Flash Types */ + +typedef enum { + ONLY_NAND, + ONLY_NOR, + NAND_NOR, + NOR_MMC, +} flash_desc; + +#define NO_OF_DBG_UART_GPIOS 2 + +#define SPI_NOR_FLASH_VENDOR_MICRON 0x1 +#define SPI_NOR_FLASH_VENDOR_SPANSION 0x2 + +/* SPI parameters */ + +typedef struct { + spi_mode mode; + spi_gsbi_bus_num bus_number; + spi_cs chip_select; + int vendor; +} spinorflash_params_t; + +typedef struct { + unsigned count; + uint8_t addr[7]; +} ipq_gmac_phy_addr_t; + +typedef struct { + unsigned base; + int unit; + unsigned is_macsec; + unsigned mac_pwr0; + unsigned mac_pwr1; + unsigned mac_conn_to_phy; + phy_interface_t phy; + ipq_gmac_phy_addr_t phy_addr; +} ipq_gmac_board_cfg_t; + +#define IPQ_GMAC_NMACS 4 + +enum gale_board_id { + BOARD_ID_GALE_PROTO = 0, + BOARD_ID_GALE_EVT = 1, + BOARD_ID_GALE_EVT2_0 = 2, + BOARD_ID_GALE_EVT2_1 = 6, + BOARD_ID_GALE_EVT3 = 5, +}; + +/* Board specific parameters */ +typedef struct { +#if 0 + unsigned int gmac_gpio_count; + gpio_func_data_t *gmac_gpio; + ipq_gmac_board_cfg_t gmac_cfg[IPQ_GMAC_NMACS]; + flash_desc flashdesc; + spinorflash_params_t flash_param; +#endif +} __packed board_ipq40xx_params_t; + +extern board_ipq40xx_params_t *gboard_param; + +#if 0 +static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg) +{ + /* + * 'cfg' is valid if and only if + * unit number is non-negative and less than IPQ_GMAC_NMACS. + * 'cfg' pointer lies within the array range of + * board_ipq40xx_params_t->gmac_cfg[] + */ + return ((cfg >= &gboard_param->gmac_cfg[0]) && + (cfg < &gboard_param->gmac_cfg[IPQ_GMAC_NMACS]) && + (cfg->unit >= 0) && (cfg->unit < IPQ_GMAC_NMACS)); +} +#endif + +unsigned int get_board_index(unsigned machid); +void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count); + +#endif /* _IPQ40XX_CDP_H_ */ diff --git a/src/soc/qualcomm/qcs405/include/soc/iomap.h b/src/soc/qualcomm/qcs405/include/soc/iomap.h new file mode 100644 index 0000000..2a7a148 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/iomap.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2012 - 2013, 2015 The Linux Foundation. All rights reserved. + * + * Copyright (c) 2008, Google Inc. + * All rights reserved. + * + * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google, Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __SOC_QUALCOMM_IPQ40XX_IOMAP_H_ +#define __SOC_QUALCOMM_IPQ40XX_IOMAP_H_ + +#include <arch/io.h> +#include <soc/cdp.h> +#include <soc/blsp.h> + +/* Typecast to allow integers being passed as address + This needs to be included because vendor code is not compliant with our + macros for read/write. Hence, special macros for readl_i and writel_i are + included to do this in one place for all occurrences in vendor code + */ +#define readl_i(a) read32((const void *)(a)) +#define writel_i(v,a) write32((void *)a, v) +#define clrsetbits_le32_i(addr, clear, set) \ + clrsetbits_le32(((void *)(addr)), (clear), (set)) + +#define GCC_CLK_CTL_REG ((void *)0x01800000u) +#define MSM_CLK_CTL_BASE GCC_CLK_CTL_REG +#define GCC_CLK_BRANCH_ENA (GCC_CLK_CTL_REG + 0x6000) +#define IMEM_AXI (1 << 17) +#define SYS_NOC_APSS_AHB (1 << 16) +#define BIMC_AXI_M0 (1 << 15) +#define APSS_AHB (1 << 14) +#define APSS_AXI (1 << 13) +#define MPM_AHB (1 << 12) +#define GMEM_SYS_NOC_AXI (1 << 11) +#define BLSP1_AHB (1 << 10) +#define BLSP1_SLEEP (1 << 9) +#define PRNG_AHB (1 << 8) +#define BOOT_ROM_AHB (1 << 7) +#define MSG_RAM_AHB (1 << 6) +#define TLMM_AHB (1 << 5) +#define TLMM (1 << 4) +#define SPMI_PCNOC_AHB (1 << 3) +#define CRYPTO (1 << 2) +#define CRYPTO_AXI (1 << 1) +#define CRYPTO_AHB (1 << 0) + +#define GCC_BLSP1_QUP1_I2C_APPS_CBCR (MSM_CLK_CTL_BASE + 0x2008) +#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR (MSM_CLK_CTL_BASE + 0x200c) +#define GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR (MSM_CLK_CTL_BASE + 0x2010) +#define GCC_BLSP1_QUP2_I2C_APPS_CBCR (MSM_CLK_CTL_BASE + 0x3010) +#define GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR (MSM_CLK_CTL_BASE + 0x3000) +#define GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR (MSM_CLK_CTL_BASE + 0x3004) + +#define GCNT_GLOBAL_CTRL_BASE ((void *)0x004a0000u) +#define GCNT_CNTCR (GCNT_GLOBAL_CTRL_BASE + 0x1000) +#define GCNT_GLB_CNTCV_LO (GCNT_GLOBAL_CTRL_BASE + 0x1008) +#define GCNT_GLB_CNTCV_HI (GCNT_GLOBAL_CTRL_BASE + 0x100c) +#define GCNT_CNTCV_LO (GCNT_GLOBAL_CTRL_BASE + 0x2000) +#define GCNT_CNTCV_HI (GCNT_GLOBAL_CTRL_BASE + 0x2004) + +#define GCNT_PSHOLD ((void *)0x004AB000u) + +/* RPM interface constants */ +#define RPM_INT ((void *)0x63020) +#define RPM_INT_ACK ((void *)0x63060) +#define RPM_SIGNAL_COOKIE ((void *)0x47C20) +#define RPM_SIGNAL_ENTRY ((void *)0x47C24) +#define RPM_FW_MAGIC_NUM 0x4D505242 + +#define TLMM_BASE_ADDR ((void *)0x01000000) +#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 * (x)) +#define GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4) + +/* Yes, this is not a typo... host2 is actually mapped before host1. */ +#define USB_HOST2_XHCI_BASE 0x10000000 +#define USB_HOST2_DWC3_BASE 0x1000C100 +#define USB_HOST2_PHY_BASE 0x100F8800 +#define USB_HOST1_XHCI_BASE 0x11000000 +#define USB_HOST1_DWC3_BASE 0x1100C100 +#define USB_HOST1_PHY_BASE 0x110F8800 + +#define UART1_DM_BASE ((void *)0x078af000) +#define UART2_DM_BASE ((void *)0x078B1000) + +enum { + BLSP1_UART1, + BLSP1_UART2, +}; + +#define GCC_BLSP1_UART_BCR_BASE (GCC_CLK_CTL_REG + 0x2038) +#define GCC_BLSP1_UART_BCR(x) (GCC_BLSP1_UART_BCR_BASE + (x) * 0xff0) +#define GCC_BLSP1_UART_APPS_CBCR(x) (GCC_BLSP1_UART_BCR(x) + 4) +#define GCC_BLSP1_UART_APPS_CMD_RCGR(x) (GCC_BLSP1_UART_APPS_CBCR(x) + 8) +#define GCC_BLSP1_UART_APPS_CFG_RCGR(x) (GCC_BLSP1_UART_APPS_CMD_RCGR(x) + 4) +#define GCC_BLSP1_UART_APPS_M(x) (GCC_BLSP1_UART_APPS_CFG_RCGR(x) + 4) +#define GCC_BLSP1_UART_APPS_N(x) (GCC_BLSP1_UART_APPS_M(x) + 4) +#define GCC_BLSP1_UART_APPS_D(x) (GCC_BLSP1_UART_APPS_N(x) + 4) +#define GCC_BLSP1_UART_MISC(x) (GCC_BLSP1_UART_APPS_D(x) + 4) + +#define BLSP1_QUP0_BASE ((void *)0x078B5000) +#define BLSP1_QUP1_BASE ((void *)0x078B6000) +#define BLSP1_QUP2_BASE ((void *)0x078B7000) +#define BLSP1_QUP3_BASE ((void *)0x078B8000) + +#define TCSR_BOOT_MISC_DETECT ((void *)0x0193D100) +#define TCSR_RESET_DEBUG_SW_ENTRY ((void *)0x01940000) + +static inline void *blsp_qup_base(blsp_qup_id_t id) +{ + switch (id) { + case BLSP_QUP_ID_0: return BLSP1_QUP0_BASE; + case BLSP_QUP_ID_1: return BLSP1_QUP1_BASE; + case BLSP_QUP_ID_2: return BLSP1_QUP2_BASE; + case BLSP_QUP_ID_3: return BLSP1_QUP3_BASE; + } + return NULL; +} + +#define BLSP_MINI_CORE_SHIFT 8 +#define BLSP_MINI_CORE_I2C (0x2u << BLSP_MINI_CORE_SHIFT) +#define BLSP_MINI_CORE_MASK (0xfu << BLSP_MINI_CORE_SHIFT) + +#define ETIMEDOUT -10 +#define EINVAL -11 +#define EIO -12 + +#endif // __SOC_QUALCOMM_IPQ40XX_IOMAP_H_ diff --git a/src/soc/qualcomm/qcs405/include/soc/ipq_uart.h b/src/soc/qualcomm/qcs405/include/soc/ipq_uart.h new file mode 100644 index 0000000..8cb0f25 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/ipq_uart.h @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2012 The Linux Foundation. All rights reserved.* + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __UART_DM_H__ +#define __UART_DM_H__ + +#define PERIPH_BLK_BLSP 1 + +#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \ + ((value << (32 - end_pos)) >> (32 - (end_pos - start_pos))) + +extern void __udelay(unsigned long usec); + + +enum MSM_BOOT_UART_DM_PARITY_MODE { + MSM_BOOT_UART_DM_NO_PARITY, + MSM_BOOT_UART_DM_ODD_PARITY, + MSM_BOOT_UART_DM_EVEN_PARITY, + MSM_BOOT_UART_DM_SPACE_PARITY +}; + +/* UART Stop Bit Length */ +enum MSM_BOOT_UART_DM_STOP_BIT_LEN { + MSM_BOOT_UART_DM_SBL_9_16, + MSM_BOOT_UART_DM_SBL_1, + MSM_BOOT_UART_DM_SBL_1_9_16, + MSM_BOOT_UART_DM_SBL_2 +}; + +/* UART Bits per Char */ +enum MSM_BOOT_UART_DM_BITS_PER_CHAR { + MSM_BOOT_UART_DM_5_BPS, + MSM_BOOT_UART_DM_6_BPS, + MSM_BOOT_UART_DM_7_BPS, + MSM_BOOT_UART_DM_8_BPS +}; + +/* 8-N-1 Configuration */ +#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \ + (MSM_BOOT_UART_DM_SBL_1 << 2) | \ + (MSM_BOOT_UART_DM_8_BPS << 4)) + +/* UART_DM Registers */ + +/* UART Operational Mode Register */ +#define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00) +#define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04) +#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8) +#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7) + +/* UART Clock Selection Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) +#else +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) +#endif + +/* UART DM TX FIFO Registers - 4 */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x))) +#else +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x))) +#endif + +/* UART Command Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8) +#else +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10) +#endif +#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0) +#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1) +#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2) +#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3) + +/* UART Channel Command */ +#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4) +#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4) << 11) +#define MSM_BOOT_UART_DM_CR_CH_CMD(x) \ + (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x)) +#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0) +#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1) +#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2) +#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3) +#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4) +#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5) +#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6) +#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7) +#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8) +#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9) +#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C) +#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D) +#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E) +#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10) +#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11) +#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12) +#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13) +#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14) + +/*UART General Command */ +#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8) + +#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2) +#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3) +#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4) +#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5) +#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6) + +/* UART Interrupt Mask Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0) +#else +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14) +#endif + +#define MSM_BOOT_UART_DM_TXLEV (1 << 0) +#define MSM_BOOT_UART_DM_RXHUNT (1 << 1) +#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2) +#define MSM_BOOT_UART_DM_RXSTALE (1 << 3) +#define MSM_BOOT_UART_DM_RXLEV (1 << 4) +#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5) +#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6) +#define MSM_BOOT_UART_DM_TX_READY (1 << 7) +#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8) +#define MSM_BOOT_UART_DM_TX_DONE (1 << 9) +#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10) +#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11) +#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12) + +#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \ + MSM_BOOT_UART_DM_TXLEV | \ + MSM_BOOT_UART_DM_RXSTALE) + +/* UART Interrupt Programming Register */ +#define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18) +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */ + +/* UART Transmit/Receive FIFO Watermark Register */ +#define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C) +/* Interrupt is generated when FIFO level is less than or equal to this value */ +#define MSM_BOOT_UART_DM_TFW_VALUE 0 + +#define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20) +/*Interrupt generated when no of words in RX FIFO is greater than this value */ +#define MSM_BOOT_UART_DM_RFW_VALUE 0 + +/* UART Hunt Character Register */ +#define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24) + +/* Used for RX transfer initialization */ +#define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34) + +/* Default DMRX value - any value bigger than FIFO size would be fine */ +#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220 + +/* Register to enable IRDA function */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8) +#else +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38) +#endif + +/* UART Data Mover Enable Register */ +#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C) + +/* Number of characters for Transmission */ +#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040) + +/* UART RX FIFO Base Address */ +#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44) + +/* UART Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4) +#else +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008) +#endif +#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0) +#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1) +#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2) +#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3) +#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4) +#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5) +#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6) +#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7) +#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8) + +/* UART Receive FIFO Registers - 4 in numbers */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x))) +#else +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x))) +#endif + +/* UART Masked Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC) +#else +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10) +#endif + +/* UART Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4) +#else +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14) +#endif + +/* Number of characters received since the end of last RX transfer */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC) +#else +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38) +#endif + +/* UART TX FIFO Status Register */ +#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C) +#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6) +#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31) +#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9) +#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13) + +/* UART RX FIFO Status Register */ +#define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50) +#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6) +#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31) +#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9) +#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13) + +/* Macros for Common Errors */ +#define MSM_BOOT_UART_DM_E_SUCCESS 0 +#define MSM_BOOT_UART_DM_E_FAILURE 1 +#define MSM_BOOT_UART_DM_E_TIMEOUT 2 +#define MSM_BOOT_UART_DM_E_INVAL 3 +#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4 +#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5 + +void ipq40xx_uart_init(void); + +#endif /* __UART_DM_H__ */ diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c new file mode 100644 index 0000000..7cdc29f --- /dev/null +++ b/src/soc/qualcomm/qcs405/uart.c @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2012 The Linux Foundation. All rights reserved. + * Source : APQ8064 LK boot + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <console/uart.h> +#include <delay.h> +#include <gpio.h> +#include <soc/clock.h> +#include <soc/blsp.h> +#include <soc/ipq_uart.h> +#include <soc/cdp.h> +#include <stdint.h> +#include <stdlib.h> +#include <soc/iomap.h> + +#define FIFO_DATA_SIZE 4 + +typedef struct { + void *uart_dm_base; + //uart_clk_mnd_t mnd_value; + unsigned blsp_uart; + gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS]; +} uart_params_t; + +void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count) +{ + int i; + + for (i = 0; i < count; i++) { + gpio_configure(gpio->gpio, gpio->func, + gpio->pull, gpio->drvstr, gpio->enable); + gpio++; + } +} + +static const uart_params_t uart_board_param = { + .uart_dm_base = UART2_DM_BASE, + //.mnd_value = { 24, 625, 313 }, + .blsp_uart = BLSP1_UART2, + .dbg_uart_gpio = { + { + .gpio = GPIO(17), + .func = 1, + .dir = GPIO_OUTPUT, + .pull = GPIO_PULL_UP, + .enable = GPIO_OUTPUT + }, + { + .gpio = GPIO(18), + .func = 1, + .dir = GPIO_INPUT, + .pull = GPIO_NO_PULL, + .enable = GPIO_INPUT + }, + }, +}; + +/** + * @brief msm_boot_uart_dm_init_rx_transfer - Init Rx transfer + * @param uart_dm_base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base) +{ + /* Reset receiver */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CMD_RESET_RX); + + /* Enable receiver */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CR_RX_ENABLE); + write32(MSM_BOOT_UART_DM_DMRX(uart_dm_base), + MSM_BOOT_UART_DM_DMRX_DEF_VALUE); + + /* Clear stale event */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CMD_RES_STALE_INT); + + /* Enable stale event */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT); + + return MSM_BOOT_UART_DM_E_SUCCESS; +} + +#if IS_ENABLED(CONFIG_DRIVERS_UART) +static unsigned int msm_boot_uart_dm_init(void *uart_dm_base); + +/* Received data is valid or not */ +static int valid_data = 0; + +/* Received data */ +static unsigned int word = 0; + + +void uart_tx_byte(int idx, unsigned char data) +{ + int num_of_chars = 1; + void *base = uart_board_param.uart_dm_base; + + /* Wait until transmit FIFO is empty. */ + while (!(read32(MSM_BOOT_UART_DM_SR(base)) & + MSM_BOOT_UART_DM_SR_TXEMT)) + udelay(1); + /* + * TX FIFO is ready to accept new character(s). First write number of + * characters to be transmitted. + */ + write32(MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base), num_of_chars); + + /* And now write the character(s) */ + write32(MSM_BOOT_UART_DM_TF(base, 0), data); +} +#endif /* CONFIG_SERIAL_UART */ + +/** + * @brief msm_boot_uart_dm_reset - resets UART controller + * @param base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_reset(void *base) +{ + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_RX); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_TX); + write32(MSM_BOOT_UART_DM_CR(base), + MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_TX_ERR); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_STALE_INT); + + return MSM_BOOT_UART_DM_E_SUCCESS; +} + +/** + * @brief msm_boot_uart_dm_init - initilaizes UART controller + * @param uart_dm_base: UART controller base address + */ +unsigned int msm_boot_uart_dm_init(void *uart_dm_base) +{ + /* Configure UART mode registers MR1 and MR2 */ + /* Hardware flow control isn't supported */ + write32(MSM_BOOT_UART_DM_MR1(uart_dm_base), 0x0); + + /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */ + write32(MSM_BOOT_UART_DM_MR2(uart_dm_base), + MSM_BOOT_UART_DM_8_N_1_MODE); + + /* Configure Interrupt Mask register IMR */ + write32(MSM_BOOT_UART_DM_IMR(uart_dm_base), + MSM_BOOT_UART_DM_IMR_ENABLED); + + /* + * Configure Tx and Rx watermarks configuration registers + * TX watermark value is set to 0 - interrupt is generated when + * FIFO level is less than or equal to 0 + */ + write32(MSM_BOOT_UART_DM_TFWR(uart_dm_base), + MSM_BOOT_UART_DM_TFW_VALUE); + + /* RX watermark value */ + write32(MSM_BOOT_UART_DM_RFWR(uart_dm_base), + MSM_BOOT_UART_DM_RFW_VALUE); + + /* Configure Interrupt Programming Register */ + /* Set initial Stale timeout value */ + write32(MSM_BOOT_UART_DM_IPR(uart_dm_base), + MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB); + + /* Configure IRDA if required */ + /* Disabling IRDA mode */ + write32(MSM_BOOT_UART_DM_IRDA(uart_dm_base), 0x0); + + /* Configure hunt character value in HCR register */ + /* Keep it in reset state */ + write32(MSM_BOOT_UART_DM_HCR(uart_dm_base), 0x0); + + /* + * Configure Rx FIFO base address + * Both TX/RX shares same SRAM and default is half-n-half. + * Sticking with default value now. + * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries). + * We have found RAM_ADDR_WIDTH = 0x7f + */ + + /* Issue soft reset command */ + msm_boot_uart_dm_reset(uart_dm_base); + + /* Enable/Disable Rx/Tx DM interfaces */ + /* Data Mover not currently utilized. */ + write32(MSM_BOOT_UART_DM_DMEN(uart_dm_base), 0x0); + + /* Enable transmitter */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CR_TX_ENABLE); + + /* Initialize Receive Path */ + msm_boot_uart_dm_init_rx_transfer(uart_dm_base); + + return 0; +} + +/** + * @brief ipq40xx_uart_init - initializes UART + * + * Initializes clocks, GPIO and UART controller. + */ +void uart_init(int idx) +{ + /* Note int idx isn't used in this driver. */ + void *dm_base; + + dm_base = uart_board_param.uart_dm_base; + + if (read32(MSM_BOOT_UART_DM_CSR(dm_base)) == 0xFF) + return; /* UART must have been already initialized. */ + + ipq_configure_gpio(uart_board_param.dbg_uart_gpio, + NO_OF_DBG_UART_GPIOS); + + /* TODO: Configure the uart clock */ + /*uart_clock_config(uart_board_param.blsp_uart, + uart_board_param.mnd_value.m_value, + uart_board_param.mnd_value.n_value, + uart_board_param.mnd_value.d_value);*/ + + write32(MSM_BOOT_UART_DM_CSR(dm_base), 0xFF); + + /* Initialize UART_DM */ + msm_boot_uart_dm_init(dm_base); +} + +/* for the benefit of non-console uart init */ +void ipq40xx_uart_init(void) +{ + uart_init(0); +} + +/** + * @brief uart_tx_flush - transmits a string of data + * @param idx: string to transmit + */ +void uart_tx_flush(int idx) +{ + void *base = uart_board_param.uart_dm_base; + + while (!(read32(MSM_BOOT_UART_DM_SR(base)) & + MSM_BOOT_UART_DM_SR_TXEMT)) + ; +} + +#if IS_ENABLED(CONFIG_DRIVERS_UART) +/** + * ipq40xx_serial_getc - reads a character + * + * Returns the character read from serial port. + */ +uint8_t uart_rx_byte(int idx) +{ + uint8_t byte; + + byte = (uint8_t)(word & 0xff); + word = word >> 8; + valid_data--; + + return byte; +} +#endif + +#ifndef __PRE_RAM__ +/* TODO: Implement function */ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = (uint64_t)UART2_DM_BASE; + serial.baud = get_uart_baudrate(); + serial.regwidth = 1; + + lb_add_serial(&serial, data); + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/29964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Gerrit-Change-Number: 29964 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qcs405: Adding the GPIO support for QCS405
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29963 Change subject: qcs405: Adding the GPIO support for QCS405 ...................................................................... qcs405: Adding the GPIO support for QCS405 Add the gpio data for all qcs405 pins Change-Id: Ibdd675527458e597c1f49544425146bd17f28075 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Pranav Agrawal <pranava(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/include/soc/gpio.h 1 file changed, 184 insertions(+), 218 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29963/1 diff --git a/src/soc/qualcomm/qcs405/include/soc/gpio.h b/src/soc/qualcomm/qcs405/include/soc/gpio.h index f436595..b12ebb1 100644 --- a/src/soc/qualcomm/qcs405/include/soc/gpio.h +++ b/src/soc/qualcomm/qcs405/include/soc/gpio.h @@ -98,247 +98,213 @@ GPIO##index##_FUNC_##func7 = 7 enum { - PIN(0, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(1, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(2, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(3, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(4, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(5, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(6, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(7, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(8, EAST, QUP_L4_0_CS, GP_PDM_MIRB, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(9, EAST, QUP_L5_0_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(10, EAST, MDP_VSYNC_P_MIRA, QUP_L6_0_CS, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(11, EAST, MDP_VSYNC_S_MIRA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(12, SOUTH, MDP_VSYNC_E, RES_2, TSIF1_SYNC, RES_4, RES_5, - RES_6, RES_7), + PIN(0, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(1, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(2, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(3, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(4, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(5, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(6, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(7, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(8, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(9, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(10, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(11, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(12, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(13, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(14, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(15, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(16, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(17, NORTH, CCI_I2C_SDA0, QUP_L0, RES_3, RES_4, RES_5, + PIN(17, NORTH, BLSP_UART_TX_A, BLSP_SPI_MOSI, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(18, SOUTH, CCI_I2C_SCL0, QUP_L1, RES_3, RES_4, RES_5, + PIN(18, NORTH, BLSP_UART_RX_A, BLSP_SPI_MISO, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(19, SOUTH, CCI_I2C_SDA1, QUP_L2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(20, SOUTH, CCI_I2C_SCL1, QUP_L3, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(21, SOUTH, CCI_TIMER0, GCC_GP2_CLK_MIRB, RES_3, RES_4, + PIN(19, NORTH, BLSP_UART_CTS_N, AUD_CDC_INT2, RES_3, BLSP_SPI_CS_N, RES_5, RES_6, RES_7), - PIN(22, SOUTH, CCI_TIMER1, GCC_GP3_CLK_MIRB, RES_3, RES_4, + PIN(20, NORTH, BLSP_UART_RFR_N, RES_2, RES_3, BLSP_SPI_CLK, RES_5, + RES_6, RES_7), + PIN(21, SOUTH, M_VOC_EXT_VFR_REF_IRQ_2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(23, SOUTH, CCI_TIMER2, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(24, SOUTH, CCI_TIMER3, CCI_ASYNC_IN1, RES_3, RES_4, + PIN(22, NORTH, BLSP_UART_TX, BLSP_SPI_MOSI_A, ASDIV1, RES_4, RES_5, RES_6, RES_7), - PIN(25, SOUTH, CCI_TIMER4, CCI_ASYNC_IN2, RES_3, RES_4, + PIN(23, NORTH, BLSP_UART_RX, BLSP_SPI_MISO_A, ASDIV2, RES_4, RES_5, RES_6, RES_7), - PIN(26, SOUTH, CCI_ASYNC_IN0, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(27, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(28, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(29, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(30, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(31, NORTH, QUP_L0, QUP_L2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(32, NORTH, QUP_L1, QUP_L3, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(33, NORTH, QUP_L2, QUP_L0, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(34, NORTH, QUP_L3, QUP_L1, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(35, SOUTH, PCI_E0_RST_N, QUP_L4_1_CS, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(36, SOUTH, PCI_E0_CLKREQN, QUP_L5_1_CS, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(37, SOUTH, QUP_L6_1_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(38, NORTH, USB_PHY_PS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(39, EAST, LPASS_SLIMBUS_DATA2, RES_2, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(40, SOUTH, SD_WRITE_PROTECT, TSIF1_ERROR, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(41, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(42, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(43, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(44, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(45, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(46, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(47, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(48, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(49, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(50, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(51, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(52, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(53, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(54, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(55, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(56, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(57, NORTH, QUA_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(58, NORTH, QUA_MI2S_SCK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(59, NORTH, QUA_MI2S_WS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(60, NORTH, QUA_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(61, NORTH, QUA_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(62, NORTH, QUA_MI2S_DATA2, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(63, NORTH, QUA_MI2S_DATA3, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(64, NORTH, PRI_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(65, NORTH, PRI_MI2S_SCK, QUP_L0, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(66, NORTH, PRI_MI2S_WS, QUP_L1, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(67, NORTH, PRI_MI2S_DATA0, QUP_L2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(68, NORTH, PRI_MI2S_DATA1, QUP_L3, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(69, EAST, SPKR_I2S_MCLK, AUDIO_REF_CLK, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(70, EAST, LPASS_SLIMBUS_CLK, SPKR_I2S_SCK, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(71, EAST, LPASS_SLIMBUS_DATA0, SPKR_I2S_DATA_OUT, RES_3, + PIN(24, NORTH, BLSP_UART_CTS_N, BLSP_I2C_SDA, BLSP_SPI_CS_N_A, RES_4, RES_5, RES_6, RES_7), - PIN(72, EAST, LPASS_SLIMBUS_DATA1, SPKR_I2S_WS, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(73, EAST, BTFM_SLIMBUS_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(74, EAST, BTFM_SLIMBUS_CLK, TER_MI2S_MCLK, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(75, EAST, TER_MI2S_SCK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(76, EAST, TER_MI2S_WS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(77, EAST, TER_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(78, EAST, TER_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(79, NORTH, SEC_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(80, NORTH, SEC_MI2S_SCK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(81, NORTH, SEC_MI2S_WS, QUP_L0, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(82, NORTH, SEC_MI2S_DATA0, QUP_L1, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(83, NORTH, SEC_MI2S_DATA1, QUP_L2, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(84, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(85, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(86, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(87, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(88, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(89, SOUTH, TSIF1_CLK, QUP_L0, QSPI_CS_N_1, RES_4, RES_5, - RES_6, RES_7), - PIN(90, SOUTH, TSIF1_EN, MDP_VSYNC0_OUT, QUP_L1, QSPI_CS_N_0, - MDP_VSYNC1_OUT, MDP_VSYNC2_OUT, MDP_VSYNC3_OUT), - PIN(91, SOUTH, TSIF1_DATA, SDC4_CMD, QUP_L2, QSPI_DATA, - RES_5, RES_6, RES_7), - PIN(92, SOUTH, TSIF2_ERROR, SDC4_DATA, QUP_L3, QSPI_DATA, - RES_5, RES_6, RES_7), - PIN(93, SOUTH, TSIF2_CLK, SDC4_CLK, QUP_L0, QSPI_DATA, - RES_5, RES_6, RES_7), - PIN(94, SOUTH, TSIF2_EN, SDC4_DATA, QUP_L1, QSPI_DATA, - RES_5, RES_6, RES_7), - PIN(95, SOUTH, TSIF2_DATA, SDC4_DATA, QUP_L2, QSPI_CLK, - RES_5, RES_6, RES_7), - PIN(96, SOUTH, TSIF2_SYNC, SDC4_DATA, QUP_L3, RES_4, - RES_5, RES_6, RES_7), - PIN(97, NORTH, RFFE6_CLK, GRFC37, MDP_VSYNC_P_MIRB, + PIN(25, NORTH, BLSP_UART_RFR_N, BLSP_I2C_SCL, BLSP_SPI_CLK_A, RES_4, RES_5, RES_6, RES_7), - PIN(98, NORTH, RFFE6_DATA, MDP_VSYNC_S_MIRB, RES_3, + PIN(26, EAST, RES_1, BLSP_UART_TX, BLSP_SPI_MOSI, RES_4, RES_5, + RES_6, RES_7), + PIN(27, EAST, RES_1, BLSP_UART_RX, BLSP_SPI_MISO, RES_4, RES_5, + RES_6, RES_7), + PIN(28, EAST, RES_1, BLSP_UART_CTS_N, RES_3, BLSP_SPI_CS_N, RES_5, + RES_6, RES_7), + PIN(29, EAST, RES_1, BLSP_UART_RFR_N, RES_3, BLSP_SPI_CLK, RES_5, + RES_6, RES_7), + PIN(30, NORTH, RES_1, BLSP_UART_TX, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(31, NORTH, RES_1, BLSP_UART_RX, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(32, NORTH, RES_1, BLSP_UART_CTS_N, BLSP_I2C_SDA, RES_4, RES_5, + RES_6, RES_7), + PIN(33, NORTH, RES_1, BLSP_UART_RFR_N, BLSP_I2C_SCL, RES_4, RES_5, + RES_6, RES_7), + PIN(34, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(35, SOUTH, PCIE_CLK_REQ, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(36, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(37, NORTH, NFC_IRQ, BLSP_SPI_MOSI, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(38, NORTH, RES_1, BLSP_SPI_MISO, AUDIO_TS_IN, RES_4, RES_5, + RES_6, RES_7), + PIN(39, EAST, RES_1, RES_2, BLSP_UART_TX_B, RES_4, RES_5, RES_6, + RES_7), + PIN(40, EAST, RES_1, RES_2, BLSP_UART_RX_B, RES_4, RES_5, RES_6, + RES_7), + PIN(41, EAST, RES_1, BLSP_I2C_SDA_B, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(42, EAST, RES_1, BLSP_I2C_SCL_B, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(43, EAST, RES_1, PWM_LED11, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(44, EAST, RES_1, PWM_LED12, BLSP_SPI_CS1_N, RES_4, RES_5, + RES_6, RES_7), + PIN(45, EAST, RES_1, PWM_LED13, BLSP_SPI_CS2_N, RES_4, RES_5, + RES_6, RES_7), + PIN(46, EAST, RES_1, PWM_LED14, BLSP_SPI_CS3_N, RES_4, RES_5, + RES_6, RES_7), + PIN(47, EAST, RES_1, PWM_LED15, BLSP_SPI_MOSI_B, RES_4, RES_5, + RES_6, RES_7), + PIN(48, EAST, RES_1, PWM_LED16, BLSP_SPI_MISO_B, RES_4, RES_5, + RES_6, RES_7), + PIN(49, EAST, RES_1, PWM_LED17, BLSP_SPI_CS_N_B, RES_4, RES_5, + RES_6, RES_7), + PIN(50, EAST, RES_1, PWM_LED18, BLSP_SPI_CLK_B, RES_4, RES_5, + RES_6, RES_7), + PIN(51, EAST, RES_1, PWM_LED19, EXT_MCLK1_B, RES_4, RES_5, RES_6, + RES_7), + PIN(52, EAST, RES_1, PWM_LED20, RES_3, I2S_3_SCK_B, RES_5, RES_6, + RES_7), + PIN(53, EAST, RES_1, PWM_LED21, I2S_3_WS_B, RES_4, RES_5, RES_6, + RES_7), + PIN(54, EAST, RES_1, I2S_3_DATA0_B, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(55, EAST, RES_1, I2S_3_DATA1_B, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(56, EAST, RES_1, RES_2, I2S_3_DATA2_B, RES_4, RES_5, RES_6, + RES_7), + PIN(57, EAST, RES_1, RES_2, I2S_3_DATA3_B, RES_4, RES_5, RES_6, + RES_7), + PIN(58, EAST, RGB_DATA_B, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(59, EAST, RGB_DATA_B, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(60, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(61, NORTH, RGMII_INT, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(62, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(63, NORTH, RGMII_CK_TX, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(64, NORTH, RGMII_TX_3, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(65, NORTH, RGMII_TX_2, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(66, NORTH, RGMII_TX_1, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(67, NORTH, RGMII_TX_0, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(68, NORTH, RGMII_CTL_TX, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(69, NORTH, RGMII_CK_RX, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(70, NORTH, RGMII_RX_3, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(71, NORTH, RGMII_RX_2, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(72, NORTH, RGMII_RX_1, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(73, NORTH, RGMII_RX_0, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(74, NORTH, RGMII_CTL_RX, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(75, NORTH, RGMII_MDIO, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(76, NORTH, RGMII_MDC, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(77, NORTH, IR_IN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(78, EAST, RGB_DATA_G, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(79, EAST, RGB_DATA_G, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(80, EAST, RGB_DATA_R, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(81, EAST, RGB_DATA_R, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(82, NORTH, BLSP_UART_TX, BLSP_SPI_MOSI, SD_WRITE_PROTECT, RES_4, RES_5, RES_6, RES_7), - PIN(99, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(100, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(101, NORTH, GRFC4, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(102, NORTH, PCI_E1_RST_N, RES_2, RES_3, RES_4, RES_5, + PIN(83, NORTH, BLSP_UART_RX, BLSP_SPI_MISO, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(103, NORTH, PCI_E1_CLKREQN, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(104, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(105, NORTH, UIM2_DATA, QUP_L0, QUP_L4_8_CS, RES_4, RES_5, - RES_6, RES_7), - PIN(106, NORTH, UIM2_CLK, QUP_L1, QUP_L5_8_CS, RES_4, RES_5, - RES_6, RES_7), - PIN(107, NORTH, UIM2_RESET, QUP_L2, QUP_L6_8_CS, RES_4, RES_5, - RES_6, RES_7), - PIN(108, NORTH, UIM2_PRESENT, QUP_L3, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(109, NORTH, UIM1_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(110, NORTH, UIM1_CLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(111, NORTH, UIM1_RESET, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(112, NORTH, UIM1_PRESENT, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(113, NORTH, UIM_BATT_ALARM, EDP_HOT_PLUG_DETECT, RES_3, + PIN(84, NORTH, BLSP_UART_CTS_N, BLSP_I2C_SDA, BLSP_SPI_CS_N, RES_4, RES_5, RES_6, RES_7), - PIN(114, NORTH, GRFC8, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRE, + PIN(85, NORTH, BLSP_UART_RFR_N, BLSP_I2C_SCL, BLSP_SPI_CLK, RES_4, RES_5, RES_6, RES_7), - PIN(115, NORTH, GRFC9, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRF, + PIN(86, EAST, RES_1, MCLK_IN1, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(87, EAST, I2S_1_SCK, DSD_CLK_A, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(88, EAST, I2S_1_WS, I2S_1_DATA0_DSD0, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(89, EAST, I2S_1_DATA0, I2S_1_DATA1_DSD1, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(90, EAST, I2S_1_DATA1, I2S_1_DATA2_DSD2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(91, EAST, I2S_1_DATA2, I2S_1_DATA3_DSD3, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(92, EAST, I2S_1_DATA3, I2S_1_DATA4_DSD4, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(93, EAST, I2S_1_DATA4, PWM_LED22, I2S_1_DATA5_DSD5, RES_4, RES_5, RES_6, RES_7), - PIN(116, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(117, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(118, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(119, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(120, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(121, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(122, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(123, EAST, QUP_L4_9_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(124, EAST, QUP_L5_9_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(125, EAST, QUP_L6_9_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(126, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(127, NORTH, GRFC3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(128, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRB, RES_4, + PIN(94, EAST, I2S_1_DATA5, PWM_LED23, I2S_1_DATA6_MIR, RES_4, RES_5, RES_6, RES_7), - PIN(129, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRC, RES_4, + PIN(95, EAST, RES_1, PWM_LED1, I2S_1_DATA7_MIR, RES_4, RES_5, + RES_6, RES_7), + PIN(96, EAST, RES_1, PWM_LED2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(97, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(98, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(99, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(100, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(101, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(102, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(103, EAST, RES_1, MCLK_IN2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(104, EAST, I2S_3_SCK_A, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(105, EAST, I2S_3_WS_A, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(106, EAST, I2S_3_DATA0_A, RES_2, HDMI_HOT_PLUG_MIR, RES_4, RES_5, RES_6, RES_7), - PIN(130, NORTH, QLINK_REQUEST, RES_2, RES_3, RES_4, RES_5, + PIN(107, EAST, I2S_3_DATA1_A, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(108, EAST, I2S_3_DATA2_A, RES_2, RES_3, PWM_LED3, RES_5, RES_6, RES_7), - PIN(131, NORTH, QLINK_ENABLE, RES_2, RES_3, RES_4, RES_5, + PIN(109, EAST, I2S_3_DATA3_A, RES_2, PWM_LED4, RES_4, RES_5, RES_6, RES_7), - PIN(132, NORTH, GRFC2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(133, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(134, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(135, NORTH, GRFC0, PA_INDICATOR_1_OR_2, RES_3, RES_4, + PIN(110, EAST, RES_1, RES_2, DSD_CLK_B, PWM_LED5, RES_5, RES_6, + RES_7), + PIN(111, EAST, RES_1, I2S_4_DATA0_DSD0, PWM_LED6, RES_4, RES_5, + RES_6, RES_7), + PIN(112, EAST, RES_1, I2S_4_DATA1_DSD1, PWM_LED7, RES_4, RES_5, + RES_6, RES_7), + PIN(113, EAST, RES_1, I2S_4_DATA2_DSD2, PWM_LED8, RES_4, RES_5, + RES_6, RES_7), + PIN(114, EAST, RES_1, I2S_4_DATA3_DSD3, PWM_LED24, RES_4, RES_5, + RES_6, RES_7), + PIN(115, EAST, RES_1, I2S_4_DATA4_DSD4, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(116, EAST, I2S_4_DATA5_DSD5, SPKR_DAC0, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(117, NORTH, BLSP_I2C_SDA, BLSP_SPI_CS_N, PWM_LED9, RES_4, RES_5, RES_6, RES_7), - PIN(136, NORTH, GRFC1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(137, NORTH, RFFE3_DATA, GRFC35, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(138, NORTH, RFFE3_CLK, GRFC32, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(139, NORTH, RFFE4_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(140, NORTH, RFFE4_CLK, GRFC36, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(141, NORTH, RFFE5_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(142, NORTH, RFFE5_CLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(143, NORTH, GRFC5, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRD, + PIN(118, NORTH, BLSP_I2C_SCL, BLSP_SPI_CLK, PWM_LED10, RES_4, RES_5, RES_6, RES_7), - PIN(144, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(145, NORTH, RES_1, GPS_TX_AGGRESSOR_MIRA, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(146, NORTH, RFFE2_DATA, GRFC34, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(147, NORTH, RFFE2_CLK, GRFC33, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(148, NORTH, RFFE1_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(149, NORTH, RFFE1_CLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), + PIN(119, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), }; struct tlmm_gpio { -- To view, visit https://review.coreboot.org/c/coreboot/+/29963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdd675527458e597c1f49544425146bd17f28075 Gerrit-Change-Number: 29963 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: clock: Adding the clock support for qcs405
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29962 Change subject: qcs405: clock: Adding the clock support for qcs405 ...................................................................... qcs405: clock: Adding the clock support for qcs405 Add basic clock support and enable UART, SPI clocks. Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Pranav Agrawal <pranava(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/bootblock.c A src/soc/qualcomm/qcs405/clock.c A src/soc/qualcomm/qcs405/include/soc/clock.h 4 files changed, 367 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29962/1 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 6fc87c7..58a62fa 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -7,6 +7,7 @@ bootblock-y += mmu.c bootblock-y += timer.c bootblock-y += gpio.c +bootblock-y += clock.c bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c bootblock-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c @@ -22,6 +23,7 @@ romstage-y += cbmem.c romstage-y += timer.c romstage-y += gpio.c +romstage-y += clock.c romstage-y += mmu.c romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c romstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c @@ -32,6 +34,7 @@ ramstage-y += cbmem.c ramstage-y += timer.c ramstage-y += gpio.c +ramstage-y += clock.c ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ramstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c diff --git a/src/soc/qualcomm/qcs405/bootblock.c b/src/soc/qualcomm/qcs405/bootblock.c index 5e63f13..15d1c18 100644 --- a/src/soc/qualcomm/qcs405/bootblock.c +++ b/src/soc/qualcomm/qcs405/bootblock.c @@ -15,6 +15,12 @@ #include <bootblock_common.h> #include <soc/mmu.h> +#include <soc/clock.h> + +void bootblock_soc_early_init(void) +{ + clock_init(); +} void bootblock_soc_init(void) { diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c new file mode 100644 index 0000000..6307259 --- /dev/null +++ b/src/soc/qualcomm/qcs405/clock.c @@ -0,0 +1,208 @@ + /* This file is part of the coreboot project. + * + * Copyright 2018 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <types.h> +#include <console/console.h> +#include <delay.h> +#include <timer.h> +#include <timestamp.h> +#include <commonlib/helpers.h> +#include <string.h> + +#include <soc/clock.h> + +#define DIV(div) (div ? (2*div - 1) : 0) +#define HALF_DIVIDER(div2x) (div2x ? (div2x - 1) : 0) + +struct clock_config uart_cfg[] = { + { + .hz = 1843200, + .hw_ctl = 0x0, + .src = SRC_GPLL0_MAIN_800MHZ, + .div = DIV(0), + .m = 36, + .n = 15625, + .d_2 = 15625, + }, + { + .hz = 3686400, + .hw_ctl = 0x0, + .src = SRC_GPLL0_MAIN_800MHZ, + .div = DIV(0), + .m = 72, + .n = 15625, + .d_2 = 15625, + } +}; + +struct clock_config i2c_cfg[] = { + { + .hz = 19200000, + .hw_ctl = 0x0, + .src = SRC_XO_19_2MHZ, + .div = DIV(0), + }, + { + .hz = 50000000, + .hw_ctl = 0x0, + .src = SRC_GPLL0_MAIN_800MHZ, + .div = DIV(32), + } +}; + +struct clock_config spi_cfg[] = { + { + .hz = 19200000, + .hw_ctl = 0x0, + .src = SRC_XO_19_2MHZ, + .div = DIV(0), + }, + { + .hz = 30000000, + .hw_ctl = 0x0, + .src = SRC_XO_19_2MHZ, + .div = DIV(0), + }, + { + .hz = 50000000, + .hw_ctl = 0x0, + .src = SRC_GPLL0_MAIN_800MHZ, + .div = DIV(32), + } +}; + + +static struct qcs405_clock *const blsp1_uart2_clk = + (void *)GCC_BLSP1_UART2_BASE; + +static struct qcs405_clock *const blsp2_qup0_spi_clk = + (void *)GCC_BLSP2_QUP0_SPI_BASE; + +static int clock_configure_mnd(struct qcs405_clock *clk, uint32_t m, uint32_t n, + uint32_t d_2) +{ + uint32_t reg_val; + + /* Configure Root Clock Generator(RCG) for Dual Edge Mode */ + reg_val = read32(&clk->cfg_rcgr); + reg_val |= (2 << CLK_CTL_CFG_MODE_SHFT); + write32(&clk->cfg_rcgr, reg_val); + + /* Set M/N/D config */ + write32(&clk->m, m & CLK_CTL_RCG_MND_BMSK); + write32(&clk->n, ~(n-m) & CLK_CTL_RCG_MND_BMSK); + write32(&clk->d_2, ~(d_2) & CLK_CTL_RCG_MND_BMSK); + + return 0; +} + +static int clock_configure(struct qcs405_clock *clk, + struct clock_config *clk_cfg, + uint32_t hz, uint32_t num_perfs) +{ + uint32_t reg_val; + uint32_t idx; + + for (idx = 0; idx < num_perfs; idx++) + if (hz <= clk_cfg[idx].hz) + break; + + reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + + /* Set clock config */ + write32(&clk->cfg_rcgr, reg_val); + + if (clk_cfg[idx].m != 0) + clock_configure_mnd(clk, clk_cfg[idx].m, clk_cfg[idx].n, + clk_cfg[idx].d_2); + + /* Commit config to RCG*/ + setbits_le32(&clk->cmd_rcgr, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + + return 0; +} + +static bool clock_is_off(void *cbcr_addr) +{ + return (read32(cbcr_addr) & CLK_CTL_CBC_CLK_OFF_BMSK); +} + +static int clock_enable_vote(void *cbcr_addr, void *vote_addr, + uint32_t vote_bit) +{ + + /* Set clock vote bit */ + setbits_le32(vote_addr, BIT(vote_bit)); + + /* Ensure clock is enabled */ + while (clock_is_off(cbcr_addr)) + ; + + return 0; +} + +static int clock_enable(void *cbcr_addr) +{ + + /* Set clock enable bit */ + setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + + /* Ensure clock is enabled */ + while (clock_is_off(cbcr_addr)) + ; + + return 0; +} + +static int clock_disable(void *cbcr_addr) +{ + + /* Set clock enable bit */ + clrbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + return 0; +} + +int clock_reset_bcr(void *bcr_addr, bool reset) +{ + struct qcs405_bcr *bcr = bcr_addr; + + if (reset) + setbits_le32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + else + clrbits_le32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + + return 0; +} + +void clock_init(void) +{ + + clock_configure(blsp1_uart2_clk, uart_cfg, 1843200, + ARRAY_SIZE(uart_cfg)); + + clock_disable(REG(GCC_BLSP1_UART0_APPS_CBCR)); + clock_enable(REG(GCC_BLSP1_UART0_APPS_CBCR)); + clock_enable(REG(GCC_BLSP1_UART2_APPS_CBCR)); + clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), + REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), + BLSP1_AHB_CLK_ENA); + + clock_configure(blsp2_qup0_spi_clk, spi_cfg, 50000000, + ARRAY_SIZE(spi_cfg)); + clock_enable(REG(GCC_BLSP2_QUP0_SPI_APPS_CBCR)); + +} + diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h new file mode 100644 index 0000000..aa8bbe5 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/clock.h @@ -0,0 +1,150 @@ + /* This file is part of the coreboot project. + * + * Copyright 2018 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_QUALCOMM_QCS405_CLOCK_H__ +#define __SOC_QUALCOMM_QCS405_CLOCK_H__ + +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE 0x01845004 + +#define GCC_BLSP1_UART0_BASE 0x180600C +#define GCC_BLSP1_UART1_BASE 0x1802044 +#define GCC_BLSP1_UART2_BASE 0x1803034 +#define GCC_BLSP1_UART3_BASE 0x1804014 +#define GCC_BLSP2_UART0_BASE 0x180C044 + +#define GCC_BLSP1_QUP0_SPI_BASE 0x1806034 +#define GCC_BLSP1_QUP1_SPI_BASE 0x1802024 +#define GCC_BLSP1_QUP2_SPI_BASE 0x1803014 +#define GCC_BLSP1_QUP3_SPI_BASE 0x1804024 +#define GCC_BLSP1_QUP4_SPI_BASE 0x1805024 +#define GCC_BLSP2_QUP0_SPI_BASE 0x180C024 + +#define GCC_BLSP1_QUP0_I2C_BASE 0x180602C +#define GCC_BLSP1_QUP1_I2C_BASE 0x180200C +#define GCC_BLSP1_QUP2_I2C_BASE 0x1803000 +#define GCC_BLSP1_QUP3_I2C_BASE 0x1804000 +#define GCC_BLSP1_QUP4_I2C_BASE 0x1805000 +#define GCC_BLSP2_QUP0_I2C_BASE 0x180C00C + +#define GCC_BLSP1_UART0_APPS_CBCR 0x1806004 +#define GCC_BLSP1_UART1_APPS_CBCR 0x180203C +#define GCC_BLSP1_UART2_APPS_CBCR 0x180302C +#define GCC_BLSP1_UART3_APPS_CBCR 0x180400C +#define GCC_BLSP2_UART0_APPS_CBCR 0x180C03C + +#define GCC_BLSP2_QUP0_SPI_APPS_CBCR 0x180C004 + +#define GCC_BLSP1_AHB_CBCR 0x1801008 +#define GCC_BLSP2_AHB_CBCR 0x180B008 + +#define BLSP1_AHB_CLK_ENA 10 +#define BLSP2_AHB_CLK_ENA 20 + + + +#define SRC_XO_19_2MHZ 0 +#define SRC_GPLL0_MAIN_800MHZ 1 + + + +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1 0x0015200C +#define SRC_XO_19_2MHZ 0 +#define REG(addr) ((void *)addr) + +/** + * USB BCR registers + */ +#define GCC_USB_HS_PHY_CFG_AHB_BCR 0x1841038 +#define GCC_USB_HS_BCR 0x1841000 +#define GCC_USB_30_BCR 0x1839000 +#define GCC_USB2A_PHY_BCR 0x1841028 +#define GCC_USB2_HS_PHY_ONLY_BCR 0x1841034 +#define GCC_QUSB2_PHY_BCR 0x184103C + +struct qcs405_clock { + uint32_t cmd_rcgr; + uint32_t cfg_rcgr; + uint32_t m; + uint32_t n; + uint32_t d_2; +}; + +struct qcs405_bcr { + uint32_t bcr; +}; + +struct mdss_clock_config { + const char *clk_name; + struct qcs405_clock *rcgr; + uint32_t *cbcr; +}; + +enum clk_ctl_gpll_user_ctl { + CLK_CTL_GPLL_PLLOUT_EVEN_BMSK = 0x2, + CLK_CTL_GPLL_PLLOUT_EVEN_SHFT = 1 +}; + +enum clk_ctl_cfg_rcgr { + CLK_CTL_CFG_HW_CTL_BMSK = 0x100000, + CLK_CTL_CFG_HW_CTL_SHFT = 20, + CLK_CTL_CFG_MODE_BMSK = 0x3000, + CLK_CTL_CFG_MODE_SHFT = 12, + CLK_CTL_CFG_SRC_SEL_BMSK = 0x700, + CLK_CTL_CFG_SRC_SEL_SHFT = 8, + CLK_CTL_CFG_SRC_DIV_BMSK = 0x1F, + CLK_CTL_CFG_SRC_DIV_SHFT = 0 +}; + +enum clk_ctl_cmd_rcgr { + CLK_CTL_CMD_ROOT_OFF_BMSK = 0x80000000, + CLK_CTL_CMD_ROOT_OFF_SHFT = 31, + CLK_CTL_CMD_ROOT_EN_BMSK = 0x2, + CLK_CTL_CMD_ROOT_EN_SHFT = 1, + CLK_CTL_CMD_UPDATE_BMSK = 0x1, + CLK_CTL_CMD_UPDATE_SHFT = 0 +}; + +enum clk_ctl_cbcr { + CLK_CTL_CBC_CLK_OFF_BMSK = 0x80000000, + CLK_CTL_CBC_CLK_OFF_SHFT = 31, + CLK_CTL_CBC_CLK_EN_BMSK = 0x1, + CLK_CTL_CBC_CLK_EN_SHFT = 0 +}; + +enum clk_ctl_rcg_mnd { + CLK_CTL_RCG_MND_BMSK = 0xFFFF, + CLK_CTL_RCG_MND_SHFT = 0, +}; + +enum clk_ctl_bcr { + CLK_CTL_BCR_BLK_ARES_BMSK = 0x1, + CLK_CTL_BCR_BLK_ARES_SHFT = 0, +}; + +struct clock_config { + uint32_t hz; + uint32_t hw_ctl; + uint32_t src; + uint32_t div; + uint32_t m; + uint32_t n; + uint32_t d_2; +}; + +void clock_init(void); +void clock_reset_aop(void); +int clock_configure_qspi(uint32_t hz); +int clock_reset_bcr(void *bcr_addr, bool reset); + +#endif // __SOC_QUALCOMM_QCS405_CLOCK_H__ -- To view, visit https://review.coreboot.org/c/coreboot/+/29962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae Gerrit-Change-Number: 29962 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: QCS405: Change DRAM size to 1GB
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29960 Change subject: QCS405: Change DRAM size to 1GB ...................................................................... QCS405: Change DRAM size to 1GB Change-Id: I94f01141d6a537166db3900cf21fc2813cfe96dc Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/cbmem.c M src/soc/qualcomm/qcs405/include/soc/mmu.h M src/soc/qualcomm/qcs405/soc.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/29960/1 diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c index 3b9ad4a..e065409 100644 --- a/src/soc/qualcomm/qcs405/cbmem.c +++ b/src/soc/qualcomm/qcs405/cbmem.c @@ -17,5 +17,5 @@ void *cbmem_top(void) { - return (void *)((uintptr_t)4 * GiB); + return (void *)((uintptr_t)3 * GiB); } diff --git a/src/soc/qualcomm/qcs405/include/soc/mmu.h b/src/soc/qualcomm/qcs405/include/soc/mmu.h index 3951f96..7bf024f 100644 --- a/src/soc/qualcomm/qcs405/include/soc/mmu.h +++ b/src/soc/qualcomm/qcs405/include/soc/mmu.h @@ -16,7 +16,7 @@ #ifndef _SOC_QUALCOMM_QCS405_MMU_H__ #define _SOC_QUALCOMM_QCS405_MMU_H__ -#define DRAMSIZE4GB 0x100000000 +#define DRAMSIZE1GB 0x40000000 void qcs405_mmu_init(void); #ifdef CONFIG_QC_SOC_SIMULATE diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c index c97822a..3de3c02 100644 --- a/src/soc/qualcomm/qcs405/soc.c +++ b/src/soc/qualcomm/qcs405/soc.c @@ -21,7 +21,7 @@ static void soc_read_resources(device_t dev) { - ram_resource(dev, 0, (uintptr_t)_dram / KiB, DRAMSIZE4GB / KiB); + ram_resource(dev, 0, (uintptr_t)_dram / KiB, DRAMSIZE1GB / KiB); reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB, _dram_reserved_size / KiB); } -- To view, visit https://review.coreboot.org/c/coreboot/+/29960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94f01141d6a537166db3900cf21fc2813cfe96dc Gerrit-Change-Number: 29960 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: Enable uart_bit_bang
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29961 Change subject: qcs405: Enable uart_bit_bang ...................................................................... qcs405: Enable uart_bit_bang uart_bit_bang has been enabled for VER, ROM, RAM stages. uart_fill_lb() empty routine has been declared to avoid compilation error. Change-Id: I387779a74913ffb58d74d2f2c5d3e22167bbc310 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/uart_bitbang.c 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/29961/1 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 17ba0f1..6fc87c7 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -14,6 +14,7 @@ verstage-y += spi.c verstage-y += timer.c verstage-y += gpio.c +verstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c verstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ @@ -21,6 +22,8 @@ romstage-y += cbmem.c romstage-y += timer.c romstage-y += gpio.c +romstage-y += mmu.c +romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c romstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ @@ -29,6 +32,7 @@ ramstage-y += cbmem.c ramstage-y += timer.c ramstage-y += gpio.c +ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ramstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ diff --git a/src/soc/qualcomm/qcs405/uart_bitbang.c b/src/soc/qualcomm/qcs405/uart_bitbang.c index 8827bc4..97782bd 100644 --- a/src/soc/qualcomm/qcs405/uart_bitbang.c +++ b/src/soc/qualcomm/qcs405/uart_bitbang.c @@ -19,6 +19,8 @@ #define UART_TX_PIN GPIO(17) +void uart_fill_lb(void *data); + static void set_tx(int line_state) { gpio_set(UART_TX_PIN, line_state); @@ -43,3 +45,11 @@ { return 0; /* not implemented */ } + +//HACK +#ifndef __PRE_RAM__ +/* TODO: Implement function */ +void uart_fill_lb(void *data) +{ +} +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/29961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I387779a74913ffb58d74d2f2c5d3e22167bbc310 Gerrit-Change-Number: 29961 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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coreboot-gerrit November 2018