coreboot-gerrit November 2018

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Change in ...coreboot[master]: mainboard/google/mistral: Add support for Mistral
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29949 Change subject: mainboard/google/mistral: Add support for Mistral ...................................................................... mainboard/google/mistral: Add support for Mistral Adding a new board variant 'Mistral' based on qcs405 soc. TEST=build Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- A src/mainboard/google/mistral/Kconfig A src/mainboard/google/mistral/Kconfig.name A src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/board_info.txt A src/mainboard/google/mistral/bootblock.c A src/mainboard/google/mistral/chromeos.c A src/mainboard/google/mistral/chromeos.fmd A src/mainboard/google/mistral/devicetree.cb A src/mainboard/google/mistral/mainboard.c A src/mainboard/google/mistral/memlayout.ld A src/mainboard/google/mistral/romstage.c 11 files changed, 256 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29949/1 diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig new file mode 100644 index 0000000..f8e8ac7 --- /dev/null +++ b/src/mainboard/google/mistral/Kconfig @@ -0,0 +1,43 @@ + +config BOARD_GOOGLE_MISTRAL_COMMON # Umbrella option to be selected by variants + def_bool n + +if BOARD_GOOGLE_MISTRAL_COMMON + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select COMMON_CBFS_SPI_WRAPPER + select SOC_QUALCOMM_QCS405 + select SPI_FLASH + select MAINBOARD_HAS_CHROMEOS + select MISSING_BOARD_RESET + +config VBOOT + select VBOOT_VBNV_FLASH + select VBOOT_MOCK_SECDATA + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_FORCE_DEV_SWITCH_ON + +config MAINBOARD_DIR + string + default google/mistral + +config MAINBOARD_VENDOR + string + default "Google" + +########################################################## +#### Update below when adding a new derivative board. #### +########################################################## + +config MAINBOARD_PART_NUMBER + string + default "Mistral" if BOARD_GOOGLE_MISTRAL + +config GBB_HWID + string + depends on CHROMEOS + default "MISTRAL TEST 1859" if BOARD_GOOGLE_MISTRAL + +endif # BOARD_GOOGLE_MISTRAL_COMMON diff --git a/src/mainboard/google/mistral/Kconfig.name b/src/mainboard/google/mistral/Kconfig.name new file mode 100644 index 0000000..ca51fa2 --- /dev/null +++ b/src/mainboard/google/mistral/Kconfig.name @@ -0,0 +1,4 @@ + +config BOARD_GOOGLE_MISTRAL + bool "Mistral" + select BOARD_GOOGLE_MISTRAL_COMMON diff --git a/src/mainboard/google/mistral/Makefile.inc b/src/mainboard/google/mistral/Makefile.inc new file mode 100644 index 0000000..0e2f6bd --- /dev/null +++ b/src/mainboard/google/mistral/Makefile.inc @@ -0,0 +1,15 @@ + +bootblock-y += memlayout.ld +bootblock-y += chromeos.c +bootblock-y += bootblock.c + +verstage-y += memlayout.ld +verstage-y += chromeos.c + +romstage-y += memlayout.ld +romstage-y += chromeos.c +romstage-y += romstage.c + +ramstage-y += memlayout.ld +ramstage-y += chromeos.c +ramstage-y += mainboard.c diff --git a/src/mainboard/google/mistral/board_info.txt b/src/mainboard/google/mistral/board_info.txt new file mode 100644 index 0000000..5ef77d7 --- /dev/null +++ b/src/mainboard/google/mistral/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Mistral Qualcomm QCS405 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/mistral/bootblock.c b/src/mainboard/google/mistral/bootblock.c new file mode 100644 index 0000000..6718d52 --- /dev/null +++ b/src/mainboard/google/mistral/bootblock.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <timestamp.h> + +void bootblock_mainboard_init(void) +{ + +} diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c new file mode 100644 index 0000000..538e46f --- /dev/null +++ b/src/mainboard/google/mistral/chromeos.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot/coreboot_tables.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + +} diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd new file mode 100644 index 0000000..e8b9978 --- /dev/null +++ b/src/mainboard/google/mistral/chromeos.fmd @@ -0,0 +1,52 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License version 2 and +## only version 2 as published by the Free Software Foundation. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +FLASH@0x0 0x800000 { + WP_RO@0x0 0x300000 { + RO_SECTION@0x0 0x2FE000 { + BOOTBLOCK@0 248K + COREBOOT(CBFS)@0x3E000 0x1E0000 + FMAP@0x21E000 0x1000 + GBB@0x21F000 0xDEF00 + RO_FRID@0x2FDF00 0x100 + } + RO_VPD@0x2FE000 0x2000 + } + + RW_NVRAM@0x300000 0x8000 + RW_ELOG@0x308000 0x8000 + RW_VPD@0x310000 0x8000 + RW_CDT@0x318000 0x8000 + + RW_SECTION_A@0x320000 0x268000 { + VBLOCK_A@0x0 0x2000 + FW_MAIN_A(CBFS)@0x2000 0x1E1F00 + RW_FWID_A@0x1E3F00 0x100 + RW_DDR_TRAINING_A@0x1E4000 0x4000 + RW_XBL_BUFFER_A@0x1E8000 0x4000 + } + + RW_SHARED@0x588000 0x10000 { + SHARED_DATA@0x0 0x10000 + } + + RW_SECTION_B@0x598000 0x268000 { + VBLOCK_B@0x0 0x2000 + FW_MAIN_B(CBFS)@0x2000 0x1E1F00 + RW_FWID_B@0x1E3F00 0x100 + RW_DDR_TRAINING_B@0x1E4000 0x4000 + RW_XBL_BUFFER_B@0x1E8000 0x4000 + } +} diff --git a/src/mainboard/google/mistral/devicetree.cb b/src/mainboard/google/mistral/devicetree.cb new file mode 100644 index 0000000..977f4c6 --- /dev/null +++ b/src/mainboard/google/mistral/devicetree.cb @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License version 2 and +## only version 2 as published by the Free Software Foundation. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/qualcomm/qcs405 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c new file mode 100644 index 0000000..c249a32 --- /dev/null +++ b/src/mainboard/google/mistral/mainboard.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <bootblock_common.h> +#include <timestamp.h> + +static void mainboard_init(device_t dev) +{ + +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/mistral/memlayout.ld b/src/mainboard/google/mistral/memlayout.ld new file mode 100644 index 0000000..cbc50e2 --- /dev/null +++ b/src/mainboard/google/mistral/memlayout.ld @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + #include <soc/memlayout.ld> diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c new file mode 100644 index 0000000..079e20b --- /dev/null +++ b/src/mainboard/google/mistral/romstage.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/exception.h> +#include <cbmem.h> +#include <halt.h> +#include <program_loading.h> +#include <console/console.h> +#include <timestamp.h> +#include <arch/stages.h> + +void platform_romstage_main(void) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d Gerrit-Change-Number: 29949 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/qualcomm/qcs405: Support for new SoC
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29948 Change subject: soc/qualcomm/qcs405: Support for new SoC ...................................................................... soc/qualcomm/qcs405: Support for new SoC Adding the basic infrastruture soc support for qcs405 and a new build variant. TEST=build Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- A src/soc/qualcomm/qcs405/Kconfig A src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/bootblock.c A src/soc/qualcomm/qcs405/cbmem.c A src/soc/qualcomm/qcs405/include/soc/gpio.h A src/soc/qualcomm/qcs405/include/soc/memlayout.ld A src/soc/qualcomm/qcs405/soc.c A src/soc/qualcomm/qcs405/spi.c A src/soc/qualcomm/qcs405/timer.c 9 files changed, 288 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/29948/1 diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig new file mode 100644 index 0000000..560d988 --- /dev/null +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -0,0 +1,21 @@ + +config SOC_QUALCOMM_QCS405 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select BOOTBLOCK_CONSOLE + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select HAVE_MONOTONIC_TIMER + +if SOC_QUALCOMM_QCS405 + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + select VBOOT_OPROM_MATTERS + select VBOOT_STARTS_IN_BOOTBLOCK +endif diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc new file mode 100644 index 0000000..15f5a0c --- /dev/null +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -0,0 +1,32 @@ + +ifeq ($(CONFIG_SOC_QUALCOMM_QCS405),y) + +################################################################################ +bootblock-y += bootblock.c +bootblock-y += timer.c +bootblock-y += spi.c + +################################################################################ +verstage-y += timer.c +verstage-y += spi.c + +################################################################################ +romstage-y += timer.c +romstage-y += spi.c +romstage-y += cbmem.c + +################################################################################ +ramstage-y += soc.c +ramstage-y += timer.c +ramstage-y += spi.c +ramstage-y += cbmem.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/qualcomm/qcs405/include + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + @printf "Generating: $(subst $(obj)/,,$(@))\n" + cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin + +endif diff --git a/src/soc/qualcomm/qcs405/bootblock.c b/src/soc/qualcomm/qcs405/bootblock.c new file mode 100644 index 0000000..3ed37ae --- /dev/null +++ b/src/soc/qualcomm/qcs405/bootblock.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> + +void bootblock_soc_init(void) +{ + +} diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c new file mode 100644 index 0000000..3b9ad4a --- /dev/null +++ b/src/soc/qualcomm/qcs405/cbmem.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ + return (void *)((uintptr_t)4 * GiB); +} diff --git a/src/soc/qualcomm/qcs405/include/soc/gpio.h b/src/soc/qualcomm/qcs405/include/soc/gpio.h new file mode 100644 index 0000000..e1ad453 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/gpio.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_QCS405_GPIO_H_ +#define _SOC_QUALCOMM_QCS405_GPIO_H_ + +#include <types.h> + +typedef u32 gpio_t; + +#endif // _SOC_QUALCOMM_QCS405_GPIO_H_ diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld new file mode 100644 index 0000000..c0f5759 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> +#include <arch/header.ld> + +/* SYSTEM_IMEM : 0x8600000 - 0x8607FFF */ +#define SSRAM_START(addr) SYMBOL(ssram, addr) +#define SSRAM_END(addr) SYMBOL(essram, addr) + +/* BOOT_IMEM : 0x8C00000 - 0x8D80000 */ +#define BSRAM_START(addr) SYMBOL(bsram, addr) +#define BSRAM_END(addr) SYMBOL(ebsram, addr) + +SECTIONS +{ + SSRAM_START(0x8600000) + SSRAM_END(0x8608000) + + BSRAM_START(0x8C00000) + OVERLAP_VERSTAGE_ROMSTAGE(0x8C00000, 100K) + REGION(fw_reserved2, 0x8C19000, 0x16000, 4096) + BOOTBLOCK(0x8C2F000, 40K) + TTB(0x8C39000, 56K) + VBOOT2_WORK(0x8C47000, 16K) + STACK(0x8C4B000, 16K) + TIMESTAMP(0x8C4F000, 1K) + PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K) + PRERAM_CBFS_CACHE(0x8C57400, 70K) + REGION(bsram_unused, 0x8C68C00, 0xA2400, 0x100) +/* REGION(qclib, 0x8D0B000, 0x80000, 4096) + REGION(dcb, 0x8D8B000, 0x4000, 4096) + REGION(pmic, 0x8D8F000, 0xA000, 4096)*/ + BSRAM_END(0x8D80000) + + DRAM_START(0x90000000) + POSTRAM_CBFS_CACHE(0x90000000, 384K) + RAMSTAGE(0x90800000, 128K) +} diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c new file mode 100644 index 0000000..7870219 --- /dev/null +++ b/src/soc/qualcomm/qcs405/soc.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <timestamp.h> + +static void soc_read_resources(device_t dev) +{ + +} + +static void soc_init(device_t dev) +{ + +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_qualcomm_qcs405_ops = { + CHIP_NAME("SOC Qualcomm QCS405") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c new file mode 100644 index 0000000..c04b15d --- /dev/null +++ b/src/soc/qualcomm/qcs405/spi.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <spi-generic.h> +#include <spi_flash.h> + +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) +{ + return 0; +} + +static void spi_ctrlr_release_bus(const struct spi_slave *slave) +{ + +} + +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t bytes_out, void *din, size_t bytes_in) +{ + return 0; +} + +static const struct spi_ctrlr spi_ctrlr = { + .claim_bus = spi_ctrlr_claim_bus, + .release_bus = spi_ctrlr_release_bus, + .xfer = spi_ctrlr_xfer, + .max_xfer_size = 65535, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = 0, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/qualcomm/qcs405/timer.c b/src/soc/qualcomm/qcs405/timer.c new file mode 100644 index 0000000..8fb84c8 --- /dev/null +++ b/src/soc/qualcomm/qcs405/timer.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <timer.h> +#include <delay.h> + +void timer_monotonic_get(struct mono_time *mt) +{ + +} + +void init_timer(void) +{ + +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e Gerrit-Change-Number: 29948 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/intel/braswell: Remove disabled LPE acpi code
by Frans Hendriks (Code Review) 30 Nov '18

30 Nov '18

Hello Patrick Rudolph, build bot (Jenkins), Hannah Williams, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29414 to look at the new patch set (#3). Change subject: src/soc/intel/braswell: Remove disabled LPE acpi code ...................................................................... src/soc/intel/braswell: Remove disabled LPE acpi code The ACPI code for LPE device was included regardless of the availability of the LPE controller. Move the LPE ACPI code to seperate SSDT and hide it when LPE is disabled. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/google/cyan/Makefile.inc M src/mainboard/google/cyan/acpi/codec_maxim.asl M src/mainboard/google/cyan/acpi/codec_realtek.asl A src/mainboard/google/cyan/ssdtlpe.asl M src/mainboard/intel/strago/Makefile.inc M src/mainboard/intel/strago/acpi/mainboard.asl A src/mainboard/intel/strago/ssdtlpe.asl M src/soc/intel/braswell/acpi/southcluster.asl M src/soc/intel/braswell/include/soc/acpi.h M src/soc/intel/braswell/lpe.c 10 files changed, 157 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/29414/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/29414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Gerrit-Change-Number: 29414 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: [Test]: Move {pci, pnp}_devfn_t to <device/pci_ops.h>
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29947 Change subject: [Test]: Move {pci,pnp}_devfn_t to <device/pci_ops.h> ...................................................................... [Test]: Move {pci,pnp}_devfn_t to <device/pci_ops.h> Change-Id: I6a3deea676308e2dc703b5e06558b05235191044 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/armv7/mmu.c M src/arch/arm/include/arch/pci_ops.h M src/arch/arm64/include/arch/pci_ops.h M src/arch/mips/include/arch/pci_ops.h M src/arch/riscv/arch_timer.c M src/arch/x86/cf9_reset.c M src/arch/x86/cpu.c M src/arch/x86/ebda.c M src/arch/x86/include/arch/io.h M src/arch/x86/include/arch/pci_io_cfg.h M src/arch/x86/include/arch/pci_mmio_cfg.h M src/arch/x86/ioapic.c M src/arch/x86/pci_ops_conf1.c M src/commonlib/storage/sdhci.h M src/console/die.c M src/console/post.c M src/cpu/allwinner/a10/clock.c M src/cpu/allwinner/a10/gpio.c M src/cpu/allwinner/a10/pinmux.c M src/cpu/allwinner/a10/raminit.c M src/cpu/allwinner/a10/timer.c M src/cpu/allwinner/a10/twi.c M src/cpu/allwinner/a10/uart.c M src/cpu/amd/family_10h-family_15h/ram_calc.c M src/cpu/amd/geode_lx/cpubug.c M src/cpu/amd/geode_lx/geode_lx_init.c M src/cpu/amd/geode_lx/syspreinit.c M src/cpu/amd/microcode/microcode.c M src/cpu/amd/smm/smm_init.c M src/cpu/intel/fsp_model_406dx/bootblock.c M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/haswell/romstage.c M src/cpu/intel/model_2065x/bootblock.c M src/cpu/intel/model_206ax/bootblock.c M src/cpu/ti/am335x/gpio.c M src/cpu/ti/am335x/pinmux.c M src/cpu/ti/am335x/uart.c M src/cpu/x86/lapic/apic_timer.c M src/cpu/x86/smm/smihandler.c M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/tsc/delay_tsc.c M src/device/azalia_device.c M src/device/device.c M src/device/oprom/include/io.h M src/device/oprom/realmode/x86.c M src/device/oprom/realmode/x86_interrupts.c M src/device/oprom/x86emu/sys.c M src/device/oprom/yabel/io.c M src/device/pci_device.c M src/device/pci_early.c M src/device/pci_ops_mmconf.c M src/device/pnp_device.c M src/drivers/aspeed/ast2050/ast2050.c M src/drivers/aspeed/common/aspeed_coreboot.h M src/drivers/elog/gsmi.c M src/drivers/emulation/qemu/bochs.c M src/drivers/emulation/qemu/cirrus.c M src/drivers/emulation/qemu/qemu_debugcon.c M src/drivers/gic/gic.c M src/drivers/i2c/at24rf08c/at24rf08c.c M src/drivers/i2c/at24rf08c/lenovo_serials.c M src/drivers/i2c/designware/dw_i2c.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/drivers/intel/fsp2_0/util.c M src/drivers/intel/gma/edid.c M src/drivers/intel/gma/intel_ddi.c M src/drivers/intel/gma/vbt.c M src/drivers/ipmi/ipmi_kcs.c M src/drivers/maxim/max77686/max77686.c M src/drivers/net/ne2k.c M src/drivers/net/r8168.c M src/drivers/pc80/pc/i8254.c M src/drivers/pc80/pc/i8259.c M src/drivers/pc80/pc/isa-dma.c M src/drivers/pc80/pc/keyboard.c M src/drivers/pc80/pc/spkmodem.c M src/drivers/pc80/pc/udelay_io.c M src/drivers/pc80/rtc/mc146818rtc.c M src/drivers/pc80/tpm/tis.c M src/drivers/pc80/vga/vga_io.c M src/drivers/ricoh/rce822/rce822.c M src/drivers/sil/3114/sil_sata.c M src/drivers/uart/oxpcie.c M src/drivers/uart/oxpcie_early.c M src/drivers/uart/pl011.c M src/drivers/uart/sifive.c M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/drivers/usb/ehci_debug.c M src/drivers/usb/pci_ehci.c M src/drivers/xgi/common/xgi_coreboot.c M src/drivers/xgi/common/xgi_coreboot.h M src/drivers/xgi/z9s/z9s.c M src/ec/acpi/ec.c M src/ec/compal/ene932/ec.c M src/ec/google/chromeec/crosec_proto.c M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec_i2c.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/common/mec.c M src/ec/google/wilco/bootblock.c M src/ec/google/wilco/mailbox.c M src/ec/hp/kbc1126/early_init.c M src/ec/hp/kbc1126/ec.c M src/ec/lenovo/h8/h8.c M src/ec/lenovo/pmh7/pmh7.c M src/ec/quanta/ene_kb3940q/ec.c M src/ec/quanta/it8518/ec.c M src/ec/smsc/mec1308/ec.c M src/include/device/azalia_device.h M src/include/device/device.h M src/include/device/pci.h M src/include/device/pci_ehci.h M src/include/device/pnp.h M src/include/pc80/mc146818rtc.h M src/include/reg_script.h M src/lib/edid.c M src/lib/reg_script.c M src/mainboard/adi/rcc-dff/romstage.c M src/mainboard/advansus/a785e-i/mainboard.c M src/mainboard/advansus/a785e-i/mptable.c M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bettong/boardid.c M src/mainboard/amd/bettong/mptable.c M src/mainboard/amd/bettong/romstage.c M src/mainboard/amd/bimini_fam10/mainboard.c M src/mainboard/amd/bimini_fam10/mptable.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/db-ft3b-lc/mainboard.c M src/mainboard/amd/db-ft3b-lc/mptable.c M src/mainboard/amd/db-ft3b-lc/romstage.c M src/mainboard/amd/gardenia/mptable.c M src/mainboard/amd/inagua/mptable.c M src/mainboard/amd/lamar/mainboard.c M src/mainboard/amd/lamar/mptable.c M src/mainboard/amd/lamar/romstage.c M src/mainboard/amd/mahogany_fam10/mainboard.c M src/mainboard/amd/mahogany_fam10/mptable.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/olivehill/mptable.c M src/mainboard/amd/olivehill/romstage.c M src/mainboard/amd/olivehillplus/mainboard.c M src/mainboard/amd/olivehillplus/mptable.c M src/mainboard/amd/olivehillplus/romstage.c M src/mainboard/amd/parmer/mptable.c M src/mainboard/amd/parmer/romstage.c M src/mainboard/amd/persimmon/mainboard.c M src/mainboard/amd/persimmon/mptable.c M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c M src/mainboard/amd/south_station/mptable.c M src/mainboard/amd/thatcher/mptable.c M src/mainboard/amd/thatcher/romstage.c M src/mainboard/amd/tilapia_fam10/mainboard.c M src/mainboard/amd/tilapia_fam10/mptable.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/amd/torpedo/acpi_tables.c M src/mainboard/amd/torpedo/fadt.c M src/mainboard/amd/torpedo/mptable.c M src/mainboard/amd/union_station/mptable.c M src/mainboard/aopen/dxplplusu/romstage.c M src/mainboard/apple/macbook21/mainboard.c M src/mainboard/apple/macbook21/romstage.c M src/mainboard/apple/macbook21/smihandler.c M src/mainboard/apple/macbookair4_2/early_southbridge.c M src/mainboard/asrock/e350m1/mainboard.c M src/mainboard/asrock/e350m1/mptable.c M src/mainboard/asrock/imb-a180/mptable.c M src/mainboard/asrock/imb-a180/romstage.c M src/mainboard/asus/am1i-a/mptable.c M src/mainboard/asus/am1i-a/romstage.c M src/mainboard/asus/f2a85-m/mptable.c M src/mainboard/asus/f2a85-m/romstage.c M src/mainboard/asus/kcma-d8/bootblock.c M src/mainboard/asus/kcma-d8/mainboard.c M src/mainboard/asus/kcma-d8/mptable.c M src/mainboard/asus/kcma-d8/romstage.c M src/mainboard/asus/kfsn4-dre/acpi_tables.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/asus/kgpe-d16/bootblock.c M src/mainboard/asus/kgpe-d16/mainboard.c M src/mainboard/asus/kgpe-d16/mptable.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/asus/m4a78-em/mainboard.c M src/mainboard/asus/m4a78-em/mptable.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/mainboard.c M src/mainboard/asus/m4a785-m/mptable.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/mainboard.c M src/mainboard/asus/m5a88-v/mptable.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/asus/maximus_iv_gene-z/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/asus/p5qc/romstage.c M src/mainboard/asus/p8h61-m_lx/romstage.c M src/mainboard/avalue/eax-785e/mainboard.c M src/mainboard/avalue/eax-785e/mptable.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/bap/ode_e20XX/mptable.c M src/mainboard/bap/ode_e20XX/romstage.c M src/mainboard/bap/ode_e21XX/mainboard.c M src/mainboard/bap/ode_e21XX/mptable.c M src/mainboard/bap/ode_e21XX/romstage.c M src/mainboard/biostar/a68n_5200/mptable.c M src/mainboard/biostar/a68n_5200/romstage.c M src/mainboard/biostar/am1ml/mptable.c M src/mainboard/biostar/am1ml/romstage.c M src/mainboard/compulab/intense_pc/romstage.c M src/mainboard/cubietech/cubieboard/bootblock.c M src/mainboard/elmex/pcm205400/mainboard.c M src/mainboard/elmex/pcm205400/mptable.c M src/mainboard/emulation/qemu-armv7/cbmem.c M src/mainboard/emulation/qemu-armv7/mainboard.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/emulation/qemu-i440fx/memory.c M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/emulation/qemu-power8/uart.c M src/mainboard/emulation/qemu-q35/bootblock.c M src/mainboard/emulation/qemu-riscv/uart.c M src/mainboard/emulation/spike-riscv/uart.c M src/mainboard/foxconn/d41s/romstage.c M src/mainboard/getac/p470/ec_oem.c M src/mainboard/getac/p470/mainboard.c M src/mainboard/getac/p470/romstage.c M src/mainboard/getac/p470/smihandler.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/gigabyte/ma785gm/mainboard.c M src/mainboard/gigabyte/ma785gm/mptable.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/mainboard.c M src/mainboard/gigabyte/ma785gmt/mptable.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/mainboard.c M src/mainboard/gigabyte/ma78gm/mptable.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/gizmosphere/gizmo/mainboard.c M src/mainboard/gizmosphere/gizmo/mptable.c M src/mainboard/gizmosphere/gizmo2/mptable.c M src/mainboard/gizmosphere/gizmo2/romstage.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/auron/variant.h M src/mainboard/google/auron/variants/buddy/variant.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/beltino/lan.c M src/mainboard/google/beltino/mainboard.c M src/mainboard/google/beltino/smihandler.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/butterfly/mainboard.c M src/mainboard/google/butterfly/mainboard_smi.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/cyan/com_init.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/eve/smihandler.c M src/mainboard/google/foster/bootblock.c M src/mainboard/google/foster/mainboard.c M src/mainboard/google/foster/reset.c M src/mainboard/google/glados/smihandler.c M src/mainboard/google/gru/bootblock.c M src/mainboard/google/gru/pwm_regulator.c M src/mainboard/google/gru/sdram_configs.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/jecht/mainboard.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kahlee/mptable.c M src/mainboard/google/link/i915.c M src/mainboard/google/link/mainboard.c M src/mainboard/google/link/mainboard_smi.c M src/mainboard/google/link/romstage.c M src/mainboard/google/nyan/bootblock.c M src/mainboard/google/nyan/mainboard.c M src/mainboard/google/nyan/romstage.c M src/mainboard/google/nyan_big/bootblock.c M src/mainboard/google/nyan_big/mainboard.c M src/mainboard/google/nyan_big/romstage.c M src/mainboard/google/nyan_blaze/bootblock.c M src/mainboard/google/nyan_blaze/mainboard.c M src/mainboard/google/nyan_blaze/romstage.c M src/mainboard/google/oak/bootblock.c M src/mainboard/google/oak/mainboard.c M src/mainboard/google/octopus/ec.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/parrot/ec.c M src/mainboard/google/parrot/mainboard.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/google/rambi/mainboard_smi.c M src/mainboard/google/rambi/variants/ninja/lan.c M src/mainboard/google/rambi/variants/sumo/lan.c M src/mainboard/google/slippy/mainboard.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/google/smaug/bootblock.c M src/mainboard/google/smaug/mainboard.c M src/mainboard/google/smaug/reset.c M src/mainboard/google/stout/chromeos.c M src/mainboard/google/stout/ec.c M src/mainboard/google/stout/mainboard.c M src/mainboard/google/stout/mainboard_smi.c M src/mainboard/google/stout/romstage.c M src/mainboard/google/urara/bootblock.c M src/mainboard/google/urara/mainboard.c M src/mainboard/google/veyron/bootblock.c M src/mainboard/google/veyron/mainboard.c M src/mainboard/google/veyron/sdram_configs.c M src/mainboard/google/veyron_mickey/bootblock.c M src/mainboard/google/veyron_mickey/mainboard.c M src/mainboard/google/veyron_mickey/sdram_configs.c M src/mainboard/google/veyron_rialto/bootblock.c M src/mainboard/google/veyron_rialto/mainboard.c M src/mainboard/google/veyron_rialto/romstage.c M src/mainboard/google/veyron_rialto/sdram_configs.c M src/mainboard/hp/2570p/romstage.c M src/mainboard/hp/2760p/romstage.c M src/mainboard/hp/8460p/romstage.c M src/mainboard/hp/8470p/romstage.c M src/mainboard/hp/8770w/romstage.c M src/mainboard/hp/abm/mptable.c M src/mainboard/hp/abm/romstage.c M src/mainboard/hp/compaq_8200_elite_sff/romstage.c M src/mainboard/hp/dl165_g6_fam10/mptable.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/hp/folio_9470m/romstage.c M src/mainboard/hp/pavilion_m6_1035dx/mainboard.c M src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c M src/mainboard/hp/pavilion_m6_1035dx/mptable.c M src/mainboard/hp/revolve_810_g1/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/ibase/mb899/superio_hwm.c M src/mainboard/iei/kino-780am2-fam10/mainboard.c M src/mainboard/iei/kino-780am2-fam10/mptable.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/baskingridge/mainboard.c M src/mainboard/intel/baskingridge/mainboard_smi.c M src/mainboard/intel/bayleybay_fsp/mainboard.c M src/mainboard/intel/bayleybay_fsp/romstage.c M src/mainboard/intel/camelbackmountain_fsp/mainboard.c M src/mainboard/intel/cannonlake_rvp/smihandler.c M src/mainboard/intel/d510mo/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/intel/dcp847ske/superio.h M src/mainboard/intel/dg43gt/romstage.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/emeraldlake2/mainboard.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/intel/emeraldlake2/smihandler.c M src/mainboard/intel/galileo/gpio.c M src/mainboard/intel/galileo/reg_access.c M src/mainboard/intel/glkrvp/ec.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kblrvp/smihandler.c M src/mainboard/intel/kunimitsu/smihandler.c M src/mainboard/intel/littleplains/romstage.c M src/mainboard/intel/mohonpeak/romstage.c M src/mainboard/intel/strago/com_init.c M src/mainboard/intel/strago/smihandler.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/intel/wtm2/mainboard.c M src/mainboard/jetway/nf81-t56n-lf/mainboard.c M src/mainboard/jetway/nf81-t56n-lf/mptable.c M src/mainboard/jetway/pa78vm5/mainboard.c M src/mainboard/jetway/pa78vm5/mptable.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/kontron/986lcd-m/mainboard.c M src/mainboard/kontron/ktqm77/mainboard.c M src/mainboard/lenovo/g505s/mainboard_smi.c M src/mainboard/lenovo/g505s/mptable.c M src/mainboard/lenovo/l520/romstage.c M src/mainboard/lenovo/l520/smihandler.c M src/mainboard/lenovo/s230u/mainboard.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/s230u/smihandler.c M src/mainboard/lenovo/t400/acpi_tables.c M src/mainboard/lenovo/t400/dock.c M src/mainboard/lenovo/t400/romstage.c M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420/smihandler.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t420s/smihandler.c M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t430/smihandler.c M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t430s/smihandler.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t520/smihandler.c M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/t530/smihandler.c M src/mainboard/lenovo/t60/dock.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/t60/smihandler.c M src/mainboard/lenovo/x131e/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/smihandler.c M src/mainboard/lenovo/x200/acpi_tables.c M src/mainboard/lenovo/x200/dock.c M src/mainboard/lenovo/x200/romstage.c M src/mainboard/lenovo/x201/dock.c M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x201/smihandler.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x220/smihandler.c M src/mainboard/lenovo/x230/romstage.c M src/mainboard/lenovo/x230/smihandler.c M src/mainboard/lenovo/x60/dock.c M src/mainboard/lenovo/x60/mainboard.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/x60/smihandler.c M src/mainboard/lenovo/z61t/dock.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/lenovo/z61t/smihandler.c M src/mainboard/lippert/frontrunner-af/mainboard.c M src/mainboard/lippert/frontrunner-af/mptable.c M src/mainboard/lippert/frontrunner-af/sema.c M src/mainboard/lippert/toucan-af/mainboard.c M src/mainboard/lippert/toucan-af/mptable.c M src/mainboard/msi/ms7721/mptable.c M src/mainboard/msi/ms7721/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/packardbell/ms2290/mainboard.c M src/mainboard/packardbell/ms2290/romstage.c M src/mainboard/pcengines/alix1c/romstage.c M src/mainboard/pcengines/alix2d/irq_tables.c M src/mainboard/pcengines/alix2d/romstage.c M src/mainboard/pcengines/apu1/gpio_ftns.c M src/mainboard/pcengines/apu1/mainboard.c M src/mainboard/pcengines/apu1/mptable.c M src/mainboard/pcengines/apu2/gpio_ftns.c M src/mainboard/pcengines/apu2/mainboard.c M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/roda/rk886ex/m3885.c M src/mainboard/roda/rk886ex/mainboard.c M src/mainboard/roda/rk886ex/romstage.c M src/mainboard/roda/rk9/acpi_tables.c M src/mainboard/roda/rk9/mainboard.c M src/mainboard/roda/rk9/romstage.c M src/mainboard/roda/rk9/smihandler.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/lumpy/smihandler.c M src/mainboard/samsung/stumpy/chromeos.c M src/mainboard/samsung/stumpy/romstage.c M src/mainboard/samsung/stumpy/smihandler.c M src/mainboard/sapphire/pureplatinumh61/romstage.c M src/mainboard/siemens/mc_bdx1/mainboard.c M src/mainboard/siemens/mc_tcu3/mainboard.c M src/mainboard/siemens/mc_tcu3/romstage.c M src/mainboard/sifive/hifive-unleashed/mainboard.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/mainboard.c M src/mainboard/supermicro/h8scm_fam10/mptable.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/ti/beaglebone/bootblock.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/mainboard/via/epia-m850/romstage.c M src/northbridge/amd/agesa/family12/northbridge.c M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family14/state_machine.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/amdfam10/amdfam10.h M src/northbridge/amd/amdfam10/amdfam10_util.c M src/northbridge/amd/amdfam10/debug.c M src/northbridge/amd/amdfam10/early_ht.c M src/northbridge/amd/amdfam10/ht_config.c M src/northbridge/amd/amdfam10/northbridge.c M src/northbridge/amd/amdfam10/pci.h M src/northbridge/amd/amdfam10/raminit_amdmct.c M src/northbridge/amd/amdk8/reset_test.c M src/northbridge/amd/lx/grphinit.c M src/northbridge/amd/lx/northbridge.c M src/northbridge/amd/lx/northbridgeinit.c M src/northbridge/amd/lx/raminit.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/amd/pi/ramtop.c M src/northbridge/intel/e7505/debug.c M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/fsp_rangeley/acpi.c M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/fsp_rangeley/port_access.c M src/northbridge/intel/fsp_rangeley/raminit.c M src/northbridge/intel/gm45/bootblock.c M src/northbridge/intel/gm45/early_init.c M src/northbridge/intel/gm45/early_reset.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/gm45/igd.c M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/gm45/pcie.c M src/northbridge/intel/gm45/pm.c M src/northbridge/intel/gm45/ram_calc.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/gm45/raminit_read_write_training.c M src/northbridge/intel/gm45/raminit_receive_enable_calibration.c M src/northbridge/intel/gm45/thermal.c M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/ram_calc.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/haswell/report_platform.c M src/northbridge/intel/i440bx/debug.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i440bx/ram_calc.c M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/i945/bootblock.c M src/northbridge/intel/i945/debug.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/ram_calc.c M src/northbridge/intel/i945/rcven.c M src/northbridge/intel/nehalem/bootblock.c M src/northbridge/intel/nehalem/early_init.c M src/northbridge/intel/nehalem/finalize.c M src/northbridge/intel/nehalem/gma.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/nehalem/ram_calc.c M src/northbridge/intel/nehalem/raminit.c M src/northbridge/intel/pineview/bootblock.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/pineview/ram_calc.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/bootblock.c M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c M src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c M src/northbridge/intel/sandybridge/iommu.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/ram_calc.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_ivy.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/x4x/bootblock.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/early_init.c M src/northbridge/intel/x4x/gma.c M src/northbridge/intel/x4x/northbridge.c M src/northbridge/intel/x4x/ram_calc.c M src/northbridge/intel/x4x/raminit.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/raminit_tables.c M src/northbridge/intel/x4x/rcven.c M src/northbridge/via/vx900/bootblock.c M src/northbridge/via/vx900/chrome9hd.c M src/northbridge/via/vx900/early_smbus.c M src/northbridge/via/vx900/early_vx900.c M src/northbridge/via/vx900/early_vx900.h M src/northbridge/via/vx900/lpc.c M src/northbridge/via/vx900/pcie.c M src/northbridge/via/vx900/raminit_ddr3.c M src/northbridge/via/vx900/vx900.h M src/soc/amd/common/block/pci/amd_pci_util.c M src/soc/amd/common/block/psp/psp.c M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/enable_usbdebug.c M src/soc/amd/stoneyridge/gpio.c M src/soc/amd/stoneyridge/hda.c M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/lpc.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/ramtop.c M src/soc/amd/stoneyridge/reset.c M src/soc/amd/stoneyridge/romstage.c M src/soc/amd/stoneyridge/sata.c M src/soc/amd/stoneyridge/sm.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/amd/stoneyridge/spi.c M src/soc/amd/stoneyridge/tsc_freq.c M src/soc/amd/stoneyridge/usb.c M src/soc/broadcom/cygnus/gpio.c M src/soc/broadcom/cygnus/hw_init.c M src/soc/broadcom/cygnus/i2c.c M src/soc/broadcom/cygnus/iomux.c M src/soc/broadcom/cygnus/ns16550.c M src/soc/broadcom/cygnus/spi.c M src/soc/broadcom/cygnus/timer.c M src/soc/broadcom/cygnus/tz.c M src/soc/broadcom/cygnus/usb.c M src/soc/cavium/cn81xx/bootblock.c M src/soc/cavium/cn81xx/clock.c M src/soc/cavium/cn81xx/cpu.c M src/soc/cavium/cn81xx/ecam0.c M src/soc/cavium/cn81xx/gpio.c M src/soc/cavium/cn81xx/spi.c M src/soc/cavium/cn81xx/timer.c M src/soc/cavium/cn81xx/twsi.c M src/soc/cavium/cn81xx/uart.c M src/soc/cavium/common/bdk-coreboot.c M src/soc/imgtec/pistachio/clocks.c M src/soc/imgtec/pistachio/ddr2_init.c M src/soc/imgtec/pistachio/ddr3_init.c M src/soc/imgtec/pistachio/include/soc/cpu.h M src/soc/imgtec/pistachio/include/soc/spi.h M src/soc/imgtec/pistachio/reset.c M src/soc/imgtec/pistachio/uart.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/cse.c M src/soc/intel/apollolake/include/soc/pci_devs.h M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/apollolake/smihandler.c M src/soc/intel/apollolake/xdci.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/baytrail/dptf.c M src/soc/intel/baytrail/elog.c M src/soc/intel/baytrail/emmc.c M src/soc/intel/baytrail/gfx.c M src/soc/intel/baytrail/hda.c M src/soc/intel/baytrail/include/soc/gpio.h M src/soc/intel/baytrail/iosf.c M src/soc/intel/baytrail/lpe.c M src/soc/intel/baytrail/lpss.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/baytrail/perf_power.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/romstage/early_spi.c M src/soc/intel/baytrail/romstage/gfx.c M src/soc/intel/baytrail/romstage/pmc.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/baytrail/romstage/uart.c M src/soc/intel/baytrail/sata.c M src/soc/intel/baytrail/sd.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/smm.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/baytrail/spi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/braswell/elog.c M src/soc/intel/braswell/emmc.c M src/soc/intel/braswell/gfx.c M src/soc/intel/braswell/hda.c M src/soc/intel/braswell/include/soc/gpio.h M src/soc/intel/braswell/iosf.c M src/soc/intel/braswell/lpe.c M src/soc/intel/braswell/lpss.c M src/soc/intel/braswell/memmap.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/braswell/romstage/early_spi.c M src/soc/intel/braswell/romstage/pmc.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/braswell/sata.c M src/soc/intel/braswell/sd.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/braswell/smm.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/braswell/spi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/bootblock/cpu.c M src/soc/intel/broadwell/bootblock/pch.c M src/soc/intel/broadwell/bootblock/systemagent.c M src/soc/intel/broadwell/ehci.c M src/soc/intel/broadwell/finalize.c M src/soc/intel/broadwell/gpio.c M src/soc/intel/broadwell/hda.c M src/soc/intel/broadwell/igd.c M src/soc/intel/broadwell/include/soc/pci_devs.h M src/soc/intel/broadwell/iobp.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/me_status.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/pch.c M src/soc/intel/broadwell/pmutil.c M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/romstage/power_state.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/romstage/report_platform.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/broadwell/romstage/smbus.c M src/soc/intel/broadwell/romstage/spi.c M src/soc/intel/broadwell/romstage/systemagent.c M src/soc/intel/broadwell/romstage/uart.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/smbus.c M src/soc/intel/broadwell/smbus_common.c M src/soc/intel/broadwell/smi.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/broadwell/spi.c M src/soc/intel/broadwell/systemagent.c M src/soc/intel/broadwell/usb_debug.c M src/soc/intel/broadwell/xhci.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/lockdown.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/romstage/power_state.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/smihandler.h M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/lpss/lpss.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcr/pcr.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/common/block/smbus/smbus_early.c M src/soc/intel/common/block/smbus/smbuslib.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smitraphandler.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/common/hda_verb.c M src/soc/intel/common/pch/lockdown/lockdown.c M src/soc/intel/denverton_ns/bootblock/uart.c M src/soc/intel/denverton_ns/gpio_dnv.c M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/denverton_ns/npk.c M src/soc/intel/denverton_ns/pmc.c M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/denverton_ns/sata.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/denverton_ns/smm.c M src/soc/intel/denverton_ns/soc_util.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/denverton_ns/xhci.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/bootblock/bootblock.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/gfx.c M src/soc/intel/fsp_baytrail/include/soc/gpio.h M src/soc/intel/fsp_baytrail/include/soc/i2c.h M src/soc/intel/fsp_baytrail/iosf.c M src/soc/intel/fsp_baytrail/lpe.c M src/soc/intel/fsp_baytrail/lpss.c M src/soc/intel/fsp_baytrail/memmap.c M src/soc/intel/fsp_baytrail/pmutil.c M src/soc/intel/fsp_baytrail/romstage/pmc.c M src/soc/intel/fsp_baytrail/romstage/report_platform.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_baytrail/romstage/uart.c M src/soc/intel/fsp_baytrail/smihandler.c M src/soc/intel/fsp_baytrail/smm.c M src/soc/intel/fsp_baytrail/southcluster.c M src/soc/intel/fsp_baytrail/spi.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/fsp_broadwell_de/gpio.c M src/soc/intel/fsp_broadwell_de/pmutil.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/smbus.c M src/soc/intel/fsp_broadwell_de/smbus_common.c M src/soc/intel/fsp_broadwell_de/smi.c M src/soc/intel/fsp_broadwell_de/smihandler.c M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/fsp_broadwell_de/southcluster.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/icelake/finalize.c M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/lockdown.c M src/soc/intel/icelake/lpc.c M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/icelake/romstage/power_state.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/quark/include/soc/reg_access.h M src/soc/intel/quark/sd.c M src/soc/intel/quark/spi.c M src/soc/intel/quark/spi_debug.c M src/soc/intel/quark/storage_test.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/lockdown.c M src/soc/intel/skylake/lpc.c M src/soc/intel/skylake/me.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/skylake/thermal.c M src/soc/intel/skylake/vr_config.c M src/soc/mediatek/common/gpio.c M src/soc/mediatek/common/include/soc/pmic_wrap_common.h M src/soc/mediatek/common/mtcmos.c M src/soc/mediatek/common/pll.c M src/soc/mediatek/common/pmic_wrap.c M src/soc/mediatek/common/spi.c M src/soc/mediatek/common/timer.c M src/soc/mediatek/common/uart.c M src/soc/mediatek/common/usb.c M src/soc/mediatek/common/wdt.c M src/soc/mediatek/mt8173/ddp.c M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/dsi.c M src/soc/mediatek/mt8173/emi.c M src/soc/mediatek/mt8173/flash_controller.c M src/soc/mediatek/mt8173/gpio.c M src/soc/mediatek/mt8173/gpio_init.c M src/soc/mediatek/mt8173/i2c.c M src/soc/mediatek/mt8173/memory.c M src/soc/mediatek/mt8173/mmu_operations.c M src/soc/mediatek/mt8173/mt6391.c M src/soc/mediatek/mt8173/pll.c M src/soc/mediatek/mt8173/pmic_wrap.c M src/soc/mediatek/mt8173/spi.c M src/soc/mediatek/mt8173/timer.c M src/soc/mediatek/mt8183/auxadc.c M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/gpio.c M src/soc/mediatek/mt8183/mmu_operations.c M src/soc/mediatek/mt8183/mtcmos.c M src/soc/mediatek/mt8183/pll.c M src/soc/mediatek/mt8183/pmic_wrap.c M src/soc/mediatek/mt8183/spi.c M src/soc/nvidia/tegra/apbmisc.c M src/soc/nvidia/tegra/gpio.c M src/soc/nvidia/tegra/i2c.c M src/soc/nvidia/tegra/pingroup.c M src/soc/nvidia/tegra/pinmux.c M src/soc/nvidia/tegra/usb.c M src/soc/nvidia/tegra124/clock.c M src/soc/nvidia/tegra124/display.c M src/soc/nvidia/tegra124/dma.c M src/soc/nvidia/tegra124/dp.c M src/soc/nvidia/tegra124/include/soc/clock.h M src/soc/nvidia/tegra124/monotonic_timer.c M src/soc/nvidia/tegra124/power.c M src/soc/nvidia/tegra124/sdram.c M src/soc/nvidia/tegra124/soc.c M src/soc/nvidia/tegra124/sor.c M src/soc/nvidia/tegra124/spi.c M src/soc/nvidia/tegra124/uart.c M src/soc/nvidia/tegra210/addressmap.c M src/soc/nvidia/tegra210/ccplex.c M src/soc/nvidia/tegra210/clock.c M src/soc/nvidia/tegra210/cpu.c M src/soc/nvidia/tegra210/dc.c M src/soc/nvidia/tegra210/dma.c M src/soc/nvidia/tegra210/dp.c M src/soc/nvidia/tegra210/dsi.c M src/soc/nvidia/tegra210/flow_ctrl.c M src/soc/nvidia/tegra210/funitcfg.c M src/soc/nvidia/tegra210/include/soc/clock.h M src/soc/nvidia/tegra210/include/soc/id.h M src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c M src/soc/nvidia/tegra210/mipi-phy.c M src/soc/nvidia/tegra210/mipi.c M src/soc/nvidia/tegra210/mipi_dsi.c M src/soc/nvidia/tegra210/monotonic_timer.c M src/soc/nvidia/tegra210/padconfig.c M src/soc/nvidia/tegra210/power.c M src/soc/nvidia/tegra210/ram_code.c M src/soc/nvidia/tegra210/sdram.c M src/soc/nvidia/tegra210/soc.c M src/soc/nvidia/tegra210/sor.c M src/soc/nvidia/tegra210/spi.c M src/soc/nvidia/tegra210/uart.c M src/soc/qualcomm/ipq40xx/blobs_init.c M src/soc/qualcomm/ipq40xx/gpio.c M src/soc/qualcomm/ipq40xx/i2c.c M src/soc/qualcomm/ipq40xx/include/soc/iomap.h M src/soc/qualcomm/ipq40xx/lcc.c M src/soc/qualcomm/ipq40xx/qup.c M src/soc/qualcomm/ipq40xx/spi.c M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/ipq40xx/usb.c M src/soc/qualcomm/ipq806x/blobs_init.c M src/soc/qualcomm/ipq806x/gpio.c M src/soc/qualcomm/ipq806x/gsbi.c M src/soc/qualcomm/ipq806x/i2c.c M src/soc/qualcomm/ipq806x/include/soc/iomap.h M src/soc/qualcomm/ipq806x/lcc.c M src/soc/qualcomm/ipq806x/qup.c M src/soc/qualcomm/ipq806x/spi.c M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/ipq806x/usb.c M src/soc/qualcomm/sdm845/gpio.c M src/soc/rockchip/common/edp.c M src/soc/rockchip/common/gpio.c M src/soc/rockchip/common/i2c.c M src/soc/rockchip/common/include/soc/soc.h M src/soc/rockchip/common/pwm.c M src/soc/rockchip/common/spi.c M src/soc/rockchip/common/vop.c M src/soc/rockchip/rk3288/bootblock.c M src/soc/rockchip/rk3288/clock.c M src/soc/rockchip/rk3288/crypto.c M src/soc/rockchip/rk3288/display.c M src/soc/rockchip/rk3288/gpio.c M src/soc/rockchip/rk3288/hdmi.c M src/soc/rockchip/rk3288/sdram.c M src/soc/rockchip/rk3288/software_i2c.c M src/soc/rockchip/rk3288/timer.c M src/soc/rockchip/rk3288/tsadc.c M src/soc/rockchip/rk3399/bootblock.c M src/soc/rockchip/rk3399/decompressor.c M src/soc/rockchip/rk3399/display.c M src/soc/rockchip/rk3399/gpio.c M src/soc/rockchip/rk3399/mipi.c M src/soc/rockchip/rk3399/saradc.c M src/soc/rockchip/rk3399/sdram.c M src/soc/rockchip/rk3399/timer.c M src/soc/rockchip/rk3399/tsadc.c M src/soc/rockchip/rk3399/usb.c M src/soc/samsung/exynos5250/clock.c M src/soc/samsung/exynos5250/dmc_common.c M src/soc/samsung/exynos5250/dmc_init_ddr3.c M src/soc/samsung/exynos5250/dp-reg.c M src/soc/samsung/exynos5250/fb.c M src/soc/samsung/exynos5250/i2c.c M src/soc/samsung/exynos5250/include/soc/cpu.h M src/soc/samsung/exynos5250/power.c M src/soc/samsung/exynos5250/spi.c M src/soc/samsung/exynos5250/timer.c M src/soc/samsung/exynos5250/tmu.c M src/soc/samsung/exynos5250/trustzone.c M src/soc/samsung/exynos5250/uart.c M src/soc/samsung/exynos5250/usb.c M src/soc/samsung/exynos5420/clock.c M src/soc/samsung/exynos5420/dmc_common.c M src/soc/samsung/exynos5420/dmc_init_ddr3.c M src/soc/samsung/exynos5420/dp.c M src/soc/samsung/exynos5420/dp_lowlevel.c M src/soc/samsung/exynos5420/fimd.c M src/soc/samsung/exynos5420/i2c.c M src/soc/samsung/exynos5420/include/soc/cpu.h M src/soc/samsung/exynos5420/power.c M src/soc/samsung/exynos5420/smp.c M src/soc/samsung/exynos5420/spi.c M src/soc/samsung/exynos5420/timer.c M src/soc/samsung/exynos5420/tmu.c M src/soc/samsung/exynos5420/trustzone.c M src/soc/samsung/exynos5420/uart.c M src/soc/samsung/exynos5420/usb.c M src/soc/sifive/fu540/bootblock.c M src/soc/sifive/fu540/clint.c M src/soc/sifive/fu540/clock.c M src/soc/sifive/fu540/otp.c M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/enable_usbdebug.c M src/southbridge/amd/agesa/hudson/fadt.c M src/southbridge/amd/agesa/hudson/hda.c M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/agesa/hudson/imc.c M src/southbridge/amd/agesa/hudson/lpc.c M src/southbridge/amd/agesa/hudson/ramtop.c M src/southbridge/amd/agesa/hudson/reset.c M src/southbridge/amd/agesa/hudson/sata.c M src/southbridge/amd/agesa/hudson/sd.c M src/southbridge/amd/agesa/hudson/sm.c M src/southbridge/amd/agesa/hudson/smi.h M src/southbridge/amd/agesa/hudson/spi.c M src/southbridge/amd/agesa/hudson/usb.c M src/southbridge/amd/amd8111/acpi.c M src/southbridge/amd/amd8111/bootblock.c M src/southbridge/amd/amd8111/nic.c M src/southbridge/amd/amd8111/reset.c M src/southbridge/amd/amd8111/smbus.c M src/southbridge/amd/amd8111/usb.c M src/southbridge/amd/cimx/cimx_util.c M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/cimx/sb800/cfg.c M src/southbridge/amd/cimx/sb800/early.c M src/southbridge/amd/cimx/sb800/fadt.c M src/southbridge/amd/cimx/sb800/lpc.c M src/southbridge/amd/cimx/sb800/ramtop.c M src/southbridge/amd/cimx/sb800/reset.c M src/southbridge/amd/cimx/sb800/smbus.c M src/southbridge/amd/cimx/sb800/spi.c M src/southbridge/amd/cimx/sb900/bootblock.c M src/southbridge/amd/cimx/sb900/early.c M src/southbridge/amd/cimx/sb900/ramtop.c M src/southbridge/amd/cimx/sb900/reset.c M src/southbridge/amd/cimx/sb900/smbus.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/amd/cs5536/cs5536.c M src/southbridge/amd/cs5536/early_setup.c M src/southbridge/amd/cs5536/early_smbus.c M src/southbridge/amd/cs5536/smbus.c M src/southbridge/amd/pi/hudson/bootblock.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/enable_usbdebug.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/amd/pi/hudson/gpio.c M src/southbridge/amd/pi/hudson/hda.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/pi/hudson/imc.c M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/amd/pi/hudson/reset.c M src/southbridge/amd/pi/hudson/sata.c M src/southbridge/amd/pi/hudson/sd.c M src/southbridge/amd/pi/hudson/sm.c M src/southbridge/amd/pi/hudson/smi.h M src/southbridge/amd/pi/hudson/usb.c M src/southbridge/amd/rs780/cmn.c M src/southbridge/amd/rs780/early_setup.c M src/southbridge/amd/rs780/rs780.c M src/southbridge/amd/sb700/bootblock.c M src/southbridge/amd/sb700/early_setup.c M src/southbridge/amd/sb700/enable_usbdebug.c M src/southbridge/amd/sb700/fadt.c M src/southbridge/amd/sb700/hda.c M src/southbridge/amd/sb700/lpc.c M src/southbridge/amd/sb700/pmio.c M src/southbridge/amd/sb700/ramtop.c M src/southbridge/amd/sb700/reset.c M src/southbridge/amd/sb700/sata.c M src/southbridge/amd/sb700/sb700.c M src/southbridge/amd/sb700/sm.c M src/southbridge/amd/sb700/smbus.h M src/southbridge/amd/sb700/spi.c M src/southbridge/amd/sb700/usb.c M src/southbridge/amd/sb800/bootblock.c M src/southbridge/amd/sb800/enable_usbdebug.c M src/southbridge/amd/sb800/fadt.c M src/southbridge/amd/sb800/hda.c M src/southbridge/amd/sb800/lpc.c M src/southbridge/amd/sb800/ramtop.c M src/southbridge/amd/sb800/reset.c M src/southbridge/amd/sb800/sata.c M src/southbridge/amd/sb800/sb800.c M src/southbridge/amd/sb800/sm.c M src/southbridge/amd/sb800/usb.c M src/southbridge/amd/sr5650/cmn.h M src/southbridge/amd/sr5650/early_setup.c M src/southbridge/amd/sr5650/sr5650.c M src/southbridge/broadcom/bcm5785/bootblock.c M src/southbridge/broadcom/bcm5785/lpc.c M src/southbridge/broadcom/bcm5785/reset.c M src/southbridge/broadcom/bcm5785/sata.c M src/southbridge/broadcom/bcm5785/sb_pci_main.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/early_me.c M src/southbridge/intel/bd82x6x/early_me_mrc.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/early_pch_common.c M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/early_spi.c M src/southbridge/intel/bd82x6x/early_thermal.c M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/early_usb_mrc.c M src/southbridge/intel/bd82x6x/elog.c M src/southbridge/intel/bd82x6x/finalize.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/smbus.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/bd82x6x/usb_ehci.c M src/southbridge/intel/bd82x6x/usb_xhci.c M src/southbridge/intel/bd82x6x/watchdog.c M src/southbridge/intel/common/acpi_pirq_gen.c M src/southbridge/intel/common/gpio.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/smbus.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/common/usb_debug.c M src/southbridge/intel/fsp_rangeley/acpi.c M src/southbridge/intel/fsp_rangeley/early_init.c M src/southbridge/intel/fsp_rangeley/early_smbus.c M src/southbridge/intel/fsp_rangeley/early_spi.c M src/southbridge/intel/fsp_rangeley/early_usb.c M src/southbridge/intel/fsp_rangeley/gpio.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/fsp_rangeley/sata.c M src/southbridge/intel/fsp_rangeley/smbus.c M src/southbridge/intel/fsp_rangeley/spi.c M src/southbridge/intel/fsp_rangeley/watchdog.c M src/southbridge/intel/i82371eb/bootblock.c M src/southbridge/intel/i82371eb/early_pm.c M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82371eb/reset.c M src/southbridge/intel/i82371eb/smbus.c M src/southbridge/intel/i82371eb/wakeup.c M src/southbridge/intel/i82801dx/ac97.c M src/southbridge/intel/i82801dx/bootblock.c M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801dx/smi.c M src/southbridge/intel/i82801dx/smihandler.c M src/southbridge/intel/i82801gx/ac97.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/bootblock.c M src/southbridge/intel/i82801gx/early_lpc.c M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/smbus.c M src/southbridge/intel/i82801gx/smi.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801gx/usb_ehci.c M src/southbridge/intel/i82801gx/watchdog.c M src/southbridge/intel/i82801ix/bootblock.c M src/southbridge/intel/i82801ix/dmi_setup.c M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801ix/hdaudio.c M src/southbridge/intel/i82801ix/i82801ix.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801ix/smbus.c M src/southbridge/intel/i82801ix/smi.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801ix/thermal.c M src/southbridge/intel/i82801jx/bootblock.c M src/southbridge/intel/i82801jx/early_lpc.c M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/i82801jx/i82801jx.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/i82801jx/smbus.c M src/southbridge/intel/i82801jx/smi.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/i82801jx/thermal.c M src/southbridge/intel/i82870/pci_parity.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/ibexpeak/early_thermal.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/madt.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/ibexpeak/smbus.c M src/southbridge/intel/ibexpeak/smi.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/ibexpeak/thermal.c M src/southbridge/intel/ibexpeak/usb_ehci.c M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/early_me.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/early_smbus.c M src/southbridge/intel/lynxpoint/early_spi.c M src/southbridge/intel/lynxpoint/early_usb.c M src/southbridge/intel/lynxpoint/elog.c M src/southbridge/intel/lynxpoint/finalize.c M src/southbridge/intel/lynxpoint/hda_verb.c M src/southbridge/intel/lynxpoint/lp_gpio.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pmutil.c M src/southbridge/intel/lynxpoint/rcba.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/smbus.c M src/southbridge/intel/lynxpoint/smi.c M src/southbridge/intel/lynxpoint/smihandler.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c M src/southbridge/intel/lynxpoint/watchdog.c M src/southbridge/nvidia/ck804/bootblock.c M src/southbridge/nvidia/ck804/ck804.c M src/southbridge/nvidia/ck804/early_smbus.c M src/southbridge/nvidia/ck804/enable_usbdebug.c M src/southbridge/nvidia/ck804/lpc.c M src/southbridge/nvidia/ck804/nic.c M src/southbridge/nvidia/ck804/reset.c M src/southbridge/nvidia/ck804/smbus.c M src/southbridge/nvidia/mcp55/azalia.c M src/southbridge/nvidia/mcp55/bootblock.c M src/southbridge/nvidia/mcp55/early_ctrl.c M src/southbridge/nvidia/mcp55/early_smbus.c M src/southbridge/nvidia/mcp55/enable_usbdebug.c M src/southbridge/nvidia/mcp55/fadt.c M src/southbridge/nvidia/mcp55/lpc.c M src/southbridge/nvidia/mcp55/mcp55.c M src/southbridge/nvidia/mcp55/nic.c M src/southbridge/nvidia/mcp55/reset.c M src/southbridge/nvidia/mcp55/smbus.c M src/southbridge/ricoh/rl5c476/rl5c476.c M src/southbridge/ti/pci1x2x/pci1x2x.c M src/southbridge/ti/pci7420/cardbus.c M src/southbridge/ti/pci7420/firewire.c M src/southbridge/ti/pcixx12/pcixx12.c M src/southbridge/via/common/via_early_smbus.h M src/superio/common/conf_mode.c M src/superio/fintek/common/early_serial.c M src/superio/fintek/common/fintek.h M src/superio/fintek/f71805f/superio.c M src/superio/fintek/f71808a/f71808a_hwm.c M src/superio/fintek/f71808a/f71808a_multifunc.c M src/superio/fintek/f71808a/fintek_internal.h M src/superio/fintek/f71808a/superio.c M src/superio/fintek/f71859/superio.c M src/superio/fintek/f71863fg/superio.c M src/superio/fintek/f71869ad/f71869ad_hwm.c M src/superio/fintek/f71869ad/f71869ad_multifunc.c M src/superio/fintek/f71869ad/fintek_internal.h M src/superio/fintek/f71869ad/superio.c M src/superio/fintek/f71872/superio.c M src/superio/fintek/f81216h/early_serial.c M src/superio/fintek/f81216h/superio.c M src/superio/fintek/f81865f/superio.c M src/superio/fintek/f81866d/f81866d_hwm.c M src/superio/fintek/f81866d/f81866d_uart.c M src/superio/fintek/f81866d/fintek_internal.h M src/superio/fintek/f81866d/superio.c M src/superio/intel/i8900/early_serial.c M src/superio/intel/i8900/superio.c M src/superio/ite/common/early_serial.c M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/ite.h M src/superio/ite/it8623e/superio.c M src/superio/ite/it8671f/early_serial.c M src/superio/ite/it8671f/it8671f.h M src/superio/ite/it8712f/superio.c M src/superio/ite/it8716f/superio.c M src/superio/ite/it8718f/early_serial.c M src/superio/ite/it8718f/it8718f.h M src/superio/ite/it8728f/superio.c M src/superio/ite/it8772f/early_init.c M src/superio/ite/it8772f/it8772f.h M src/superio/ite/it8772f/superio.c M src/superio/ite/it8783ef/it8783ef.h M src/superio/nsc/pc87309/early_serial.c M src/superio/nsc/pc87309/pc87309.h M src/superio/nsc/pc87309/superio.c M src/superio/nsc/pc87360/early_serial.c M src/superio/nsc/pc87360/pc87360.h M src/superio/nsc/pc87360/superio.c M src/superio/nsc/pc87366/early_serial.c M src/superio/nsc/pc87366/pc87366.h M src/superio/nsc/pc87366/superio.c M src/superio/nsc/pc87382/superio.c M src/superio/nsc/pc87384/superio.c M src/superio/nsc/pc87392/early_serial.c M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/early_init.c M src/superio/nsc/pc87417/early_serial.c M src/superio/nsc/pc87417/pc87417.h M src/superio/nsc/pc87417/superio.c M src/superio/nsc/pc97317/early_serial.c M src/superio/nsc/pc97317/pc97317.h M src/superio/nsc/pc97317/superio.c M src/superio/nuvoton/common/early_serial.c M src/superio/nuvoton/common/nuvoton.h M src/superio/nuvoton/nct5104d/early_init.c M src/superio/nuvoton/nct5104d/superio.c M src/superio/nuvoton/nct5572d/superio.c M src/superio/nuvoton/nct6776/superio.c M src/superio/nuvoton/nct6779d/superio.c M src/superio/nuvoton/nct6791d/superio.c M src/superio/nuvoton/npcd378/superio.c M src/superio/nuvoton/wpcm450/early_init.c M src/superio/nuvoton/wpcm450/superio.c M src/superio/renesas/m3885x/superio.c M src/superio/serverengines/pilot/early_init.c M src/superio/serverengines/pilot/early_serial.c M src/superio/smsc/dme1737/dme1737.h M src/superio/smsc/dme1737/early_serial.c M src/superio/smsc/dme1737/superio.c M src/superio/smsc/kbc1100/early_init.c M src/superio/smsc/kbc1100/kbc1100.h M src/superio/smsc/kbc1100/superio.c M src/superio/smsc/lpc47b272/early_serial.c M src/superio/smsc/lpc47b272/lpc47b272.h M src/superio/smsc/lpc47b272/superio.c M src/superio/smsc/lpc47b397/early_serial.c M src/superio/smsc/lpc47b397/lpc47b397.h M src/superio/smsc/lpc47b397/superio.c M src/superio/smsc/lpc47m10x/early_serial.c M src/superio/smsc/lpc47m10x/lpc47m10x.h M src/superio/smsc/lpc47m10x/superio.c M src/superio/smsc/lpc47m15x/early_serial.c M src/superio/smsc/lpc47m15x/lpc47m15x.h M src/superio/smsc/lpc47m15x/superio.c M src/superio/smsc/lpc47n207/early_serial.c M src/superio/smsc/lpc47n207/lpc47n207.h M src/superio/smsc/lpc47n217/early_serial.c M src/superio/smsc/lpc47n217/lpc47n217.h M src/superio/smsc/lpc47n217/superio.c M src/superio/smsc/lpc47n227/early_serial.c M src/superio/smsc/lpc47n227/superio.c M src/superio/smsc/mec1308/superio.c M src/superio/smsc/sch4037/sch4037_early_init.c M src/superio/smsc/sch4037/superio.c M src/superio/smsc/sio1007/early_serial.c M src/superio/smsc/sio1036/sio1036.h M src/superio/smsc/sio1036/sio1036_early_init.c M src/superio/smsc/sio1036/superio.c M src/superio/smsc/smscsuperio/early_serial.c M src/superio/smsc/smscsuperio/smscsuperio.h M src/superio/smsc/smscsuperio/superio.c M src/superio/via/vt1211/superio.c M src/superio/winbond/common/early_init.c M src/superio/winbond/common/winbond.h M src/superio/winbond/w83627dhg/early_serial.c M src/superio/winbond/w83627dhg/superio.c M src/superio/winbond/w83627dhg/w83627dhg.h M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c M src/superio/winbond/w83627thg/superio.c M src/superio/winbond/w83627thg/w83627thg.h M src/superio/winbond/w83627uhg/superio.c M src/superio/winbond/w83667hg-a/superio.c M src/superio/winbond/w83697hf/superio.c M src/superio/winbond/w83977tf/superio.c M src/superio/winbond/wpcd376i/early_serial.c M src/superio/winbond/wpcd376i/superio.c M src/superio/winbond/wpcd376i/wpcd376i.h M util/uio_usbdebug/uio_usbdebug_intel.c 1,357 files changed, 1,359 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/29947/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a3deea676308e2dc703b5e06558b05235191044 Gerrit-Change-Number: 29947 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: [WIP]opencelluar: Add EC interface
by Patrick Rudolph (Code Review) 30 Nov '18

30 Nov '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29946 Change subject: [WIP]opencelluar: Add EC interface ...................................................................... [WIP]opencelluar: Add EC interface Add the EC driver that uses the OpenCellular Management Protocol. Implement the board_reset() method using introduced methods. Change-Id: I67eb4ee8e0ad297a8d1984d55102146688c291fc Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A src/ec/opencellular/tiva/Kconfig A src/ec/opencellular/tiva/Makefile.inc A src/ec/opencellular/tiva/ec.c A src/ec/opencellular/tiva/ec.h M src/mainboard/opencellular/elgon/Kconfig M src/mainboard/opencellular/elgon/Makefile.inc A src/mainboard/opencellular/elgon/reset.c 7 files changed, 327 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/29946/1 diff --git a/src/ec/opencellular/tiva/Kconfig b/src/ec/opencellular/tiva/Kconfig new file mode 100644 index 0000000..a56b06a --- /dev/null +++ b/src/ec/opencellular/tiva/Kconfig @@ -0,0 +1,5 @@ +config EC_OPENCELLULAR_TIVA + bool + depends on CONSOLE_SERIAL + help + OpenCellular Tiva EC protocol driver over serial. diff --git a/src/ec/opencellular/tiva/Makefile.inc b/src/ec/opencellular/tiva/Makefile.inc new file mode 100644 index 0000000..fadaf44 --- /dev/null +++ b/src/ec/opencellular/tiva/Makefile.inc @@ -0,0 +1,9 @@ +ifeq ($(CONFIG_EC_OPENCELLULAR_TIVA),y) + +bootblock-y += ec.c +romstage-y += ec.c +verstage-y += ec.c +postcar-y += ec.c +ramstage-y += ec.c + +endif diff --git a/src/ec/opencellular/tiva/ec.c b/src/ec/opencellular/tiva/ec.c new file mode 100644 index 0000000..d46f284 --- /dev/null +++ b/src/ec/opencellular/tiva/ec.c @@ -0,0 +1,203 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <string.h> +#include <console/uart.h> +#include "ec.h" + +/* Packet definition as per OpenCellular Management Protocol */ +enum ec_iface { + EC_UART = 1, + EC_ETHERNET = 2, + EC_SBD = 3, + EC_USB = 4, +}; + +struct ec_header { + uint8_t sof; + uint8_t len; + uint8_t iface; + uint32_t seq; + uint32_t ts; +} __packed; + +struct ec_payload { + uint8_t subsystem; + uint8_t component_id; + uint8_t message_type; + uint8_t action_type; + uint16_t parameter_info; + uint8_t message[48]; +} __packed; + +struct ec_packet { + struct ec_header hdr; + struct ec_payload pld; +} __packed; + +struct ec_msg { + union { + struct ec_packet p; + uint8_t raw[sizeof(struct ec_packet)]; + }; +}; + +/* Create a packet to BMS:TIVA from given arguments */ +static size_t ec_create_tx_msg(struct ec_packet *p, + const enum ec_message_type mt, + const enum ec_action_type at, + const uint8_t parameter_info, + const enum ec_iface iface, + const uint8_t *data_in, + const uint8_t data_in_len) +{ + size_t len = sizeof(*p) - sizeof(p->pld.message) + data_in_len; + + p->pld.subsystem = EC_BMS; + p->pld.component_id = EC_TIVA; + p->pld.message_type = mt; + p->pld.action_type = at; + p->pld.parameter_info = parameter_info; + if (data_in) + memcpy(&p->pld.message, data_in, data_in_len); + + p->hdr.iface = iface; + p->hdr.len = data_in_len; + p->hdr.sof = 0x55; + p->hdr.ts = 0; /* Reserved for future use */ + p->hdr.seq = 0; /* Reserved for future use */ + + return len; +} + +/* Returns true on valid header */ +static bool ec_verify_rx_hdr(struct ec_packet *p, const enum ec_iface iface) +{ + if (p->hdr.sof != 0x55) + return false; + if (p->hdr.len > 48) + return false; + if (p->hdr.iface != iface) + return false; + return true; +} + + +/* Returns true on valid packet */ +static bool ec_verify_rx_msg(struct ec_packet *p, const enum ec_iface iface) +{ + if (!ec_verify_rx_hdr(p, iface)) + return false; + if (p->pld.subsystem != EC_BMS) + return false; + if (p->pld.component_id != EC_TIVA) + return false; + + return true; +} + +/** + * Transmits a packet to EC using one of the UARTs. + * The function is blocking until a data has been transmitted. + * + * All pointers can be NULL if not required. + * + * @param uart_idx The UART connected to EC + * @param mt Message type to transmit + * @param at Action type to transmit + * @param parameter_info Parameter info to transmit + * @param data_in Buffer to data to transmit + * @param data_in_len Length of data to transmit + * + * @return Zero on success, negative on failure + */ +int ec_transmit_msg_uart(const uint8_t uart_idx, + const enum ec_message_type mt, + const enum ec_action_type at, + const uint8_t parameter_info, + const uint8_t *data_in, + const uint8_t data_in_len) +{ + struct ec_msg msg; + + size_t len = ec_create_tx_msg(&msg.p, mt, at, parameter_info, EC_UART, + data_in, data_in_len); + + for (size_t i = 0; i < len; i++) + uart_tx_byte(uart_idx, msg.raw[i]); + + return 0; +} + +/** + * Receives a packet from EC using one of the UARTs. + * The function is blocking and waits for a SOF byte. + * + * The caller must provide a data buffer of size 48. + * If no data buffer is provided the received data (if any) is dropped. + * + * All pointers can be NULL if not required. + * + * @param uart_idx The UART connected to EC + * @param mt Receveived message type + * @param at Receveived action type + * @param parameter_info Receveived parameter info + * @param data_out Buffer to place receveived data + * @param data_out_len Length of received data + * + * @return Zero on success, negative on failure + */ +int ec_receive_msg_uart(const uint8_t uart_idx, + enum ec_message_type *mt, + enum ec_action_type *at, + uint8_t *parameter_info, + uint8_t *data_out, + uint8_t *data_out_len) +{ + struct ec_msg msg; + + do { + msg.raw[0] = uart_rx_byte(uart_idx); + } while (msg.raw[0] != 0x55); + + for (size_t i = 0; i < sizeof(struct ec_header); i++) + msg.raw[i] = uart_rx_byte(uart_idx); + + if (!ec_verify_rx_hdr(&msg.p, EC_UART)) + return -1; + + const size_t len = sizeof(msg.p.pld) - sizeof(msg.p.pld.message) + + msg.p.hdr.len; + + for (size_t i = 0; i < len; i++) + msg.raw[sizeof(struct ec_header) + i] = uart_rx_byte(uart_idx); + + if (!ec_verify_rx_msg(&msg.p, EC_UART)) + return -1; + + if (mt) + *mt = msg.p.pld.message_type; + if (at) + *at = msg.p.pld.action_type; + if (parameter_info) + *parameter_info = msg.p.pld.parameter_info; + if (data_out) + memcpy(data_out, msg.p.pld.message, msg.p.hdr.len); + if (*data_out_len) + *data_out_len = msg.p.hdr.len; + return 0; +} + diff --git a/src/ec/opencellular/tiva/ec.h b/src/ec/opencellular/tiva/ec.h new file mode 100644 index 0000000..7728f7e --- /dev/null +++ b/src/ec/opencellular/tiva/ec.h @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> + +/** + * Command interface as per OpenCellular Management Protocol: + * + * This protocol allows to handle all the configuration, status and alert + * processing through a ‘Request-Response’ mechanism between host and MCU. + */ + +enum ec_subsystem { + EC_SYSTEM = 0, + EC_POWER = 1, + EC_BMS = 2, + EC_HCI = 3, + EC_ETHERNET_SWITCH = 4, + EC_OBC = 5, + EC_GPP = 6, + EC_SDR = 7, + EC_RF = 8, + EC_SYNC = 9, + EC_TEST_MODULE = 10, + EC_WATCHDOG = 11, + EC_ALERT_MANAGER = 12 +}; + +/* We only support subsystem BMS here */ +enum ec_subsystem_bms { + EC_ALL = 0, + EC_TIVA = 1, +}; + +enum ec_message_type { + EC_CONFIG = 1, + EC_STATUS = 2, + EC_ALERT = 3, + EC_COMMAND = 4, +}; + +enum ec_action_type { + EC_GET = 1, + EC_SET = 2, + EC_REPLY = 3, + EC_ACTIVE = 4, + EC_CLEAR = 5, + EC_RESET = 6, + EC_ENABLE = 7, + EC_DISABLE = 8, +}; + +int ec_transmit_msg_uart(const uint8_t uart_idx, + const enum ec_message_type mt, + const enum ec_action_type at, + const uint8_t parameter_info, + const uint8_t *data_in, + const uint8_t data_in_len); + +int ec_receive_msg_uart(const uint8_t uart_idx, + enum ec_message_type *mt, + enum ec_action_type *at, + uint8_t *parameter_info, + uint8_t *data_out, + uint8_t *data_out_len); diff --git a/src/mainboard/opencellular/elgon/Kconfig b/src/mainboard/opencellular/elgon/Kconfig index 3ba2a60..b9f93ab 100644 --- a/src/mainboard/opencellular/elgon/Kconfig +++ b/src/mainboard/opencellular/elgon/Kconfig @@ -25,7 +25,7 @@ select SPI_FLASH_WINBOND select MAINBOARD_HAS_I2C_TPM_GENERIC select MAINBOARD_HAS_TPM1 - select MISSING_BOARD_RESET + select EC_OPENCELLULAR_TIVA config VBOOT select VBOOT_NO_BOARD_SUPPORT diff --git a/src/mainboard/opencellular/elgon/Makefile.inc b/src/mainboard/opencellular/elgon/Makefile.inc index 343a52e..3440833 100644 --- a/src/mainboard/opencellular/elgon/Makefile.inc +++ b/src/mainboard/opencellular/elgon/Makefile.inc @@ -16,16 +16,20 @@ bootblock-y += bootblock.c bootblock-y += memlayout.ld bootblock-y += death.c +bootblock-y += reset.c romstage-y += memlayout.ld romstage-y += romstage.c romstage-y += bdk_devicetree.c romstage-y += death.c +romstage-y += reset.c ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += bdk_devicetree.c ramstage-y += death.c +ramstage-y += reset.c verstage-y += memlayout.ld verstage-y += death.c +verstage-y += reset.c diff --git a/src/mainboard/opencellular/elgon/reset.c b/src/mainboard/opencellular/elgon/reset.c new file mode 100644 index 0000000..d73d9af --- /dev/null +++ b/src/mainboard/opencellular/elgon/reset.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/opencellular/tiva/ec.h> +#include <reset.h> +#include <soc/gpio.h> +#include "mainboard.h" + +void do_board_reset(void) +{ + /* Route UART0 to EC */ + gpio_output(ELGON_GPIO_UART_SEL, 1); + + ec_transmit_msg_uart(0, EC_COMMAND, EC_RESET, 0, NULL, 0); + /* FIXME: Is there a response ? */ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67eb4ee8e0ad297a8d1984d55102146688c291fc Gerrit-Change-Number: 29946 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: riscv: add support to select the privilege level of the payload running
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29494 ) Change subject: riscv: add support to select the privilege level of the payload running ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/#/c/29494/10/src/arch/riscv/boot.c File src/arch/riscv/boot.c: https://review.coreboot.org/#/c/29494/10/src/arch/riscv/boot.c@49 PS10, Line 49: void (*doit)(void *) = prog_entry(prog); function definition argument 'void *' should also have an identifier name -- To view, visit https://review.coreboot.org/c/coreboot/+/29494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951 Gerrit-Change-Number: 29494 Gerrit-PatchSet: 10 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 30 Nov 2018 07:09:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: riscv: add support to select the privilege level of the payload running
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29494 ) Change subject: riscv: add support to select the privilege level of the payload running ...................................................................... Patch Set 9: (4 comments) https://review.coreboot.org/#/c/29494/9/src/arch/riscv/boot.c File src/arch/riscv/boot.c: https://review.coreboot.org/#/c/29494/9/src/arch/riscv/boot.c@43 PS9, Line 43: void (*fn)(uintptr_t, uintptr_t) = prog_entry(prog); function definition argument 'uintptr_t' should also have an identifier name https://review.coreboot.org/#/c/29494/9/src/arch/riscv/boot.c@43 PS9, Line 43: void (*fn)(uintptr_t, uintptr_t) = prog_entry(prog); function definition argument 'uintptr_t' should also have an identifier name https://review.coreboot.org/#/c/29494/9/src/arch/riscv/boot.c@49 PS9, Line 49: void (*doit)(void *) = prog_entry(prog); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/29494/9/src/arch/riscv/payload.c File src/arch/riscv/payload.c: https://review.coreboot.org/#/c/29494/9/src/arch/riscv/payload.c@28 PS9, Line 28: uintptr_t status = read_csr(mstatus) trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/29494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951 Gerrit-Change-Number: 29494 Gerrit-PatchSet: 9 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 30 Nov 2018 07:05:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: riscv: add support to select the privilege level of the payload running
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29494 ) Change subject: riscv: add support to select the privilege level of the payload running ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/#/c/29494/8/src/arch/riscv/boot.c File src/arch/riscv/boot.c: https://review.coreboot.org/#/c/29494/8/src/arch/riscv/boot.c@50 PS8, Line 50: void (*doit)(void *) = prog_entry(prog); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/29494/8/src/arch/riscv/payload.c File src/arch/riscv/payload.c: https://review.coreboot.org/#/c/29494/8/src/arch/riscv/payload.c@28 PS8, Line 28: uintptr_t status = read_csr(mstatus) trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/29494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951 Gerrit-Change-Number: 29494 Gerrit-PatchSet: 8 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 30 Nov 2018 07:00:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Update USB port info
by Furquan Shaikh (Code Review) 30 Nov '18

30 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29912 ) Change subject: mb/google/fizz/variants/karma: Update USB port info ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7383b3d676fd7c775a6d749c70af65b28cf941eb Gerrit-Change-Number: 29912 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 04:19:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Disable native SD card controller
by Furquan Shaikh (Code Review) 30 Nov '18

30 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29918 ) Change subject: mb/google/fizz/variants/karma: Disable native SD card controller ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68dc9be511a370d882e4656c165efbe5dc6ee52e Gerrit-Change-Number: 29918 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 04:17:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2018