Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29854 )
Change subject: smmstore: update smm store filename to use an underscore
......................................................................
Patch Set 1: Code-Review+2
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Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29830 )
Change subject: mb/google/sarien/variants/sarien: Enable melf touchscreen
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/29830/2/src/mainboard/google/sarien/variant…
File src/mainboard/google/sarien/variants/sarien/devicetree.cb:
https://review.coreboot.org/#/c/29830/2/src/mainboard/google/sarien/variant…
PS2, Line 124: GPP_B13
There does not seem to be a dedicated touchscreen reset pin, this is PLTRST and doesn't seem like what we should be using.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29945
to look at the new patch set (#2).
Change subject: google/sarien: Increase BIOS region to 28MB
......................................................................
google/sarien: Increase BIOS region to 28MB
Platform have a 32MB SPI chip, so we can increase the bios region from
16MB to 28MB.
BUG=b:119267832
TEST=Build and boot fine on sarien platform.
Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524
Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com>
---
M src/mainboard/google/sarien/chromeos.fmd
1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/29945/2
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29928 )
Change subject: soc/intel/baytrail: Improve CAR setup
......................................................................
Patch Set 2: Code-Review+1
tested on google/squawks in conjunction with 29929/30
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29929 )
Change subject: soc/intel/baytrail: Use postcar_frame functions to set up frame
......................................................................
Patch Set 2: Code-Review+1
tested on google/squawks in conjunction with 29928/30
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29930 )
Change subject: soc/intel/baytrail: Implement POSTCAR stage
......................................................................
Patch Set 2: Code-Review+1
tested on google/squawks in conjunction with 29928/29
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Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29944
Change subject: soc/intel/common: Limit BIOS region cache to 16MB
......................................................................
soc/intel/common: Limit BIOS region cache to 16MB
Cache BIOS region can boost boot performance, however it can't be over
16MB, according to processor EDS vol1, FLASH+APIC LT will be less than
20MB under 4G. Set the maxiam to 16GB to save numbers of mtrr entries.
BUG=b:119267832
TEST=Build and boot up fine on whiskeylake rvp platform.
Change-Id: I46a47c8bf66b14fb2fcb7b6b1d30d02886c450a4
Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com>
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/29944/1
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 5ff0872..8649f0c 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -240,6 +240,10 @@
if (!bios_size)
return;
+ /* Cache up to 16MB to boost boot performace */
+ if (bios_size > 16 * MiB)
+ bios_size = 16 * MiB;
+
/* Round to power of two */
alignment = 1UL << (log2_ceil(bios_size));
bios_size = ALIGN_UP(bios_size, alignment);
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